This is done in preparation for D45259.
With D45259, models can specify the size of the reorder buffer, and the retire
throughput directly via tablegen.
llvm-svn: 329274
defaults to the 'IssueWidth' specified by the processor scheduling model.
If width is zero, then the default dispatch width is used.
-.. option:: -max-retire-per-cycle=<retire throughput>
-
- Specify the retire throughput (i.e. how many instructions can be retired by the
- retire control unit every cycle).
-
.. option:: -register-file-size=<size>
Specify the size of the register file. When specified, this flag limits
Backend(const llvm::MCSubtargetInfo &Subtarget,
const llvm::MCRegisterInfo &MRI, InstrBuilder &B, SourceMgr &Source,
unsigned DispatchWidth = 0, unsigned RegisterFileSize = 0,
- unsigned MaxRetirePerCycle = 0, unsigned LoadQueueSize = 0,
- unsigned StoreQueueSize = 0, bool AssumeNoAlias = false)
+ unsigned LoadQueueSize = 0, unsigned StoreQueueSize = 0,
+ bool AssumeNoAlias = false)
: STI(Subtarget), IB(B),
HWS(llvm::make_unique<Scheduler>(this, Subtarget.getSchedModel(),
LoadQueueSize, StoreQueueSize,
AssumeNoAlias)),
DU(llvm::make_unique<DispatchUnit>(
this, STI, MRI, Subtarget.getSchedModel().MicroOpBufferSize,
- RegisterFileSize, MaxRetirePerCycle, DispatchWidth, HWS.get())),
+ RegisterFileSize, DispatchWidth, HWS.get())),
SM(Source), Cycles(0) {
HWS->setDispatchUnit(DU.get());
}
DispatchUnit *Owner;
public:
- RetireControlUnit(unsigned NumSlots, unsigned RPC, DispatchUnit *DU)
+ RetireControlUnit(unsigned NumSlots, DispatchUnit *DU)
: NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
- AvailableSlots(NumSlots), MaxRetirePerCycle(RPC), Owner(DU) {
+ AvailableSlots(NumSlots), MaxRetirePerCycle(0), Owner(DU) {
assert(NumSlots && "Expected at least one slot!");
Queue.resize(NumSlots);
}
public:
DispatchUnit(Backend *B, const llvm::MCSubtargetInfo &STI,
const llvm::MCRegisterInfo &MRI, unsigned MicroOpBufferSize,
- unsigned RegisterFileSize, unsigned MaxRetirePerCycle,
- unsigned MaxDispatchWidth, Scheduler *Sched)
+ unsigned RegisterFileSize, unsigned MaxDispatchWidth,
+ Scheduler *Sched)
: DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
CarryOver(0U), SC(Sched),
RAT(llvm::make_unique<RegisterFile>(STI.getSchedModel(), MRI,
RegisterFileSize)),
- RCU(llvm::make_unique<RetireControlUnit>(MicroOpBufferSize,
- MaxRetirePerCycle, this)),
+ RCU(llvm::make_unique<RetireControlUnit>(MicroOpBufferSize, this)),
Owner(B) {}
unsigned getDispatchWidth() const { return DispatchWidth; }
cl::desc("Dispatch Width. By default it is set equal to IssueWidth"),
cl::init(0));
-static cl::opt<unsigned> MaxRetirePerCycle(
- "max-retire-per-cycle",
- cl::desc("Maximum number of instructions that can be retired in one cycle"),
- cl::init(0));
-
static cl::opt<unsigned>
RegisterFileSize("register-file-size",
cl::desc("Maximum number of temporary registers which can "
}
std::unique_ptr<mca::Backend> B = llvm::make_unique<mca::Backend>(
- *STI, *MRI, *IB, *S, Width, RegisterFileSize, MaxRetirePerCycle,
- LoadQueueSize, StoreQueueSize, AssumeNoAlias);
+ *STI, *MRI, *IB, *S, Width, RegisterFileSize, LoadQueueSize,
+ StoreQueueSize, AssumeNoAlias);
std::unique_ptr<mca::BackendPrinter> Printer =
llvm::make_unique<mca::BackendPrinter>(*B);