drm/amdgpu: use DRM_SCHED_FENCE_DONT_PIPELINE for VM updates

Make sure that we always have a CPU round trip to let the submission
code correctly decide if a TLB flush is necessary or not.

Signed-off-by: Christian König <christian.koenig@amd.com>
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2113#note_1579296
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221014081553.114899-2-christian.koenig@amd.com

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index 1fd3cbc..c7bf189 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -115,8 +115,15 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
                amdgpu_bo_fence(p->vm->root.bo, f, true);
        }
 
-       if (fence && !p->immediate)
+       if (fence && !p->immediate) {
+               /*
+                * Most hw generations now have a separate queue for page table
+                * updates, but when the queue is shared with userspace we need
+                * the extra CPU round trip to correctly flush the TLB.
+                */
+               set_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &f->flags);
                swap(*fence, f);
+       }
        dma_fence_put(f);
        return 0;