drm/nouveau/sw: switch to device pri macros
authorBen Skeggs <bskeggs@redhat.com>
Thu, 20 Aug 2015 04:54:10 +0000 (14:54 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 28 Aug 2015 02:40:19 +0000 (12:40 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c

index b35b459..eade9e3 100644 (file)
@@ -51,19 +51,20 @@ gf100_sw_mthd_mp_control(struct nvkm_object *object, u32 mthd,
 {
        struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
        struct nvkm_sw *sw = (void *)nv_object(chan)->engine;
+       struct nvkm_device *device = sw->engine.subdev.device;
        u32 data = *(u32 *)args;
 
        switch (mthd) {
        case 0x600:
-               nv_wr32(sw, 0x419e00, data); /* MP.PM_UNK000 */
+               nvkm_wr32(device, 0x419e00, data); /* MP.PM_UNK000 */
                break;
        case 0x644:
                if (data & ~0x1ffffe)
                        return -EINVAL;
-               nv_wr32(sw, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */
+               nvkm_wr32(device, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */
                break;
        case 0x6ac:
-               nv_wr32(sw, 0x419eac, data); /* MP.PM_UNK0AC */
+               nvkm_wr32(device, 0x419eac, data); /* MP.PM_UNK0AC */
                break;
        default:
                return -EINVAL;
@@ -100,13 +101,14 @@ gf100_sw_vblsem_release(struct nvkm_notify *notify)
        struct nv50_sw_chan *chan =
                container_of(notify, typeof(*chan), vblank.notify[notify->index]);
        struct nvkm_sw *sw = (void *)nv_object(chan)->engine;
-       struct nvkm_bar *bar = nvkm_bar(sw);
+       struct nvkm_device *device = sw->engine.subdev.device;
+       struct nvkm_bar *bar = device->bar;
 
-       nv_wr32(sw, 0x001718, 0x80000000 | chan->vblank.channel);
+       nvkm_wr32(device, 0x001718, 0x80000000 | chan->vblank.channel);
        bar->flush(bar);
-       nv_wr32(sw, 0x06000c, upper_32_bits(chan->vblank.offset));
-       nv_wr32(sw, 0x060010, lower_32_bits(chan->vblank.offset));
-       nv_wr32(sw, 0x060014, chan->vblank.value);
+       nvkm_wr32(device, 0x06000c, upper_32_bits(chan->vblank.offset));
+       nvkm_wr32(device, 0x060010, lower_32_bits(chan->vblank.offset));
+       nvkm_wr32(device, 0x060014, chan->vblank.value);
 
        return NVKM_NOTIFY_DROP;
 }
index f1bb1e6..3bdab84 100644 (file)
@@ -97,7 +97,7 @@ nv04_sw_cclass = {
 void
 nv04_sw_intr(struct nvkm_subdev *subdev)
 {
-       nv_mask(subdev, 0x000100, 0x80000000, 0x00000000);
+       nvkm_mask(subdev->device, 0x000100, 0x80000000, 0x00000000);
 }
 
 static int
index af2c1af..ab3175a 100644 (file)
@@ -122,18 +122,19 @@ nv50_sw_vblsem_release(struct nvkm_notify *notify)
        struct nv50_sw_chan *chan =
                container_of(notify, typeof(*chan), vblank.notify[notify->index]);
        struct nvkm_sw *sw = (void *)nv_object(chan)->engine;
-       struct nvkm_bar *bar = nvkm_bar(sw);
+       struct nvkm_device *device = sw->engine.subdev.device;
+       struct nvkm_bar *bar = device->bar;
 
-       nv_wr32(sw, 0x001704, chan->vblank.channel);
-       nv_wr32(sw, 0x001710, 0x80000000 | chan->vblank.ctxdma);
+       nvkm_wr32(device, 0x001704, chan->vblank.channel);
+       nvkm_wr32(device, 0x001710, 0x80000000 | chan->vblank.ctxdma);
        bar->flush(bar);
 
        if (nv_device(sw)->chipset == 0x50) {
-               nv_wr32(sw, 0x001570, chan->vblank.offset);
-               nv_wr32(sw, 0x001574, chan->vblank.value);
+               nvkm_wr32(device, 0x001570, chan->vblank.offset);
+               nvkm_wr32(device, 0x001574, chan->vblank.value);
        } else {
-               nv_wr32(sw, 0x060010, chan->vblank.offset);
-               nv_wr32(sw, 0x060014, chan->vblank.value);
+               nvkm_wr32(device, 0x060010, chan->vblank.offset);
+               nvkm_wr32(device, 0x060014, chan->vblank.value);
        }
 
        return NVKM_NOTIFY_DROP;