/* External addresses referenced in a function. Rather than trying to
work relocatable address directly into bytecoded functions (which would
require us to provide hairy location info and possibly obey alignment
- rules imposed by the architecture) we build an auxilary table of
+ rules imposed by the architecture) we build an auxiliary table of
pointer constants, and encode just offsets into this table into the
actual bytecode. */
static struct bc_seg *ptrconsts;
static char *inpoint = NULL;
-/* Safely allocate NBYTES bytes of memory. Reuturns pointer to block of
+/* Safely allocate NBYTES bytes of memory. Returns pointer to block of
memory. */
static char *
The above applies to BYTE_LOW_ENDIAN machines. In BYTE_BIG_ENDIAN machines, the
bit numbering is reversed (i.e. bit 0 is the sign bit).
- (Alright, so I drew this to keep my tongue in cheek while writing the code below,
+ (All right, so I drew this to keep my tongue in cheek while writing the code below,
not because I'm into ASCII art.) */
TEM may equal DECL or it may be a previous decl of the same name. */
tem = pushdecl (decl);
- /* For C and Obective-C, we by default put things in .common when
+ /* For C and Objective-C, we by default put things in .common when
possible. */
DECL_COMMON (tem) = 1;
{
preserve_initializer ();
/* Hack? Set the permanent bit for something that is permanent,
- but not on the permenent obstack, so as to convince
+ but not on the permanent obstack, so as to convince
output_constant_def to make its rtl on the permanent
obstack. */
TREE_PERMANENT (DECL_INITIAL (decl)) = 1;
ITERATOR_BOUND_P (idecl) = 0;
/* we can reset rtl since there is not chance that this expansion */
- /* would be superceded by a higher level one */
+ /* would be superseded by a higher level one */
if (top_level_ixpansion_p ())
DECL_RTL (idecl) = 0;
if (end_note)
\f
/* Record an iterator expansion ("ixpansion") for IDECL.
- The remaining paramters are the notes in the loop entry
+ The remaining parameters are the notes in the loop entry
and exit rtl. */
static void
goto string_constant;
}
ungetc(c, finput);
- /* Fall through to treat '@' as the start of an indentifier. */
+ /* Fall through to treat '@' as the start of an identifier. */
}
case 'A': case 'B': case 'C': case 'D': case 'E':
;
ifobjc
-/* Produces an OBJC_STRING_CST with prehaps more OBJC_STRING_CSTs chained
+/* Produces an OBJC_STRING_CST with perhaps more OBJC_STRING_CSTs chained
onto it. */
objc_string:
OBJC_STRING
| error
/* These are for labeled elements. The syntax for an array element
initializer conflicts with the syntax for an Objective-C message,
- so don't include these productions in the Objective-C grammer. */
+ so don't include these productions in the Objective-C grammar. */
ifc
| '[' expr_no_commas ELLIPSIS expr_no_commas ']' '='
{ set_init_index ($2, $4); }
static tree constructor_index;
/* For an ARRAY_TYPE, this is the end index of the range
- to intitialize with the next element, or NULL in the ordinary case
+ to initialize with the next element, or NULL in the ordinary case
where the element is used just once. */
static tree constructor_range_end;
int type = TREE_CODE_CLASS (code);
int length = tree_code_length[(int) code];
- /* If this code is langauge-specific, we don't know what it will do. */
+ /* If this code is language-specific, we don't know what it will do. */
if ((int) code >= NUM_TREE_CODES)
return 1;
args[i].aligned_regs = (rtx *) alloca (sizeof (rtx)
* args[i].n_aligned_regs);
- /* Structures smaller than a word are aligned to the least signifcant
+ /* Structures smaller than a word are aligned to the least significant
byte (to the right). On a BYTES_BIG_ENDIAN machine, this means we
must skip the empty high order bytes when calculating the bit
offset. */
#else
extern char *sys_errlist[];
#endif
-#else /* HAVE_STERRROR */
+#else /* HAVE_STRERROR */
char *strerror ();
#endif
#else /* VMS */
#undef fopen /* Get back the REAL fopen routine */
/* The gcc-vms-1.42 distribution's header files prototype fopen with two
fixed arguments, which matches ANSI's specification but not VAXCRTL's
- pre-ANSI implmentation. This hack circumvents the mismatch problem. */
+ pre-ANSI implementation. This hack circumvents the mismatch problem. */
FILE *(*vmslib_fopen)() = (FILE *(*)()) fopen;
if (*type == 'w')
/* Some systems use __main in a way incompatible with its use in gcc, in these
cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
give the same symbol without quotes for an alternative entry point. You
- must define both, or niether. */
+ must define both, or neither. */
#ifndef NAME__MAIN
#define NAME__MAIN "__main"
#define SYMBOL__MAIN __main
static int total_attempts, total_merges, total_extras, total_successes;
-/* Define a defulat value for REVERSIBLE_CC_MODE.
+/* Define a default value for REVERSIBLE_CC_MODE.
We can never assume that a condition code mode is safe to reverse unless
the md tells us so. */
#ifndef REVERSIBLE_CC_MODE
/* If we have a PLUS whose second operand is a constant and the
address is not valid, perhaps will can split it up using
the machine-specific way to split large constants. We use
- the first psuedo-reg (one of the virtual regs) as a placeholder;
+ the first pseudo-reg (one of the virtual regs) as a placeholder;
it will not remain in the result. */
if (GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
}
/* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
- make can't possibly match and would supress other optimizations. */
+ make can't possibly match and would suppress other optimizations. */
else if (code == COMPARE)
;
value = SET_SRC (set);
/* Make sure that VALUE doesn't reference X. Replace any
- expliit references with a CLOBBER. If there are any remaining
+ explicit references with a CLOBBER. If there are any remaining
references (rare), don't use the value. */
if (reg_mentioned_p (x, value))
/* Function called via note_stores from reg_dead_at_p.
- If DEST is within [reg_dead_rengno, reg_dead_endregno), set
+ If DEST is within [reg_dead_regno, reg_dead_endregno), set
reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
static void
;********************
;; Bit field instructions, general cases.
-;; "o,d" constraint causes a nonoffsetable memref to match the "o"
+;; "o,d" constraint causes a nonoffsettable memref to match the "o"
;; so that its address is reloaded.
;; (define_insn "extv" ...
linked to procedure descriptors.
Outputting the lineno helps debugging of one line functions as they
would otherwise get no line number at all. Please note that we would
- like to put out last_linenum from final.c, but it is not accesible. */
+ like to put out last_linenum from final.c, but it is not accessible. */
if (write_symbols == SDB_DEBUG)
{
/* Loading and storing HImode or QImode values to and from memory
usually requires a scratch register. The exceptions are loading
QImode and HImode from an aligned address to a general register.
- We also cannot load an unaligned address or a paradodixal SUBREG into an
+ We also cannot load an unaligned address or a paradoxical SUBREG into an
FP register. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
/* Output assembler code to FILE to increment profiler label # LABELNO
for profiling a function entry. Under OSF/1, profiling is enabled
- by simply passing -pg to the assember and linker. */
+ by simply passing -pg to the assembler and linker. */
#define FUNCTION_PROFILER(FILE, LABELNO)
{ extern rtx get_unaligned_address ();
rtx addr = get_unaligned_address (operands[1]);
/* It is possible that one of the registers we got for operands[2]
- might co-incide with that of operands[0] (which is why we made
+ might coincide with that of operands[0] (which is why we made
it TImode). Pick the other one to use as our scratch. */
rtx scratch = gen_rtx (REG, DImode,
REGNO (operands[0]) == REGNO (operands[2])
/* What type of cpu are we compiling for? */
enum processor_type arm_cpu;
-/* Waht type of floating point are we compiling for? */
+/* What type of floating point are we compiling for? */
enum floating_point_type arm_fpu;
/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
multiplication by a power of 2 with the recognizer for a
shift. >=32 is not a valid shift for "asl", so we must try and
output a shift that produces the correct arithmetical result.
- Using lsr #32 is idendical except for the fact that the carry bit
+ Using lsr #32 is identical except for the fact that the carry bit
is not set correctly if we set the flags; but we never use the
carry bit from such an operation, so we can ignore that. */
if (code == ROTATERT)
if (live_regs_mask)
{
/* If we have to push any regs, then we must push lr as well, or
- we won't get a propper return. */
+ we won't get a proper return. */
live_regs_mask |= 0x4000;
emit_multi_reg_push (live_regs_mask);
}
\f
/* If CODE is 'd', then the X is a condition operand and the instruction
should only be executed if the condition is true.
- if CODE is 'D', then the X is a condition operand and the instruciton
+ if CODE is 'D', then the X is a condition operand and the instruction
should only be executed if the condition is false: however, if the mode
of the comparison is CCFPEmode, then always execute the instruction -- we
do this because in these circumstances !GE does not necessarily imply LT;
in these cases the instruction pattern will take care to make sure that
an instruction containing %d will follow, thereby undoing the effects of
- doing this instrucion unconditionally.
+ doing this instruction unconditionally.
If CODE is 'N' then X is a floating point operand that must be negated
before output.
If CODE is 'B' then output a bitwise inverted value of X (a const int).
abort ();
/* When generating the instructions, we never mask out the bits that we
- think will be always zero, then if a mistake has occured somewhere, the
+ think will be always zero, then if a mistake has occurred somewhere, the
assembler will spot it and generate an error. */
/* If the symbol is word aligned then we might be able to reduce the
if (GET_CODE (insn) != JUMP_INSN)
return;
- /* This jump might be paralled with a clobber of the condition codes
+ /* This jump might be paralleled with a clobber of the condition codes
the jump should always come first */
if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
body = XVECEXP (body, 0, 0);
}
/* restore recog_operand (getting the attributes of other insns can
destroy this array, but final.c assumes that it remains intact
- accross this call; since the insn has been recognized already we
+ across this call; since the insn has been recognized already we
call recog direct). */
recog (PATTERN (insn), insn, NULL_PTR);
}
#define MEMORY_MOVE_COST(MODE) 10
/* All address computations that can be done are free, but rtx cost returns
- the same for practically all of them. So we weight the differnt types
+ the same for practically all of them. So we weight the different types
of address here in the order (most pref first):
PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
#define ADDRESS_COST(X) \
/* Condition code information. */
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
return the mode to be used for the comparison.
- CCFPEmode should be used with floating inequalites,
+ CCFPEmode should be used with floating inequalities,
CCFPmode should be used with floating equalities.
- CC_NOOVmode should be used with SImode integer equalites
+ CC_NOOVmode should be used with SImode integer equalities.
CCmode should be used otherwise. */
#define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
; but are if the branch wasn't taken; the effect is to limit the branch
; elimination scanning.
-; NOCOND means that the condition codes are niether altered nor affect the
+; NOCOND means that the condition codes are neither altered nor affect the
; output of this insn
(define_attr "conds" "use,set,clob,jump_clob,nocond"
;; Operand 1 is the destination address in a register (SImode)
;; In both this routine and the next, we must be careful not to spill
-;; a memory address of reg+large_const into a seperate PLUS insn, since this
+;; a memory address of reg+large_const into a separate PLUS insn, since this
;; can generate unrecognizable rtl.
(define_expand "storehi"
")
;; Don't match these patterns if we can use a conditional compare, since they
-;; tell the final prescan branch elimator code that full branch inlining
+;; tell the final prescan branch eliminator code that full branch inlining
;; can't be done.
(define_insn ""
")
;; Don't match these patterns if we can use a conditional compare, since they
-;; tell the final prescan branch elimator code that full branch inlining
+;; tell the final prescan branch eliminator code that full branch inlining
;; can't be done.
(define_insn ""
""
"*
/* If we have an operation where (op x 0) is the identity operation and
- the condtional operator is LT or GE and we are comparing against zero and
+ the conditional operator is LT or GE and we are comparing against zero and
everything is in registers then we can do this in two instructions */
if (operands[3] == const0_rtx
&& GET_CODE (operands[7]) != AND
""
"*
/* If we have an operation where (op x 0) is the identity operation and
- the condtional operator is LT or GE and we are comparing against zero and
+ the conditional operator is LT or GE and we are comparing against zero and
everything is in registers then we can do this in two instructions */
if (operands[5] == const0_rtx
&& GET_CODE (operands[7]) != AND
;; any of our local variables. If we call alloca then this is unsafe
;; since restoring the frame frees the memory, which is not what we want.
;; Sometimes the return might have been targeted by the final prescan:
-;; if so then emit a propper return insn as well.
+;; if so then emit a proper return insn as well.
;; Unfortunately, if the frame pointer is required, we don't know if the
;; current function has any implicit stack pointer adjustments that will
;; be restored by the return: we can't therefore do a tail call.
;; and jump direct to the subroutine. On return from the subroutine
;; execution continues at the branch; this avoids a prefetch stall.
;; We use the length attribute (via short_branch ()) to establish whether or
-;; not this is possible, this is the same asthe sparc does.
+;; not this is possible, this is the same as the sparc does.
(define_peephole
[(parallel[(call (mem:SI (match_operand:SI 0 "" "i"))
%{!mbsd:%{!mxopen:%{!ansi: -D_BSD_C}}}"
#endif
-/* RISCiX has some wierd symbol name munging, that is done to the object module
+/* RISCiX has some weird symbol name munging, that is done to the object module
after assembly, which enables multiple libraries to be supported within
one (possibly shared) library. It basically changes the symbol name of
certain symbols (for example _bcopy is converted to _$bcopy if using BSD)
/* Some systems use __main in a way incompatible with its use in gcc, in these
cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
give the same symbol without quotes for an alternative entry point. You
- must define both, or niether. */
+ must define both, or neither. */
#ifndef NAME__MAIN
#define NAME__MAIN "__gccmain"
#define SYMBOL__MAIN __gccmain
/* Let's keep the stack somewhat aligned. */
#define STACK_BOUNDARY 64
-/* Define this macro if it is advisible to hold scalars in registers
+/* Define this macro if it is advisable to hold scalars in registers
in a wider mode than that declared by the program. In such cases,
the value is constrained to be within the bounds of the declared
type, but kept valid in the wider mode. The signedness of the
(const_string "clobber")))
;;
-;; clipper seems to be a tradional risc processor
+;; clipper seems to be a traditional risc processor
;; we define a functional unit 'memory'
;;
(define_function_unit "memory" 1 1 (eq_attr "type" "load") 4 0)
operands[1] = force_reg (DImode, operands[1]);
}")
-;; If an operand is a MEM but not offsetable, we can't load it into
+;; If an operand is a MEM but not offsettable, we can't load it into
;; a register, so we must force the third alternative to be the one
;; reloaded. Hence we show the first as more expensive.
(define_insn ""
Unit. */
#define TARGET_BMU (target_flags & MASK_BMU)
-/* Optimize to conseverve memory */
+/* Optimize to conserve memory */
#define TARGET_OPTIMIZE_MEMORY (target_flags & MASK_OPTIMIZE_MEMORY)
/* Optimize for maximum speed */
For the 1600 we can decide arbitrarily since there are no machine instructions for them. */
#define WORDS_BIG_ENDIAN 1
-/* number of bits in an addressible storage unit */
+/* number of bits in an addressable storage unit */
#define BITS_PER_UNIT 16
/* Width in bits of a "word", which is the contents of a machine register.
controlled by target switches, then GCC will automatically avoid
using these registers when the target switches are opposed to
them.) If the user tells us there is no BMU, we can't use
- ar0-ar3 for regsiter allocation */
+ ar0-ar3 for register allocation */
#define CONDITIONAL_REGISTER_USAGE \
do \
/* Define the first register to be used for argument passing */
#define FIRST_REG_FOR_FUNCTION_ARG REG_Y
-/* Define the profitablity of saving registers around calls.
- NOTE: For now we turin this off because of a bug in the
+/* Define the profitability of saving registers around calls.
+ NOTE: For now we turn this off because of a bug in the
caller-saves code and also because i'm not sure it is helpful
on the 1610. */
case CONST_DOUBLE: \
return COSTS_N_INSNS (2);
-/* Like CONST_COSTS but applies to nonsonstant RTL expressions.
+/* Like CONST_COSTS but applies to nonconstant RTL expressions.
This can be used, for example to indicate how costly a multiply
instruction is. */
#define RTX_COSTS(X,CODE,OUTER_CODE) \
/* This is how to output an assembler line that says to advance
the location counter to a multiple of 2**LOG bytes. We should
- not have to do any alignemnt since the 1610 is a word machine. */
+ not have to do any alignment since the 1610 is a word machine. */
#define ASM_OUTPUT_ALIGN(FILE,LOG)
/* Define this macro if ASM_OUTPUT_SKIP should not be used in the text section
/* Defining this macro causes the compiler to omit a sign-extend, zero-extend,
or bitwise 'and' instruction that truncates the count of a shift operation
to a width equal to the number of bits needed to represent the size of the
- object being shifted. Do not define this macro unless the trucation applies
- to both shoft operations and bit-field operations (if any). */
+ object being shifted. Do not define this macro unless the truncation applies
+ to both shift operations and bit-field operations (if any). */
/* #define SHIFT_COUNT_TRUNCATED */
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
switch (which_alternative)
{
case 0:
- /* We have to use the move mneumonic otherwise the 1610 will
- attempt to transfer all 32-bits of 'y', 'p' or an accumualtor
+ /* We have to use the move mnemonic otherwise the 1610 will
+ attempt to transfer all 32-bits of 'y', 'p' or an accumulator
, which we don't want */
if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD
|| IS_ACCUM_REG(REGNO(operands[1])))
switch (which_alternative)
{
case 0:
- /* We have to use the move mneumonic otherwise the 1610 will
- attempt to transfer all 32-bits of 'y', 'p' or an accumualtor
+ /* We have to use the move mnemonic otherwise the 1610 will
+ attempt to transfer all 32-bits of 'y', 'p' or an accumulator
, which we don't want */
if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD
|| IS_ACCUM_REG(REGNO(operands[1])))
extern int current_function_calls_alloca; \
/* this conditional is ONLY here because there is a BUG; \
EXIT_IGNORE_STACK is ignored itself when the first part of \
- the condition is true! (atleast in version 1.35) */ \
+ the condition is true! (at least in version 1.35) */ \
/* the 8*10 is for 64 bits of .r5 - .r14 */ \
if (current_function_calls_alloca || (SIZE)>=(256-8*10)) { \
/* use .r4 as a temporary! Ok for now.... */ \
/* Huge exponent*/
if (fraction == 0)
{
- /* Attatched to a zero fraction - means infinity */
+ /* Attached to a zero fraction - means infinity */
dst->class = CLASS_INFINITY;
}
else
tmp->normal_exp = a_normal_exp;
tmp->fraction.ll = -tfraction;
}
- /* and renomalize it */
+ /* and renormalize it */
while (tmp->fraction.ll < IMPLICIT_1 && tmp->fraction.ll)
{
break;
case 'L':
/* 'L' must always be used twice in a single pattern. It generates
- the same lable twice, and then will generate a unique label the
+ the same label twice, and then will generate a unique label the
next time it is used. */
asm_fprintf (file, "tl%d", (lab++) / 2);
break;
;; BIT FIELDS
;; -----------------------------------------------------------------
;; The H8/300 has given 1/8th of its opcode space to bitfield
-;; instuctions so let's use them as well as we can
+;; instructions so let's use them as well as we can
;; BCC and BCS patterns.
extern int current_function_outgoing_args_size;
-/* Compile using char instructins (mvc, nc, oc, xc). On 4341 use this since
+/* Compile using char instructions (mvc, nc, oc, xc). On 4341 use this since
these are more than twice as fast as load-op-store.
On 3090 don't use this since load-op-store is much faster. */
#define WORDS_BIG_ENDIAN 1
-/* Number of bits in an addressible storage unit. */
+/* Number of bits in an addressable storage unit. */
#define BITS_PER_UNIT 8
;;- Machine description for GNU compiler -- System/370 version.
;; Copyright (C) 1989, 1993, 1994 Free Software Foundation, Inc.
;; Contributed by Jan Stein (jan@cd.chalmers.se).
-;; Modifed for MVS C/370 by Dave Pitts (pitts@mcdata.com)
+;; Modified for MVS C/370 by Dave Pitts (pitts@mcdata.com)
;; This file is part of GNU CC.
;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
;; %X -- Print a constant byte integer in hex.
;;
-;; We have a special contraint for pattern matching.
+;; We have a special constraint for pattern matching.
;;
;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
;;
/* Configuration for GNU C-compiler for System/370.
Copyright (C) 1989, 1993 Free Software Foundation, Inc.
Contributed by Jan Stein (jan@cd.chalmers.se).
- Modifed for MVS C/370 by Dave Pitts (pitts@mcdata.com)
+ Modified for MVS C/370 by Dave Pitts (pitts@mcdata.com)
This file is part of GNU CC.
/* Macros used in the machine description to test the flags. */
-/* configure can arrage to make this 2, to force a 486. */
+/* configure can arrange to make this 2, to force a 486. */
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT 0
#endif
register and zero otherwise. On most machines, this default
should be used. Only define this macro to some other expression
if pseudo allocated by `local-alloc.c' end up in memory because
- their hard registers were needed for spill regisers. If this
+ their hard registers were needed for spill registers. If this
macro returns nonzero for those classes, those pseudos will only
be allocated by `global.c', which knows how to reallocate the
pseudo to another register. If there would not be another
for x86 FP registers, but the SDB on x86/svr4 is so completely
broken with respect to FP registers that it is hardly worth thinking
of it as something to strive for compatibility with.
- The verison of x86/svr4 SDB I have at the moment does (partially)
+ The version of x86/svr4 SDB I have at the moment does (partially)
seem to believe that DWARF register number 11 is associated with
the x86 register %st(0), but that's about all. Higher DWARF
register numbers don't seem to be associated with anything in
#undef PCC_BITFIELD_TYPE_MATTERS
#define PCC_BITFIELD_TYPE_MATTERS (maximum_field_alignment == 0)
-/* Define this macro if it is advisible to hold scalars in registers
+/* Define this macro if it is advisable to hold scalars in registers
in a wider mode than that declared by the program. In such cases,
the value is constrained to be within the bounds of the declared
type, but kept valid in the wider mode. The signedness of the
broken with respect to FP registers that it is hardly worth thinking
of it as something to strive for compatibility with.
- The verison of x86/svr4 SDB I have at the moment does (partially)
+ The version of x86/svr4 SDB I have at the moment does (partially)
seem to believe that DWARF register number 11 is associated with
the x86 register %st(0), but that's about all. Higher DWARF
register numbers don't seem to be associated with anything in
;; Signed bitfield extractions come out looking like
;; (shiftrt (sign_extend (shift <Y> <C1>)) <C2>)
;; which we expand poorly as four shift insns.
-;; These patters yeild two shifts:
+;; These patterns yield two shifts:
;; (shiftrt (shift <Y> <C3>) <C4>)
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
/* autoinit.o autolaunches NX applications */
#define STARTFILE_SPEC "-ycrt0.o%s %{mnx:-yoptions/autoinit.o%s}"
-/* libic.a is the PGI intrisic library */
+/* libic.a is the PGI intrinsic library */
/* libpm.o and guard.o are for the performance monitoring modules (ignored) */
/* /usr/lib/noieee contains non-IEEE compliant (but faster) math routines */
#if HAVE_DASH_G
else
leaf_proc_ok = 0;
- /* Even if nobody uses extra parms, can't have leafroc or tail calls if
+ /* Even if nobody uses extra parms, can't have leafproc or tail calls if
argblock, because argblock uses g14 implicitly. */
if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
/* Target machine storage layout. */
/* Define for cross-compilation from a host with a different float format
- or endianess (e.g. VAX, x86). */
+ or endianness (e.g. VAX, x86). */
#define REAL_ARITHMETIC
/* Define this if most significant bit is lowest numbered
#undef EMPTY_FIELD_BOUNDARY
#define EMPTY_FIELD_BOUNDARY 32
-/* Allocation boundry in bits for the code of a function */
+/* Allocation boundary in bits for the code of a function */
#undef FUNCTION_BOUNDARY
#define FUNCTION_BOUNDARY 32
(! symbolic_operand (X, VOIDmode) \
|| ((GET_CODE(X) == SYMBOL_REF) && SYMBOL_REF_FLAG(X)))
-/* hpux8 and later have C++ compatable include files, so do not
+/* hpux8 and later have C++ compatible include files, so do not
pretend they are `extern "C"'. */
#define NO_IMPLICIT_EXTERN_C
divu d1, d0 /* now we have 16 bit divisor */
andl IMM (0xffff), d0 /* mask out divisor, ignore remainder */
-/* Muliply the 16 bit tentative quotient with the 32 bit divisor. Because of
+/* Multiply the 16 bit tentative quotient with the 32 bit divisor. Because of
the operand ranges, this might give a 33 bit product. If this product is
greater than the dividend, the tentative quotient was too large. */
movel d2, d1
| Here we have a's exponent larger than b's, so we have to shift b. We do
| this by using as counter d2:
1: movew d4,d2 | move largest exponent to d2
- subw d5,d2 | and substract second exponent
+ subw d5,d2 | and subtract second exponent
exg d4,a2 | get back the longs we saved
exg d5,a3 |
| if difference is too large we don't shift (actually, we can just exit) '
| Now we have the numbers in d0--d3 and d4--d7, the exponent in a2, and
| the signs in a4.
-| Here we have to decide whether to add or substract the numbers:
+| Here we have to decide whether to add or subtract the numbers:
exg d7,a0 | get the signs
exg d6,a3 | a3 is free to be used
movel d7,d6 |
movew IMM (0),d6 | and b's sign in d6 '
eorl d7,d6 | compare the signs
bmi Lsubdf$0 | if the signs are different we have
- | to substract
+ | to subtract
exg d7,a0 | else we add the numbers
exg d6,a3 |
addl d7,d3 |
| Before rounding normalize so bit #DBL_MANT_DIG is set (we will consider
| the case of denormalized numbers in the rounding routine itself).
-| As in the addition (not in the substraction!) we could have set
+| As in the addition (not in the subtraction!) we could have set
| one more bit we check this:
btst IMM (DBL_MANT_DIG+1),d0
beq 1f
bra Ld$overflow
Lsubdf$0:
-| Here we do the substraction.
+| Here we do the subtraction.
exg d7,a0 | put sign back in a0
exg d6,a3 |
subl d7,d3 |
| Before rounding normalize so bit #DBL_MANT_DIG is set (we will consider
| the case of denormalized numbers in the rounding routine itself).
-| As in the addition (not in the substraction!) we could have set
+| As in the addition (not in the subtraction!) we could have set
| one more bit we check this:
btst IMM (DBL_MANT_DIG+1),d0
beq 1f
3:
| Now comes the check for +/-INFINITY. We know that both are (maybe not
| finite) numbers, but we have to check if both are infinite whether we
-| are adding or substracting them.
+| are adding or subtracting them.
eorl d7,d6 | to check sign bits
bmi 1f
andl IMM (0x80000000),d7 | get (common) sign bit
lsrw IMM (4),d5 |
Lmuldf$2: |
addw d5,d4 | add exponents
- subw IMM (D_BIAS+1),d4 | and substract bias (plus one)
+ subw IMM (D_BIAS+1),d4 | and subtract bias (plus one)
| We are now ready to do the multiplication. The situation is as follows:
| both a and b have bit 52 ( bit 20 of d0 and d2) set (even if they were
swap d5 |
lsrw IMM (4),d5 |
Ldivdf$2: |
- subw d5,d4 | substract exponents
+ subw d5,d4 | subtract exponents
addw IMM (D_BIAS),d4 | and add bias
| We are now ready to do the division. We have prepared things in such a way
dbra d5,1b | and branch back
bra 5f
4: cmpl d1,d3 | here d0==d2, so check d1 and d3
- bhi 3b | if d1 > d2 skip the substraction
+ bhi 3b | if d1 > d2 skip the subtraction
bra 2b | else go do it
5:
| Here we have to start setting the bits in the second long.
dbra d5,1b | and branch back
bra 5f
4: cmpl d1,d3 | here d0==d2, so check d1 and d3
- bhi 3b | if d1 > d2 skip the substraction
+ bhi 3b | if d1 > d2 skip the subtraction
bra 2b | else go do it
5:
| Now go ahead checking until we hit a one, which we store in d2.
| signs are stored in a0 and a1).
Laddsf$3:
-| Here we have to decide whether to add or substract the numbers
+| Here we have to decide whether to add or subtract the numbers
exg d6,a0 | get signs back
exg d7,a1 | and save the exponents
eorl d6,d7 | combine sign bits
bmi Lsubsf$0 | if negative a and b have opposite
- | sign so we actually substract the
+ | sign so we actually subtract the
| numbers
| Here we have both positive or both negative
| Before rounding normalize so bit #FLT_MANT_DIG is set (we will consider
| the case of denormalized numbers in the rounding routine itself).
-| As in the addition (not in the substraction!) we could have set
+| As in the addition (not in the subtraction!) we could have set
| one more bit we check this:
btst IMM (FLT_MANT_DIG+1),d0
beq 1f
Lsubsf$0:
| We are here if a > 0 and b < 0 (sign bits cleared).
-| Here we do the substraction.
+| Here we do the subtraction.
movel d6,d7 | put sign in d7
andl IMM (0x80000000),d7
| Now d0-d1 is positive and the sign bit is in d7.
-| Note that we do not have to normalize, since in the substraction bit
+| Note that we do not have to normalize, since in the subtraction bit
| #FLT_MANT_DIG+1 is never set, and denormalized numbers are handled by
| the rounding routines themselves.
lea Lsubsf$1,a0 | to return from rounding routine
| Note: when adding two floats of the same sign if either one is
| NaN we return NaN without regard to whether the other is finite or
-| not. When substracting them (i.e., when adding two numbers of
+| not. When subtracting them (i.e., when adding two numbers of
| opposite signs) things are more complicated: if both are INFINITY
| we return NaN, if only one is INFINITY and the other is NaN we return
| NaN, but if it is finite we return INFINITY with the corresponding sign.
bhi Lf$inop
| Now comes the check for +/-INFINITY. We know that both are (maybe not
| finite) numbers, but we have to check if both are infinite whether we
-| are adding or substracting them.
+| are adding or subtracting them.
eorl d3,d2 | to check sign bits
bmi 1f
movel d0,d7
lsrw IMM (7),d3 |
Lmulsf$2: |
addw d3,d2 | add exponents
- subw IMM (F_BIAS+1),d2 | and substract bias (plus one)
+ subw IMM (F_BIAS+1),d2 | and subtract bias (plus one)
| We are now ready to do the multiplication. The situation is as follows:
| both a and b have bit FLT_MANT_DIG-1 set (even if they were
beq Ldivsf$b$0 | branch if b is zero
cmpl d6,d0 | is a big?
bhi Ldivsf$inop | if a is NaN return NaN
- beq Ldivsf$inf | if a is INIFINITY we have to check b
+ beq Ldivsf$inf | if a is INFINITY we have to check b
cmpl d6,d1 | now compare b with INFINITY
bhi Ldivsf$inop | if b is NaN return NaN
beq Ldivsf$underflow
swap d3 |
lsrw IMM (7),d3 |
Ldivsf$2: |
- subw d3,d2 | substract exponents
+ subw d3,d2 | subtract exponents
addw IMM (F_BIAS),d2 | and add bias
| We are now ready to do the division. We have prepared things in such a way
/* Likewise, try with not.w */
if (use_movq (i ^ 0xffff))
return NOTW;
- /* This is the only value where neg.w is usefull */
+ /* This is the only value where neg.w is useful */
if (i == -65408)
return NEGW;
/* Try also with swap */
The Plexus port of gcc requires you to use gas ( either 1.3X with COFF
patches or 2.X ), If you use gas 2.X you have to use binutils-2.X.
- With using gas-2.X the Plexus gcc port is now capabable of generating
+ With using gas-2.X the Plexus gcc port is now capable of generating
output suitable for use by gdb-4.X ( send mail to above address for
info on getting gdb patches or other GNU items for the Plexus )
OLDCC=cc -g -A nansi -A cpu,3000 -A runtype,bsd4.3 -A systype,any -DSHORT_ENUM_BUG
# This used to redefine CFLAGS and LIBGCC2_CFLAGS to eliminate the unsupported
-# -g flag from both macros. This gives an undebugable stage1 compiler which
+# -g flag from both macros. This gives an undebuggable stage1 compiler which
# is bad, and it also does the wrong thing if we are cross compiling to a
# target which does support debugging. There is currently no way to avoid
# the -g option that doesn't break something else.
&& op == CONST0_RTX (mode)));
}
-/* Return true if OP is valid to use in the context of logic aritmethic
+/* Return true if OP is valid to use in the context of logic arithmetic
on condition codes. */
int
PUT_OCS_FUNCTION_END (stream);
/* If the last insn isn't a BARRIER, we must write a return insn. This
- should only happen if the function has no prologe and no body. */
+ should only happen if the function has no prologue and no body. */
if (GET_CODE (insn) == NOTE)
insn = prev_nonnote_insn (insn);
if (insn == 0 || GET_CODE (insn) != BARRIER)
/* The bundled ld program needs link editor directives which normally
reside in /lib/default.ld. We'll pass our own copy during the link
- phase because additioal information about extra sections must be added
+ phase because additional information about extra sections must be added
so that gcc generated files will link properly.
--KRG.
*/
start and end boundaries). */
int sdb_label_count = 0;
-/* Next label # for each statment for Silicon Graphics IRIS systems. */
+/* Next label # for each statement for Silicon Graphics IRIS systems. */
int sym_lineno = 0;
/* Non-zero if inside of a function, because the stupid MIPS asm can't
}
else
{
- base_reg_rtx = (rtx)0; /* Make sure these are initialzed */
+ base_reg_rtx = (rtx)0; /* Make sure these are initialized */
base_offset = 0;
}
#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
mips_output_filename (STREAM, NAME)
-/* This is defined so that it can be overriden in iris6.h. */
+/* This is defined so that it can be overridden in iris6.h. */
#define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
do \
{ \
#undef USE_COLLECT2
#define USE_COLLECT2
-/* use this until a newer gdb for NeXTStep21 is availible */
+/* use this until a newer gdb for NeXTStep21 is available */
#define DEFAULT_GDB_EXTENSIONS 0
/* we need the call to __main to start all global destructors and constructors
#define LINK_SPEC \
"%{!shared:-u main} %{static:-a archive} %{g*:-a archive} %{shared:-b}"
-/* hpux8 and later have C++ compatable include files, so do not
+/* hpux8 and later have C++ compatible include files, so do not
pretend they are `extern "C"'. */
#define NO_IMPLICIT_EXTERN_C
unsigned int total_code_bytes;
/* Variables to handle plabels that we discover are necessary at assembly
- output time. They are output after the currrent function. */
+ output time. They are output after the current function. */
struct defer_plab
{
unsigned HOST_WIDE_INT lsb_mask, t;
/* This might not be obvious, but it's at least fast.
- This function is critcal; we don't have the time loops would take. */
+ This function is critical; we don't have the time loops would take. */
lsb_mask = x & -x;
t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
/* Return true iff t is a power of two. */
It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
- adressing modes to be used).
+ addressing modes to be used).
Put X and Z into registers. Then put the entire expression into
a register. */
output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
}
/* This is a pain. You have to be prepared to deal with an
- arbritary address here including pre/post increment/decrement.
+ arbitrary address here including pre/post increment/decrement.
so avoid this in the MD. */
else
mcounts do, _mcount appears to behave differently on the HPPA. It
takes the return address of the caller, the address of this routine,
and the address of the label. Also, it isn't magic, so
- argument registre hsave to be preserved. */
+ argument registers have to be preserved. */
if (profile_flag)
{
int pc_offset, i, arg_offset, basereg, offsetadj;
case TYPE_FPSQRTSGL:
case TYPE_FPSQRTDBL:
/* A fpload can't be issued until one cycle before a
- preceeding arithmetic operation has finished if
+ preceding arithmetic operation has finished if
the target of the fpload is any of the sources
(or destination) of the arithmetic operation. */
return cost - (pa_cpu_attr == PROCESSOR_700) ? 1 : 2;
case TYPE_FPSQRTSGL:
case TYPE_FPSQRTDBL:
/* An ALU flop can't be issued until two cycles before a
- preceeding divide or sqrt operation has finished if
+ preceding divide or sqrt operation has finished if
the target of the ALU flop is any of the sources
(or destination) of the divide or sqrt operation. */
return cost - (pa_cpu_attr == PROCESSOR_700) ? 2 : 4;
case TYPE_FPSQRTSGL:
case TYPE_FPSQRTDBL:
/* A fpload can't be issued until one cycle before a
- preceeding arithmetic operation has finished if
+ preceding arithmetic operation has finished if
the target of the fpload is the destination of the
arithmetic operation. */
return cost - (pa_cpu_attr == PROCESSOR_700) ? 1 : 2;
case TYPE_FPSQRTSGL:
case TYPE_FPSQRTDBL:
/* An ALU flop can't be issued until two cycles before a
- preceeding divide or sqrt operation has finished if
+ preceding divide or sqrt operation has finished if
the target of the ALU flop is also the target of
of the divide or sqrt operation. */
return cost - (pa_cpu_attr == PROCESSOR_700) ? 2 : 4;
instructions!
Because we actually jump into the table, the addresses of each entry
- must stay contant in relation to the beginning of the table (which
+ must stay constant in relation to the beginning of the table (which
itself must stay constant relative to the instruction to jump into
it). I don't believe we can guarantee earlier passes of the compiler
will adhere to those rules.
#define DEFAULT_GDB_EXTENSIONS 1
/* This is the way other stabs-in-XXX tools do things. We will be
- compatable. */
+ compatible. */
#define DBX_BLOCKS_FUNCTION_RELATIVE 1
/* Likewise for linenos.
name *first*... */
#define DBX_FUNCTION_FIRST
-/* Only lables should ever begin in colunm zero. */
+/* Only labels should ever begin in column zero. */
#define ASM_STABS_OP "\t.stabs"
#define ASM_STABN_OP "\t.stabn"
/* target machine storage layout */
/* Define for cross-compilation from a host with a different float format
- or endianess (e.g. VAX, x86). */
+ or endianness (e.g. VAX, x86). */
#define REAL_ARITHMETIC
/* Define this macro if it is advisable to hold scalars in registers
/* Arghh. This is used for stuff in the constant pool; this may include
function addresses on the PA, which during PIC code generation must
- reside in the data space. Unfortuantely, there's no way to determine
+ reside in the data space. Unfortunately, there's no way to determine
if a particular label in the constant pool refers to a function address.
So just force everything into the data space during PIC generation. */
#define SELECT_RTX_SECTION(RTX,MODE) \
/* This is how to output an element of a case-vector that is relative.
This must be defined correctly as it is used when generating PIC code.
- I belive it safe to use the same definition as ASM_OUTPUT_ADDR_VEC_ELT
+ I believe it safe to use the same definition as ASM_OUTPUT_ADDR_VEC_ELT
on the PA since ASM_OUTPUT_ADDR_VEC_ELT uses pc-relative jump instructions
rather than a table of absolute addresses. */
CC=gcc -DUSE_C_ALLOCA -D__inline= -Dbsd4_4
-# BSD on the PA already has ANSI include files which are c++ compatable.
+# BSD on the PA already has ANSI include files which are c++ compatible.
INSTALL_HEADERS=
STMP_FIXPROTO=
}
else /* if (GET_CODE (SET_DEST (exp)) == MEM) */
{
- /* the last else is a bit paranoic, but since nearly all instructions
+ /* the last else is a bit paranoiac, but since nearly all instructions
play with condition codes, it's reasonable! */
CC_STATUS_INIT; /* paranoia*/
char *output_move_quad();
char *output_block_move();
-/* check whther load_fpu_reg or not */
+/* check whether load_fpu_reg or not */
#define LOAD_FPU_REG_P(x) ((x)>=8 && (x)<=11)
#define NO_LOAD_FPU_REG_P(x) ((x)==12 || (x)==13)
#define FPU_REG_P(x) (LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x))
{ "abshi", 128}, \
{ "no-abshi", -128}, \
/* is branching expensive - on a PDP, it's actually really cheap */ \
-/* this is just to play aroound and check what code gcc generates */ \
+/* this is just to play around and check what code gcc generates */ \
{ "branch-expensive", 256}, \
{ "branch-cheap", -256}, \
/* optimize for space instead of time - just in a couple of places */ \
/* Define this if most significant word of a multiword number is numbered. */
#define WORDS_BIG_ENDIAN 1
-/* number of bits in an addressible storage unit */
+/* number of bits in an addressable storage unit */
#define BITS_PER_UNIT 8
/* Width in bits of a "word", which is the contents of a machine register.
operand as its first argument and the constraint letter as its
second operand.
- `Q' is for memory refereces using take more than 1 instruction.
- `R' is for memory refereces which take 1 word for the instruction. */
+ `Q' is for memory references using take more than 1 instruction.
+ `R' is for memory references which take 1 word for the instruction. */
#define EXTRA_CONSTRAINT(OP,CODE) \
((GET_CODE (OP) != MEM) ? 0 \
;; length default is 1 word each
(define_attr "length" "" (const_int 1))
-;; a users asm staement
+;; a user's asm statement
(define_asm_attributes
[(set_attr "type" "unknown")
; all bets are off how long it is - make it 256, forces long jumps
[(set_attr "length" "8,8,8")])
;; maybe fiddle a bit with move_ratio, then
-;; let contraints only accept a register ...
+;; let constraints only accept a register ...
(define_expand "movstrhi"
[(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" "=g,g"))
[(set_attr "length" "6")])
;; make float to int and vice versa
-;; using the cc_status.flag field we coulf probably cut down
+;; using the cc_status.flag field we could probably cut down
;; on seti and setl
;; assume that we are normally in double and integer mode -
;; what do pdp library routines do to fpu mode ?
\f
;;- subtract instructions
;; we don't have to care for constant second
-;; args, since they are cononical plus:xx now!
+;; args, since they are canonical plus:xx now!
;; also for minus:DF ??
(define_insn "subdf3"
output_asm_insn (\"sub %2, %0\", lateoperands);
return \"\";
}"
-;; offsetable memory addresses always are expensive!!!
+;; offsettable memory addresses always are expensive!!!
[(set_attr "length" "3,5,6,8")])
(define_insn "subhi3"
# Normal program, load up register 2
lwz 2,.Lgot(11) # normal GOT address
- b __do_global_ctors # do any C++ global contstructors (which returns to caller)
+ b __do_global_ctors # do any C++ global constructors (which returns to caller)
# We need to relocate the .got2 pointers. Don't load register 2
# Done adjusting pointers, return
.Ldone:
- b __do_global_ctors # do any C++ global contstructors (which returns to caller)
+ b __do_global_ctors # do any C++ global constructors (which returns to caller)
# Routines for saving floating point registers, called by the compiler.
# Called with r11 pointing to the stack header word of the caller of the
long alloca_reg; /* stack/frame register */
long fpr_max = 64 - first_fp_reg; /* # of floating point registers saved */
long gpr_max = 32 - first_reg; /* # of general purpose registers saved */
- long sp_max; /* 1 if the function aquires a stack frame */
+ long sp_max; /* 1 if the function acquires a stack frame */
long lr_max; /* 1 if the function stores the link register */
long cr_max; /* 1 if the function has a CR save word */
long fpscr_max = 0; /* 1 if the function has a FPSCR save word */
;; AIX architecture-independent common-mode multiply (DImode),
;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
-;; R4; results in R3 and somtimes R4; link register always clobbered by bla
+;; R4; results in R3 and sometimes R4; link register always clobbered by bla
;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
;; assumed unused if generating common-mode, so ignore.
(define_insn "mulh_call"
/* The SH has two sorts of general registers, R0 and the rest. R0 can
be used as the destination of some of the arithmetic ops. There are
also some special purpose registers; the T bit register, the
- Procedure Return Register and the Multipy Accumulate Registers. */
+ Procedure Return Register and the Multiply Accumulate Registers. */
enum reg_class
{
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts.
- On the SH, the trapoline looks like
+ On the SH, the trampoline looks like
1 0000 D301 mov.l l1,r3
2 0002 DD02 mov.l l2,r13
3 0004 4D2B jmp @r13
;; we take advantage of the library routines which don't clobber as many
;; registers as a normal function call would.
-;; We must use a psuedo-reg forced to reg 0 in the SET_DEST rather than
+;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
;; hard register 0. If we used hard register 0, then the next instruction
;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
;; gets allocated to a stack slot that needs its address reloaded, then
we need the movcc patterns). It is possible to provide the movcc
patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
- to tell cse that CCFPE mode registers (even pseudoes) are call
+ to tell cse that CCFPE mode registers (even pseudos) are call
clobbered. */
/* ??? This is an experiment. Rather than making changes to cse which may
abort ();
}
- /* Normal case: move the four words in lowest to higest address order. */
+ /* Normal case: move the four words in lowest to highest address order. */
output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]);
(to store insns). This is a bit excessive. Perhaps a different
mechanism would be better here.
- Emit 3 FLUSH instructions to synchonize the data and instruction caches.
+ Emit 3 FLUSH instructions to synchronize the data and instruction caches.
??? v9: We assume the top 32 bits of function addresses are 0. */
Don't change the order of insns emitted here without checking with
the gdb folk first. */
- /* Is the entire register save area offsetable from %sp? */
+ /* Is the entire register save area offsettable from %sp? */
if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
{
if (size <= 4096)
fp_str, size, sp_str);
}
- /* Is the entire register save area offsetable from %sp? */
+ /* Is the entire register save area offsettable from %sp? */
if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
{
size1 = 0;
;; The scan instruction searches from the most significant bit while ffs
;; searches from the least significant bit. The bit index and treatment of
;; zero also differ. It takes at least 7 instructions to get the proper
-;; result. Here is an obvious 8 instruction seequence.
+;; result. Here is an obvious 8 instruction sequence.
(define_insn "ffssi2"
[(set (match_operand:SI 0 "register_operand" "=&r")
;; When the field position and size are constant and the destination
;; is a register, extv and extzv are much slower than a rotate followed
-;; by a bicl or sign extension. Becase we might end up choosing ext[z]v
+;; by a bicl or sign extension. Because we might end up choosing ext[z]v
;; anyway, we can't allow immediate values for the primary source operand.
(define_insn ""
(the static type of the complete object), and then convert back
to the type we want. Until that is done, or until we can
recognize when that is, we cannot do the short cut logic. (mrs) */
- /* Do this, until we can undo any previous convertions. See net35.C
+ /* Do this, until we can undo any previous conversions. See net35.C
for a testcase. */
fixed_type_p = complete_type_p (expr);
consideration the virtual base class pointers that we
stick in before the virtual function table pointer.
- Also, we want just the delta bewteen the most base class
+ Also, we want just the delta between the most base class
that we derived this vfield from and us. */
base_offset = size_binop (PLUS_EXPR,
get_derived_offset (binfo, DECL_CONTEXT (current_fndecl)),
consideration the virtual base class pointers that we
stick in before the virtual function table pointer.
- Also, we want just the delta bewteen the most base class
+ Also, we want just the delta between the most base class
that we derived this vfield from and us. */
base_offset = size_binop (PLUS_EXPR,
get_derived_offset (binfo, DECL_CONTEXT (fndecl)),
return;
}
{
- /* This MUST be overriden, or the class is ill-formed. */
+ /* This MUST be overridden, or the class is ill-formed. */
/* For now, we just make it abstract. */
tree fndecl = TREE_OPERAND (FNADDR_FROM_VTABLE_ENTRY (TREE_VALUE (virtuals)), 0);
tree vfn;
vbases = CLASSTYPE_VBASECLASSES (t);
while (vbases)
{
- /* We might be able to shorten the ammount of work we do by
+ /* We might be able to shorten the amount of work we do by
only doing this for vtables that come from virtual bases
that have differing offsets, but don't want to miss any
entries. */
{
tree item;
- /* Hooray, our cacheing was successful, let's just install the
+ /* Hooray, we successfully cached; let's just install the
cached class_shadowed list, and walk through it to get the
IDENTIFIER_TYPE_VALUEs correct. */
set_class_shadows (previous_class_values);
extern tree opaque_type_node, signature_type_node;
/* Node for "pointer to (virtual) function".
- This may be distinct from ptr_type_node so gdb can distinuish them. */
+ This may be distinct from ptr_type_node so gdb can distinguish them. */
#define vfunc_ptr_type_node \
(flag_vtable_thunks ? vtable_entry_type : ptr_type_node)
extern int flag_alt_external_templates;
-/* Nonzero means implicit template instantatiations are emitted. */
+/* Nonzero means implicit template instantiations are emitted. */
extern int flag_implicit_templates;
/* Nonzero if we want to conserve space in the .o files. We do this
by putting uninitialized data and runtime initialized data into
- .common instead of .data at the expense of not flaging multiple
+ .common instead of .data at the expense of not flagging multiple
definitions. */
extern int flag_conserve_space;
for (shadowed = level->shadowed; shadowed; shadowed = TREE_CHAIN (shadowed))
IDENTIFIER_LOCAL_VALUE (TREE_PURPOSE (shadowed)) = TREE_VALUE (shadowed);
/* If we're leaving a toplevel class, don't bother to do the setting
- of IDENTIFER_CLASS_VALUE to NULL_TREE, since first of all this slot
+ of IDENTIFIER_CLASS_VALUE to NULL_TREE, since first of all this slot
shouldn't even be used when current_class_type isn't set, and second,
- if we don't touch it here, we're able to use the caching effect if the
+ if we don't touch it here, we're able to use the cache effect if the
next time we're entering a class scope, it is the same class. */
if (current_class_depth != 1 || force)
for (shadowed = level->class_shadowed;
#endif
/* Push a tag name NAME for struct/class/union/enum type TYPE.
- Normally put into into the inner-most non-tag-tranparent scope,
+ Normally put into into the inner-most non-tag-transparent scope,
but if GLOBALIZE is true, put it in the inner-most non-class scope.
The latter is needed for implicit declarations. */
{
flag_inline_functions = 0;
#if 0
- /* This causes uneccessary emission of inline functions. */
+ /* This causes unnecessary emission of inline functions. */
flag_default_inline = 0;
#endif
}
expand_expr (build_function_call (lookup_name (get_identifier ("__gc_main"), 0), NULL_TREE),
0, VOIDmode, 0);
#if 0
- /* done at a differnet time */
+ /* done at a different time */
if (flag_rtti)
output_builtin_tdesc_entries ();
#endif
/* Non-zero means warn when the compiler will reorder code. */
int warn_reorder;
-/* Non-zero means warn when sysnthesis behavior differs from Cfront's. */
+/* Non-zero means warn when synthesis behavior differs from Cfront's. */
int warn_synth;
/* Nonzero means `$' can be in an identifier.
/* Nonzero if we want to conserve space in the .o files. We do this
by putting uninitialized data and runtime initialized data into
- .common instead of .data at the expense of not flaging multiple
+ .common instead of .data at the expense of not flagging multiple
definitions. */
int flag_conserve_space;
#if 0
/* This code is going into the compiler, but currently, it makes
- libg++/src/Interger.cc not compile. The problem is that the nice name
+ libg++/src/Integer.cc not compile. The problem is that the nice name
winds up going into the symbol table, and conversion operations look
for the manged name. */
substitute_nice_name (function);
return rval;
/* We do need to push the scope in this case, since CTYPE helps
- determine subsequent intializers (i.e., Foo::Bar x = foo_enum_1;). */
+ determine subsequent initializers (i.e., Foo::Bar x = foo_enum_1;). */
push_nested_class (ctype, 3);
TREE_COMPLEXITY (rval) = current_class_depth;
emit_note (input_filename, lineno);
/* 9.5p5: The initializer of a static member of a class has
- the same acess rights as a member function. */
+ the same access rights as a member function. */
DECL_CLASS_CONTEXT (current_function_decl) = DECL_CONTEXT (decl);
DECL_STATIC_FUNCTION_P (current_function_decl) = 1;
OB_PUTC2 (':', ':');
}
- /* kludge around wierd behavior on g++.brendan/line1.C */
+ /* kludge around weird behavior on g++.brendan/line1.C */
if (TREE_CODE (name) != IDENTIFIER_NODE)
name = DECL_NAME (name);
Shortcomings:
1. The type of the throw and catch must still match
exactly (no support yet for matching base classes)
- 2. Throw specifications of functions still doesnt't work.
+ 2. Throw specifications of functions still don't work.
Cool Things:
1. Destructors are called properly :-)
2. No overhead for the non-exception thrown case.
/* label for the start of the protection region. */
start_protect_label_rtx = pop_label_entry (&false_label_stack);
- /* Cleanup the EH paramater. */
+ /* Cleanup the EH parameter. */
decls = getdecls ();
expand_end_bindings (decls, decls != NULL_TREE, 0);
params=tree_cons (NULL_TREE, integer_zero_node, NULL_TREE);
fcall = build_function_call (BuiltinReturnAddress, params);
return_val_rtx = expand_expr (fcall, NULL_RTX, SImode, 0);
- /* In the return, the new pc is pc+8, as the value comming in is
+ /* In the return, the new pc is pc+8, as the value coming in is
really the address of the call insn, not the next insn. */
emit_move_insn (return_val_rtx, plus_constant(gen_rtx (LABEL_REF,
Pmode,
}
/* is called from expand_exception_blocks () to generate the code in a function
- to "throw" if anything in the function needs to preform a throw.
+ to "throw" if anything in the function needs to perform a throw.
- expands "throw" as the following psuedo code:
+ expands "throw" as the following pseudo code:
throw:
eh = find_first_exception_match (saved_pc);
pointer to the type of the real derived type that we want to
initialize for. This is the case when addr is a pointer to a sub
object of a complete object, and we only want to do part of the
- complete object's initiailzation of vtable pointers. This is done
+ complete object's initialization of vtable pointers. This is done
for all virtual table pointers in virtual base classes. REAL_BINFO
is used to find the BINFO_VTABLE that we initialize with. BINFO is
used for conversions of addr to subobjects.
/* If we want to check the value of the allocation expression,
and the number of elements in the array is not a constant, we
*must* expand the SAVE_EXPR for nelts in alloc_expr before we
- expand it in the actual initalization. So we need to build up
+ expand it in the actual initialization. So we need to build up
an RTL_EXPR for alloc_expr. Sigh. */
if (alloc_expr && ! TREE_CONSTANT (nelts))
{
}
}
- /* Do the actions implied by the preceeding numbers. */
+ /* Do the actions implied by the preceding numbers. */
if (action == act_push)
{
Return -3 if PARENT is private to TYPE, and PROTECT is non-zero.
If PATH_PTR is non-NULL, then also build the list of types
- from PARENT to TYPE, with TREE_VIA_VIRUAL and TREE_VIA_PUBLIC
+ from PARENT to TYPE, with TREE_VIA_VIRTUAL and TREE_VIA_PUBLIC
set.
PARENT can also be a binfo, in which case that exact parent is found
are initializing.
When USE_COMPUTED_OFFSETS is non-zero, we can assume that the
- object was laidout by a top-level contructor and the computed
+ object was laid out by a top-level constructor and the computed
offsets are valid to store vtables. When zero, we must store new
vtables through virtual baseclass pointers.
current_obstack = ambient_obstack;
saveable_obstack = ambient_saveable_obstack;
- /* Ouput debug information for this type. */
+ /* Output debug information for this type. */
rest_of_type_compilation (t, 1);
return t;
resultcode = RDIV_EXPR;
else
/* When dividing two signed integers, we have to promote to int.
- unless we divide by a conatant != -1. Note that default
+ unless we divide by a constant != -1. Note that default
conversion will have been performed on the operands at this
point, so we have to dig out the original type to find out if
it was unsigned. */
return 1;
}
\f
-/* Get differnce in deltas for different pointer to member function
+/* Get difference in deltas for different pointer to member function
types. Return inetger_zero_node, if FROM cannot be converted to a
TO type. If FORCE is true, then allow reverse conversions as well. */
static tree
tree npfn;
tree u;
- /* Handle multiple conversions of pointer to member fucntions. */
+ /* Handle multiple conversions of pointer to member functions. */
if (TYPE_PTRMEMFUNC_P (TREE_TYPE (pfn)))
{
tree ndelta, ndelta2, nindex;
return buf;
}
-/* Open file for xrefing. */
+/* Open file for xreffing. */
static void
open_xref_file(file)
{"compound", ", ", 0}, /* old */
{"cm", ", ", DMGL_ANSI}, /* ansi */
{"cond", "?:", 0}, /* old */
- {"cn", "?:", DMGL_ANSI}, /* psuedo-ansi */
+ {"cn", "?:", DMGL_ANSI}, /* pseudo-ansi */
{"max", ">?", 0}, /* old */
- {"mx", ">?", DMGL_ANSI}, /* psuedo-ansi */
+ {"mx", ">?", DMGL_ANSI}, /* pseudo-ansi */
{"min", "<?", 0}, /* old */
- {"mn", "<?", DMGL_ANSI}, /* psuedo-ansi */
+ {"mn", "<?", DMGL_ANSI}, /* pseudo-ansi */
{"nop", "", 0}, /* old (for operator=) */
{"rm", "->*", DMGL_ANSI} /* ansi */
};
break;
default:
/* it's probably user defined type, let's assume
- it's integeral, it seems hard to figure out
+ it's integral, it seems hard to figure out
what it really is */
done = is_integral = 1;
}
{
/* If we have 10 or more types we might have more than a 1 digit
index so we'll have to consume the whole count here. This
- will loose if the next thing is a type name preceeded by a
+ will lose if the next thing is a type name preceded by a
count but it's impossible to demangle that case properly
anyway. Eg if we already have 12 types is T12Pc "(..., type1,
- anyway. Eg if we already have 12 types is T12Pc "(..., type1,
Pc, ...)" or "(..., type12, char *, ...)" */
if ((t = consume_count(mangled)) == 0)
{
This function expects to see "fname" or <fname> on the input.
The input is normally in part of the output_buffer following
- CPP_WRITTEN, and will get overwriiten by output_line_command.
+ CPP_WRITTEN, and will get overwritten by output_line_command.
I.e. in input file specification has been popped by handle_directive.
This is safe. */
if (CPP_BUFFER (pfile)->nominal_fname && next_buf != 0)
{
/* We're about to return from an #include file.
- Emit #line information now (as part of the CPP_POP) restult.
+ Emit #line information now (as part of the CPP_POP) result.
But the #line refers to the file we will pop to. */
cpp_buffer *cur_buffer = CPP_BUFFER (pfile);
CPP_BUFFER (pfile) = next_buf;
#else
extern char *sys_errlist[];
#endif
-#else /* HAVE_STERRROR */
+#else /* HAVE_STRERROR */
char *strerror ();
#endif
#else /* VMS */
char for_lint;
/* Nonzero means handle CHILL comment syntax
- and output CHILL string delimeter for __DATE___ etc. */
+ and output CHILL string delimiter for __DATE___ etc. */
char chill;
projects / platform / upstream / linaro-gcc.git / commitdiff