[AArch64] Allow MOVPRFX to be used with FMOV

The entry for the FMOV alias of FCPY was missing C_SCAN_MOVPRFX.
(The entry for FCPY itself was OK.)

This was the only /m-predicated instruction I could see that was
missing the flag.

2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
	SVE FMOV alias of FCPY.

gas/
	* testsuite/gas/aarch64/sve-movprfx_27.s,
	* testsuite/gas/aarch64/sve-movprfx_27.d: New test.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3a76a05..f3fe16a 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 
+       * testsuite/gas/aarch64/sve-movprfx_27.s,
+       * testsuite/gas/aarch64/sve-movprfx_27.d: New test.
+
+2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
+
        * testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
        SCVTF, UCVTF, LSR and ASR.
        * testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.

diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_27.d b/gas/testsuite/gas/aarch64/sve-movprfx_27.d
new file mode 100644 (file)
index 0000000..ef0bc9a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_27.d
@@ -0,0 +1,14 @@
+#source: sve-movprfx_27.s
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+: 0420bc20        movprfx z0, z1
+[^:]+: 0590ce00        fmov    z0.s, p0/m, #1.0+(e\+00)?
+[^:]+: 0420bc20        movprfx z0, z1
+[^:]+: 0590ce00        fmov    z0.s, p0/m, #1.0+(e\+00)?
+[^:]+: d65f03c0        ret

diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_27.s b/gas/testsuite/gas/aarch64/sve-movprfx_27.s
new file mode 100644 (file)
index 0000000..bb4d3a7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-movprfx_27.s
@@ -0,0 +1,11 @@
+       .text
+       .arch armv8-a+sve
+
+f:
+       movprfx z0, z1
+       fmov z0.s, p0/m, #1.0
+
+       movprfx z0, z1
+       fcpy z0.s, p0/m, #1.0
+
+       ret

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 064e48e..882ab3f 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 
+       * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
+       SVE FMOV alias of FCPY.
+
+2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
+
        * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
        to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 6216750..ee36f1c 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3809,7 +3809,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("ble", 0x5400000d, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO),
   /* SVE instructions.  */
   _SVE_INSN ("fmov", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_ALIAS, 0),
-  _SVE_INSN ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, 0),
+  _SVE_INSNC ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("mov", 0x04603000, 0xffe0fc00, sve_misc, OP_MOV_Z_Z, OP2 (SVE_Zd, SVE_Zn), OP_SVE_DD, F_ALIAS | F_MISC, 0),
   _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
   _SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0),