ARM: dts: rockchip: Add device tree for rk3288-veyron-mighty
authorDouglas Anderson <dianders@chromium.org>
Mon, 25 Mar 2019 16:20:05 +0000 (09:20 -0700)
committerHeiko Stuebner <heiko@sntech.de>
Wed, 27 Mar 2019 12:17:01 +0000 (13:17 +0100)
Mighty is basically the same Chromebook as Jaq but it has a full-sized
SD slot and some different (slightly more rugged) plastics around it.
Like Jaq, Mighty may show up with various different brandings but all
of them have the same board inside.

In the downstream kernel Mighty and Jaq share a "dtsi" and Mighty just
adds the SD write protect (needed for a full-sized SD slot).  We'll do
this upstream by just including the Jaq dts and make the changes.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/rk3288-veyron-mighty.dts [new file with mode: 0644]

index f4f5aea..48282eb 100644 (file)
@@ -909,6 +909,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
        rk3288-veyron-jaq.dtb \
        rk3288-veyron-jerry.dtb \
        rk3288-veyron-mickey.dtb \
+       rk3288-veyron-mighty.dtb \
        rk3288-veyron-minnie.dtb \
        rk3288-veyron-pinky.dtb \
        rk3288-veyron-speedy.dtb \
diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rk3288-veyron-mighty.dts
new file mode 100644 (file)
index 0000000..f640857
--- /dev/null
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Veyron Mighty Rev 1+ board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ */
+
+/dts-v1/;
+
+#include "rk3288-veyron-jaq.dts"
+
+/ {
+       model = "Google Mighty";
+       compatible = "google,veyron-mighty-rev5", "google,veyron-mighty-rev4",
+                    "google,veyron-mighty-rev3", "google,veyron-mighty-rev2",
+                    "google,veyron-mighty-rev1", "google,veyron-mighty",
+                    "google,veyron", "rockchip,rk3288";
+};
+
+&sdmmc {
+       pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+                       &sdmmc_wp_gpio &sdmmc_bus4>;
+       wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
+
+       /delete-property/ disable-wp;
+};
+
+&pinctrl {
+       sdmmc {
+               sdmmc_wp_gpio: sdmmc-wp-gpio {
+                       rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+};