--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <stm32f7-u-boot.dtsi>
+/{
+ chosen {
+ bootargs = "root=/dev/mmcblk0p1 rw rootwait";
+ };
+
+ aliases {
+ /* Aliases for gpios so as to use sequence */
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ mmc0 = &sdio;
+ spi0 = &qspi;
+ };
+
+ button1 {
+ compatible = "st,button1";
+ button-gpio = <&gpioc 13 0>;
+ };
+
+ led1 {
+ compatible = "st,led1";
+ led-gpio = <&gpiof 10 0>;
+ };
+};
+
+&fmc {
+ /*
+ * Memory configuration from sdram datasheet IS42S32800G-6BLI
+ */
+ bank1: bank@0 {
+ u-boot,dm-pre-reloc;
+ st,sdram-control = /bits/ 8 <NO_COL_9
+ NO_ROW_12
+ MWIDTH_32
+ BANKS_4
+ CAS_2
+ SDCLK_3
+ RD_BURST_EN
+ RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1
+ TXSR_1
+ TRAS_1
+ TRC_6
+ TRP_2
+ TWR_1
+ TRCD_1>;
+ st,sdram-refcount = <1539>;
+ };
+};
+
+&mac {
+ phy-mode = "mii";
+};
+
+&pinctrl {
+ ethernet_mii: mii@0 {
+ pins {
+ pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+ <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
+ <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+ <STM32F746_PA2_FUNC_ETH_MDIO>,
+ <STM32F746_PC1_FUNC_ETH_MDC>,
+ <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+ <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+ <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+ <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
+ slew-rate = <2>;
+ };
+ };
+
+ fmc_pins: fmc@0 {
+ pins {
+ pinmux = <STM32F746_PI10_FUNC_FMC_D31>, /* FMC_D31 */
+ <STM32F746_PI9_FUNC_FMC_D30>, /* FMC_D30*/
+ <STM32F746_PI7_FUNC_FMC_D29>, /* FMC_D29 */
+ <STM32F746_PI6_FUNC_FMC_D28>, /* FMC_D28 */
+ <STM32F746_PI3_FUNC_FMC_D27>, /* FMC_D27 */
+ <STM32F746_PI2_FUNC_FMC_D26>, /* FMC_D26 */
+ <STM32F746_PI1_FUNC_FMC_D25>, /* FMC_D25 */
+ <STM32F746_PI0_FUNC_FMC_D24>, /* FMC_D24 */
+ <STM32F746_PH15_FUNC_FMC_D23>, /* FMC_D23 */
+ <STM32F746_PH14_FUNC_FMC_D22>, /* FMC_D22 */
+ <STM32F746_PH13_FUNC_FMC_D21>, /* FMC_D21 */
+ <STM32F746_PH12_FUNC_FMC_D20>, /* FMC_D20 */
+ <STM32F746_PH11_FUNC_FMC_D19>, /* FMC_D19 */
+ <STM32F746_PH10_FUNC_FMC_D18>, /* FMC_D18 */
+ <STM32F746_PH9_FUNC_FMC_D17>, /* FMC_D17 */
+ <STM32F746_PH8_FUNC_FMC_D16>, /* FMC_D16 */
+
+ <STM32F746_PD10_FUNC_FMC_D15>, /* FMC_D15 */
+ <STM32F746_PD9_FUNC_FMC_D14>, /* FMC_D14*/
+ <STM32F746_PD8_FUNC_FMC_D13>, /* FMC_D13 */
+ <STM32F746_PE15_FUNC_FMC_D12>,/* FMC_D12 */
+ <STM32F746_PE14_FUNC_FMC_D11>,/* FMC_D11 */
+ <STM32F746_PE13_FUNC_FMC_D10>,/* FMC_D10 */
+ <STM32F746_PE12_FUNC_FMC_D9>, /* FMC_D9 */
+ <STM32F746_PE11_FUNC_FMC_D8>, /* FMC_D8 */
+ <STM32F746_PE10_FUNC_FMC_D7>, /* FMC_D7 */
+ <STM32F746_PE9_FUNC_FMC_D6>, /* FMC_D6 */
+ <STM32F746_PE8_FUNC_FMC_D5>, /* FMC_D5*/
+ <STM32F746_PE7_FUNC_FMC_D4>, /* FMC_D4 */
+ <STM32F746_PD1_FUNC_FMC_D3>, /* FMC_D3 */
+ <STM32F746_PD0_FUNC_FMC_D2>, /* FMC_D2 */
+ <STM32F746_PD15_FUNC_FMC_D1>, /* FMC_D1 */
+ <STM32F746_PD14_FUNC_FMC_D0>, /* FMC_D0 */
+
+ <STM32F746_PI5_FUNC_FMC_NBL3>, /* FMC_NBL3 */
+ <STM32F746_PI4_FUNC_FMC_NBL2>, /* FMC_NBL2 */
+ <STM32F746_PE1_FUNC_FMC_NBL1>, /* FMC_NBL1 */
+ <STM32F746_PE0_FUNC_FMC_NBL0>, /* FMC_NBL0 */
+
+ <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, /* FMC_A15 FMC_BA1 */
+ <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, /* FMC_A14 FMC_BA0*/
+
+ <STM32F746_PG1_FUNC_FMC_A11>, /* FMC_A11 */
+ <STM32F746_PG0_FUNC_FMC_A10>, /* FMC_A10 */
+ <STM32F746_PF15_FUNC_FMC_A9>, /* FMC_A9 */
+ <STM32F746_PF14_FUNC_FMC_A8>, /* FMC_A8 */
+ <STM32F746_PF13_FUNC_FMC_A7>, /* FMC_A7 */
+ <STM32F746_PF12_FUNC_FMC_A6>, /* FMC_A6 */
+ <STM32F746_PF5_FUNC_FMC_A5>, /* FUNC_FMC_A5 */
+ <STM32F746_PF4_FUNC_FMC_A4>, /* FMC_A4 */
+ <STM32F746_PF3_FUNC_FMC_A3>, /* FMC_A3 */
+ <STM32F746_PF2_FUNC_FMC_A2>, /* FMC_A2 */
+ <STM32F746_PF1_FUNC_FMC_A1>, /* FMC_A1 */
+ <STM32F746_PF0_FUNC_FMC_A0>, /* FMC_A0 */
+
+ <STM32F746_PH3_FUNC_FMC_SDNE0>,/* FMC_SDNE0 */
+ <STM32F746_PH5_FUNC_FMC_SDNWE>, /* FMC_SDNWE */
+ <STM32F746_PF11_FUNC_FMC_SDNRAS>, /* FMC_SDNRAS */
+ <STM32F746_PG15_FUNC_FMC_SDNCAS>, /* FMC_SDNCAS */
+ <STM32F746_PH2_FUNC_FMC_SDCKE0>, /* FMC_SDCKE0 */
+ <STM32F746_PG8_FUNC_FMC_SDCLK>; /* FMC_SDCLK */
+ slew-rate = <2>;
+ };
+ };
+
+ qspi_pins: qspi@0 {
+ pins {
+ pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
+ <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
+ <STM32F746_PF8_FUNC_QUADSPI_BK1_IO0>,
+ <STM32F746_PF9_FUNC_QUADSPI_BK1_IO1>,
+ <STM32F746_PF6_FUNC_QUADSPI_BK1_IO3>,
+ <STM32F746_PF7_FUNC_QUADSPI_BK1_IO2>;
+ slew-rate = <2>;
+ };
+ };
+};
+
+&qspi {
+ qflash0: n25q512a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <108000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ reg = <0>;
+ };
+};
compatible = "st,stm32f746g-eval", "st,stm32f746";
chosen {
- bootargs = "root=/dev/mmcblk0p1 rw rootwait";
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &usart1;
- spi0 = &qspi;
- mmc0 = &sdio;
- /* Aliases for gpios so as to use sequence */
- gpio0 = &gpioa;
- gpio1 = &gpiob;
- gpio2 = &gpioc;
- gpio3 = &gpiod;
- gpio4 = &gpioe;
- gpio5 = &gpiof;
- gpio6 = &gpiog;
- gpio7 = &gpioh;
- gpio8 = &gpioi;
- gpio9 = &gpioj;
- gpio10 = &gpiok;
- };
-
- led1 {
- compatible = "st,led1";
- led-gpio = <&gpiof 10 0>;
- };
-
- button1 {
- compatible = "st,button1";
- button-gpio = <&gpioc 13 0>;
};
};
&pinctrl {
usart1_pins_a: usart1@0 {
pins1 {
- pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
+ pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
bias-disable;
};
};
-
- ethernet_mii: mii@0 {
- pins {
- pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
- <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
- <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
- <STM32F746_PA2_FUNC_ETH_MDIO>,
- <STM32F746_PC1_FUNC_ETH_MDC>,
- <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
- <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
- <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
- <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
- slew-rate = <2>;
- };
- };
-
- fmc_pins: fmc@0 {
- pins {
- pinmux = <STM32F746_PI10_FUNC_FMC_D31>, /* FMC_D31 */
- <STM32F746_PI9_FUNC_FMC_D30>, /* FMC_D30*/
- <STM32F746_PI7_FUNC_FMC_D29>, /* FMC_D29 */
- <STM32F746_PI6_FUNC_FMC_D28>, /* FMC_D28 */
- <STM32F746_PI3_FUNC_FMC_D27>, /* FMC_D27 */
- <STM32F746_PI2_FUNC_FMC_D26>, /* FMC_D26 */
- <STM32F746_PI1_FUNC_FMC_D25>, /* FMC_D25 */
- <STM32F746_PI0_FUNC_FMC_D24>, /* FMC_D24 */
- <STM32F746_PH15_FUNC_FMC_D23>, /* FMC_D23 */
- <STM32F746_PH14_FUNC_FMC_D22>, /* FMC_D22 */
- <STM32F746_PH13_FUNC_FMC_D21>, /* FMC_D21 */
- <STM32F746_PH12_FUNC_FMC_D20>, /* FMC_D20 */
- <STM32F746_PH11_FUNC_FMC_D19>, /* FMC_D19 */
- <STM32F746_PH10_FUNC_FMC_D18>, /* FMC_D18 */
- <STM32F746_PH9_FUNC_FMC_D17>, /* FMC_D17 */
- <STM32F746_PH8_FUNC_FMC_D16>, /* FMC_D16 */
-
- <STM32F746_PD10_FUNC_FMC_D15>, /* FMC_D15 */
- <STM32F746_PD9_FUNC_FMC_D14>, /* FMC_D14*/
- <STM32F746_PD8_FUNC_FMC_D13>, /* FMC_D13 */
- <STM32F746_PE15_FUNC_FMC_D12>,/* FMC_D12 */
- <STM32F746_PE14_FUNC_FMC_D11>,/* FMC_D11 */
- <STM32F746_PE13_FUNC_FMC_D10>,/* FMC_D10 */
- <STM32F746_PE12_FUNC_FMC_D9>, /* FMC_D9 */
- <STM32F746_PE11_FUNC_FMC_D8>, /* FMC_D8 */
- <STM32F746_PE10_FUNC_FMC_D7>, /* FMC_D7 */
- <STM32F746_PE9_FUNC_FMC_D6>, /* FMC_D6 */
- <STM32F746_PE8_FUNC_FMC_D5>, /* FMC_D5*/
- <STM32F746_PE7_FUNC_FMC_D4>, /* FMC_D4 */
- <STM32F746_PD1_FUNC_FMC_D3>, /* FMC_D3 */
- <STM32F746_PD0_FUNC_FMC_D2>, /* FMC_D2 */
- <STM32F746_PD15_FUNC_FMC_D1>, /* FMC_D1 */
- <STM32F746_PD14_FUNC_FMC_D0>, /* FMC_D0 */
-
- <STM32F746_PI5_FUNC_FMC_NBL3>, /* FMC_NBL3 */
- <STM32F746_PI4_FUNC_FMC_NBL2>, /* FMC_NBL2 */
- <STM32F746_PE1_FUNC_FMC_NBL1>, /* FMC_NBL1 */
- <STM32F746_PE0_FUNC_FMC_NBL0>, /* FMC_NBL0 */
-
- <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, /* FMC_A15 FMC_BA1 */
- <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, /* FMC_A14 FMC_BA0*/
-
- <STM32F746_PG1_FUNC_FMC_A11>, /* FMC_A11 */
- <STM32F746_PG0_FUNC_FMC_A10>, /* FMC_A10 */
- <STM32F746_PF15_FUNC_FMC_A9>, /* FMC_A9 */
- <STM32F746_PF14_FUNC_FMC_A8>, /* FMC_A8 */
- <STM32F746_PF13_FUNC_FMC_A7>, /* FMC_A7 */
- <STM32F746_PF12_FUNC_FMC_A6>, /* FMC_A6 */
- <STM32F746_PF5_FUNC_FMC_A5>, /* FUNC_FMC_A5 */
- <STM32F746_PF4_FUNC_FMC_A4>, /* FMC_A4 */
- <STM32F746_PF3_FUNC_FMC_A3>, /* FMC_A3 */
- <STM32F746_PF2_FUNC_FMC_A2>, /* FMC_A2 */
- <STM32F746_PF1_FUNC_FMC_A1>, /* FMC_A1 */
- <STM32F746_PF0_FUNC_FMC_A0>, /* FMC_A0 */
-
- <STM32F746_PH3_FUNC_FMC_SDNE0>,/* FMC_SDNE0 */
- <STM32F746_PH5_FUNC_FMC_SDNWE>, /* FMC_SDNWE */
- <STM32F746_PF11_FUNC_FMC_SDNRAS>, /* FMC_SDNRAS */
- <STM32F746_PG15_FUNC_FMC_SDNCAS>, /* FMC_SDNCAS */
- <STM32F746_PH2_FUNC_FMC_SDCKE0>, /* FMC_SDCKE0 */
- <STM32F746_PG8_FUNC_FMC_SDCLK>; /* FMC_SDCLK */
- slew-rate = <2>;
- };
- };
};
&usart1 {
status = "okay";
};
-&mac {
- status = "okay";
- pinctrl-0 = <ðernet_mii>;
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&fmc {
- pinctrl-0 = <&fmc_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /*
- * Memory configuration from sdram datasheet IS42S32800G-6BLI
- */
- bank1: bank@0 {
- st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
- CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
- st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
- TWR_1 TRCD_1>;
- st,sdram-refcount = <1539>;
- };
-};
-
&sdio {
status = "okay";
pinctrl-names = "default", "opendrain";
+// SPDX-License-Identifier: GPL-2.0+
+
/{
soc {
- timer5: timer@40000c00 {
+ u-boot,dm-pre-reloc;
+
+ fmc: fmc@A0000000 {
+ compatible = "st,stm32-fmc";
+ reg = <0xA0000000 0x1000>;
+ clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
+ pinctrl-0 = <&fmc_pins>;
+ pinctrl-names = "default";
+ status = "okay";
u-boot,dm-pre-reloc;
};
+
+ mac: ethernet@40028000 {
+ compatible = "st,stm32-dwmac";
+ reg = <0x40028000 0x8000>;
+ reg-names = "stmmaceth";
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
+ <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
+ <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
+ interrupts = <61>, <62>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ snps,pbl = <8>;
+ snps,mixed-burst;
+ dma-ranges;
+ pinctrl-0 = <ðernet_mii>;
+ phy-mode = "rmii";
+ phy-handle = <&phy0>;
+
+ status = "okay";
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+ };
+
+ qspi: quadspi@A0001000 {
+ compatible = "st,stm32-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
+ reg-names = "qspi", "qspi_mm";
+ interrupts = <92>;
+ spi-max-frequency = <108000000>;
+ clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
+ resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
+ pinctrl-0 = <&qspi_pins>;
+
+ status = "okay";
+ };
};
};
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+ compatible = "st,stm32-gpio";
+};
+
+&gpiok {
+ compatible = "st,stm32-gpio";
+};
+
&pinctrl {
+ u-boot,dm-pre-reloc;
+
+ fmc_pins: fmc@0 {
+ u-boot,dm-pre-reloc;
+ pins
+ {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
usart1_pins_a: usart1@0 {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
};
- fmc_pins: fmc@0 {
- u-boot,dm-pre-reloc;
- pins
- {
- u-boot,dm-pre-reloc;
- };
- };
};
-&fmc {
- bank1: bank@0 {
- u-boot,dm-pre-reloc;
- };
+&pwrcfg {
+ u-boot,dm-pre-reloc;
};
-&pwrcfg {
+&rcc {
u-boot,dm-pre-reloc;
};
-&clk_hse {
+&timer5 {
+ u-boot,dm-pre-reloc;
+};
+
+&usart1 {
u-boot,dm-pre-reloc;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <stm32f7-u-boot.dtsi>
+/{
+ chosen {
+ bootargs = "root=/dev/ram rdinit=/linuxrc";
+ };
+
+ aliases {
+ /* Aliases for gpios so as to use sequence */
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ mmc0 = &sdio;
+ spi0 = &qspi;
+ };
+
+ backlight: backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiok 3 0>;
+ status = "okay";
+ };
+
+ button1 {
+ compatible = "st,button1";
+ button-gpio = <&gpioi 11 0>;
+ };
+
+ led1 {
+ compatible = "st,led1";
+ led-gpio = <&gpioi 1 0>;
+ };
+
+ panel-rgb@0 {
+ compatible = "simple-panel";
+ backlight = <&backlight>;
+ enable-gpios = <&gpioi 12 0>;
+ status = "okay";
+
+ display-timings {
+ timing@0 {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <2>;
+ hback-porch = <2>;
+ hsync-len = <41>;
+ vfront-porch = <2>;
+ vback-porch = <2>;
+ vsync-len = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <0>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
+
+ soc {
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+ pinctrl-0 = <<dc_pins>;
+
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
+
+&fmc {
+ /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
+ bank1: bank@0 {
+ u-boot,dm-pre-reloc;
+ st,sdram-control = /bits/ 8 <NO_COL_8
+ NO_ROW_12
+ MWIDTH_16
+ BANKS_4
+ CAS_3
+ SDCLK_2
+ RD_BURST_EN
+ RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_2
+ TXSR_6
+ TRAS_4
+ TRC_6
+ TWR_2
+ TRP_2
+ TRCD_2>;
+ /* refcount = (64msec/total_row_sdram)*freq - 20 */
+ st,sdram-refcount = < 1542 >;
+ };
+};
+
+&pinctrl {
+ ethernet_mii: mii@0 {
+ pins {
+ pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+ <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
+ <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+ <STM32F746_PA2_FUNC_ETH_MDIO>,
+ <STM32F746_PC1_FUNC_ETH_MDC>,
+ <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+ <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+ <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+ <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
+ slew-rate = <2>;
+ };
+ };
+
+ fmc_pins: fmc@0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
+ <STM32F746_PD9_FUNC_FMC_D14>,
+ <STM32F746_PD8_FUNC_FMC_D13>,
+ <STM32F746_PE15_FUNC_FMC_D12>,
+ <STM32F746_PE14_FUNC_FMC_D11>,
+ <STM32F746_PE13_FUNC_FMC_D10>,
+ <STM32F746_PE12_FUNC_FMC_D9>,
+ <STM32F746_PE11_FUNC_FMC_D8>,
+ <STM32F746_PE10_FUNC_FMC_D7>,
+ <STM32F746_PE9_FUNC_FMC_D6>,
+ <STM32F746_PE8_FUNC_FMC_D5>,
+ <STM32F746_PE7_FUNC_FMC_D4>,
+ <STM32F746_PD1_FUNC_FMC_D3>,
+ <STM32F746_PD0_FUNC_FMC_D2>,
+ <STM32F746_PD15_FUNC_FMC_D1>,
+ <STM32F746_PD14_FUNC_FMC_D0>,
+
+ <STM32F746_PE1_FUNC_FMC_NBL1>,
+ <STM32F746_PE0_FUNC_FMC_NBL0>,
+
+ <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
+ <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
+
+ <STM32F746_PG1_FUNC_FMC_A11>,
+ <STM32F746_PG0_FUNC_FMC_A10>,
+ <STM32F746_PF15_FUNC_FMC_A9>,
+ <STM32F746_PF14_FUNC_FMC_A8>,
+ <STM32F746_PF13_FUNC_FMC_A7>,
+ <STM32F746_PF12_FUNC_FMC_A6>,
+ <STM32F746_PF5_FUNC_FMC_A5>,
+ <STM32F746_PF4_FUNC_FMC_A4>,
+ <STM32F746_PF3_FUNC_FMC_A3>,
+ <STM32F746_PF2_FUNC_FMC_A2>,
+ <STM32F746_PF1_FUNC_FMC_A1>,
+ <STM32F746_PF0_FUNC_FMC_A0>,
+
+ <STM32F746_PH3_FUNC_FMC_SDNE0>,
+ <STM32F746_PH5_FUNC_FMC_SDNWE>,
+ <STM32F746_PF11_FUNC_FMC_SDNRAS>,
+ <STM32F746_PG15_FUNC_FMC_SDNCAS>,
+ <STM32F746_PC3_FUNC_FMC_SDCKE0>,
+ <STM32F746_PG8_FUNC_FMC_SDCLK>;
+ slew-rate = <2>;
+ };
+ };
+
+ ltdc_pins: ltdc@0 {
+ pins {
+ pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
+ <STM32F746_PG12_FUNC_LCD_B4>,
+ <STM32F746_PI9_FUNC_LCD_VSYNC>,
+ <STM32F746_PI10_FUNC_LCD_HSYNC>,
+ <STM32F746_PI14_FUNC_LCD_CLK>,
+ <STM32F746_PI15_FUNC_LCD_R0>,
+ <STM32F746_PJ0_FUNC_LCD_R1>,
+ <STM32F746_PJ1_FUNC_LCD_R2>,
+ <STM32F746_PJ2_FUNC_LCD_R3>,
+ <STM32F746_PJ3_FUNC_LCD_R4>,
+ <STM32F746_PJ4_FUNC_LCD_R5>,
+ <STM32F746_PJ5_FUNC_LCD_R6>,
+ <STM32F746_PJ6_FUNC_LCD_R7>,
+ <STM32F746_PJ7_FUNC_LCD_G0>,
+ <STM32F746_PJ8_FUNC_LCD_G1>,
+ <STM32F746_PJ9_FUNC_LCD_G2>,
+ <STM32F746_PJ10_FUNC_LCD_G3>,
+ <STM32F746_PJ11_FUNC_LCD_G4>,
+ <STM32F746_PJ13_FUNC_LCD_B1>,
+ <STM32F746_PJ14_FUNC_LCD_B2>,
+ <STM32F746_PJ15_FUNC_LCD_B3>,
+ <STM32F746_PK0_FUNC_LCD_G5>,
+ <STM32F746_PK1_FUNC_LCD_G6>,
+ <STM32F746_PK2_FUNC_LCD_G7>,
+ <STM32F746_PK4_FUNC_LCD_B5>,
+ <STM32F746_PK5_FUNC_LCD_B6>,
+ <STM32F746_PK6_FUNC_LCD_B7>,
+ <STM32F746_PK7_FUNC_LCD_DE>;
+ slew-rate = <2>;
+ };
+ };
+
+ qspi_pins: qspi@0 {
+ pins {
+ pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
+ <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
+ <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
+ <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
+ <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
+ <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
+ slew-rate = <2>;
+ };
+ };
+
+ usart1_pins_a: usart1@0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&pwrcfg {
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ qflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q128a13", "jedec,spi-nor";
+ spi-max-frequency = <108000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ memory-map = <0x90000000 0x1000000>;
+ reg = <0>;
+ };
+};
+
+&timer5 {
+ u-boot,dm-pre-reloc;
+};
aliases {
serial0 = &usart1;
- spi0 = &qspi;
- mmc0 = &sdio;
- /* Aliases for gpios so as to use sequence */
- gpio0 = &gpioa;
- gpio1 = &gpiob;
- gpio2 = &gpioc;
- gpio3 = &gpiod;
- gpio4 = &gpioe;
- gpio5 = &gpiof;
- gpio6 = &gpiog;
- gpio7 = &gpioh;
- gpio8 = &gpioi;
- gpio9 = &gpioj;
- gpio10 = &gpiok;
};
- led1 {
- compatible = "st,led1";
- led-gpio = <&gpioi 1 0>;
- };
-
- button1 {
- compatible = "st,button1";
- button-gpio = <&gpioi 11 0>;
- };
-
- backlight: backlight {
- compatible = "gpio-backlight";
- gpios = <&gpiok 3 0>;
- status = "okay";
- };
-
- panel-rgb@0 {
- compatible = "simple-panel";
- backlight = <&backlight>;
- enable-gpios = <&gpioi 12 0>;
- status = "okay";
-
- display-timings {
- timing@0 {
- clock-frequency = <9000000>;
- hactive = <480>;
- vactive = <272>;
- hfront-porch = <2>;
- hback-porch = <2>;
- hsync-len = <41>;
- vfront-porch = <2>;
- vback-porch = <2>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <0>;
- pixelclk-active = <1>;
- };
- };
- };
};
&clk_hse {
bias-disable;
};
};
-
- ethernet_mii: mii@0 {
- pins {
- pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
- <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
- <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
- <STM32F746_PA2_FUNC_ETH_MDIO>,
- <STM32F746_PC1_FUNC_ETH_MDC>,
- <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
- <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
- <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
- <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
- slew-rate = <2>;
- };
- };
-
- qspi_pins: qspi@0 {
- pins {
- pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
- <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
- <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
- <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
- <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
- <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
- slew-rate = <2>;
- };
- };
-
- fmc_pins: fmc@0 {
- pins {
- pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
- <STM32F746_PD9_FUNC_FMC_D14>,
- <STM32F746_PD8_FUNC_FMC_D13>,
- <STM32F746_PE15_FUNC_FMC_D12>,
- <STM32F746_PE14_FUNC_FMC_D11>,
- <STM32F746_PE13_FUNC_FMC_D10>,
- <STM32F746_PE12_FUNC_FMC_D9>,
- <STM32F746_PE11_FUNC_FMC_D8>,
- <STM32F746_PE10_FUNC_FMC_D7>,
- <STM32F746_PE9_FUNC_FMC_D6>,
- <STM32F746_PE8_FUNC_FMC_D5>,
- <STM32F746_PE7_FUNC_FMC_D4>,
- <STM32F746_PD1_FUNC_FMC_D3>,
- <STM32F746_PD0_FUNC_FMC_D2>,
- <STM32F746_PD15_FUNC_FMC_D1>,
- <STM32F746_PD14_FUNC_FMC_D0>,
-
- <STM32F746_PE1_FUNC_FMC_NBL1>,
- <STM32F746_PE0_FUNC_FMC_NBL0>,
-
- <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
- <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
-
- <STM32F746_PG1_FUNC_FMC_A11>,
- <STM32F746_PG0_FUNC_FMC_A10>,
- <STM32F746_PF15_FUNC_FMC_A9>,
- <STM32F746_PF14_FUNC_FMC_A8>,
- <STM32F746_PF13_FUNC_FMC_A7>,
- <STM32F746_PF12_FUNC_FMC_A6>,
- <STM32F746_PF5_FUNC_FMC_A5>,
- <STM32F746_PF4_FUNC_FMC_A4>,
- <STM32F746_PF3_FUNC_FMC_A3>,
- <STM32F746_PF2_FUNC_FMC_A2>,
- <STM32F746_PF1_FUNC_FMC_A1>,
- <STM32F746_PF0_FUNC_FMC_A0>,
-
- <STM32F746_PH3_FUNC_FMC_SDNE0>,
- <STM32F746_PH5_FUNC_FMC_SDNWE>,
- <STM32F746_PF11_FUNC_FMC_SDNRAS>,
- <STM32F746_PG15_FUNC_FMC_SDNCAS>,
- <STM32F746_PC3_FUNC_FMC_SDCKE0>,
- <STM32F746_PG8_FUNC_FMC_SDCLK>;
- slew-rate = <2>;
- };
- };
-
- ltdc_pins: ltdc@0 {
- pins {
- pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
- <STM32F746_PG12_FUNC_LCD_B4>,
- <STM32F746_PI9_FUNC_LCD_VSYNC>,
- <STM32F746_PI10_FUNC_LCD_HSYNC>,
- <STM32F746_PI14_FUNC_LCD_CLK>,
- <STM32F746_PI15_FUNC_LCD_R0>,
- <STM32F746_PJ0_FUNC_LCD_R1>,
- <STM32F746_PJ1_FUNC_LCD_R2>,
- <STM32F746_PJ2_FUNC_LCD_R3>,
- <STM32F746_PJ3_FUNC_LCD_R4>,
- <STM32F746_PJ4_FUNC_LCD_R5>,
- <STM32F746_PJ5_FUNC_LCD_R6>,
- <STM32F746_PJ6_FUNC_LCD_R7>,
- <STM32F746_PJ7_FUNC_LCD_G0>,
- <STM32F746_PJ8_FUNC_LCD_G1>,
- <STM32F746_PJ9_FUNC_LCD_G2>,
- <STM32F746_PJ10_FUNC_LCD_G3>,
- <STM32F746_PJ11_FUNC_LCD_G4>,
- <STM32F746_PJ13_FUNC_LCD_B1>,
- <STM32F746_PJ14_FUNC_LCD_B2>,
- <STM32F746_PJ15_FUNC_LCD_B3>,
- <STM32F746_PK0_FUNC_LCD_G5>,
- <STM32F746_PK1_FUNC_LCD_G6>,
- <STM32F746_PK2_FUNC_LCD_G7>,
- <STM32F746_PK4_FUNC_LCD_B5>,
- <STM32F746_PK5_FUNC_LCD_B6>,
- <STM32F746_PK6_FUNC_LCD_B7>,
- <STM32F746_PK7_FUNC_LCD_DE>;
- slew-rate = <2>;
- };
- };
};
&usart1 {
status = "okay";
};
-&fmc {
- pinctrl-0 = <&fmc_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
- bank1: bank@0 {
- st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4
- CAS_3 SDCLK_2 RD_BURST_EN
- RD_PIPE_DL_0>;
- st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2
- TRP_2 TRCD_2>;
- /* refcount = (64msec/total_row_sdram)*freq - 20 */
- st,sdram-refcount = < 1542 >;
- };
-};
-
-&mac {
- status = "okay";
- pinctrl-0 = <ðernet_mii>;
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&qspi {
- pinctrl-0 = <&qspi_pins>;
- status = "okay";
-
- qflash0: n25q128a {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q128a13", "jedec,spi-nor";
- spi-max-frequency = <108000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- memory-map = <0x90000000 0x1000000>;
- reg = <0>;
- };
-};
-
&sdio {
status = "okay";
cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
bus-width = <4>;
max-frequency = <25000000>;
};
-
-<dc {
- status = "okay";
- pinctrl-0 = <<dc_pins>;
-};
compatible = "fixed-clock";
clock-frequency = <0>;
};
-};
+ };
soc {
- u-boot,dm-pre-reloc;
- mac: ethernet@40028000 {
- compatible = "st,stm32-dwmac";
- reg = <0x40028000 0x8000>;
- reg-names = "stmmaceth";
- clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
- <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
- <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
- interrupts = <61>, <62>;
- interrupt-names = "macirq", "eth_wake_irq";
- snps,pbl = <8>;
- snps,mixed-burst;
- dma-ranges;
- status = "disabled";
- };
-
- fmc: fmc@A0000000 {
- compatible = "st,stm32-fmc";
- reg = <0xA0000000 0x1000>;
- clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
- u-boot,dm-pre-reloc;
- };
-
- qspi: quadspi@A0001000 {
- compatible = "st,stm32-qspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
- reg-names = "qspi", "qspi_mm";
- interrupts = <92>;
- spi-max-frequency = <108000000>;
- clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
- resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
- status = "disabled";
- };
usart1: serial@40011000 {
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
status = "disabled";
- u-boot,dm-pre-reloc;
};
pwrcfg: power-config@58024800 {
reg = <0x40023800 0x400>;
clocks = <&clk_hse>;
st,syscfg = <&pwrcfg>;
- u-boot,dm-pre-reloc;
};
pinctrl: pin-controller {
#size-cells = <1>;
compatible = "st,stm32f746-pinctrl";
ranges = <0 0x40020000 0x3000>;
- u-boot,dm-pre-reloc;
pins-are-numbered;
gpioa: gpio@40020000 {
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
- u-boot,dm-pre-reloc;
};
gpiob: gpio@40020400 {
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
- u-boot,dm-pre-reloc;
};
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
- u-boot,dm-pre-reloc;
};
gpiod: gpio@40020c00 {
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
- u-boot,dm-pre-reloc;
};
gpioe: gpio@40021000 {
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
- u-boot,dm-pre-reloc;
};
gpiof: gpio@40021400 {
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
- u-boot,dm-pre-reloc;
};
gpiog: gpio@40021800 {
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
- u-boot,dm-pre-reloc;
};
gpioh: gpio@40021c00 {
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
- u-boot,dm-pre-reloc;
};
gpioi: gpio@40022000 {
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
- u-boot,dm-pre-reloc;
};
gpioj: gpio@40022400 {
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
- u-boot,dm-pre-reloc;
};
gpiok: gpio@40022800 {
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
- u-boot,dm-pre-reloc;
};
sdio_pins: sdio_pins@0 {
interrupts = <50>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
};
-
- ltdc: display-controller@40016800 {
- compatible = "st,stm32-ltdc";
- reg = <0x40016800 0x200>;
- resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
- u-boot,dm-pre-reloc;
- status = "disabled";
- };
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <stm32f7-u-boot.dtsi>
+/{
+ chosen {
+ bootargs = "root=/dev/ram rdinit=/linuxrc";
+ };
+
+ aliases {
+ /* Aliases for gpios so as to use sequence */
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ mmc0 = &sdio2;
+ spi0 = &qspi;
+ };
+
+ button1 {
+ compatible = "st,button1";
+ button-gpio = <&gpioa 0 0>;
+ };
+
+ led1 {
+ compatible = "st,led1";
+ led-gpio = <&gpioj 5 0>;
+ };
+};
+
+&fmc {
+ /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
+ bank1: bank@0 {
+ u-boot,dm-pre-reloc;
+ st,sdram-control = /bits/ 8 <NO_COL_8
+ NO_ROW_12
+ MWIDTH_32
+ BANKS_4
+ CAS_3
+ SDCLK_2
+ RD_BURST_EN
+ RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_2
+ TXSR_6
+ TRAS_4
+ TRC_6
+ TWR_2
+ TRP_2
+ TRCD_2>;
+ /* refcount = (64msec/total_row_sdram)*freq - 20 */
+ st,sdram-refcount = < 1542 >;
+ };
+};
+
+&pinctrl {
+ ethernet_mii: mii@0 {
+ pins {
+ pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+ <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
+ <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+ <STM32F746_PA2_FUNC_ETH_MDIO>,
+ <STM32F746_PC1_FUNC_ETH_MDC>,
+ <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+ <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+ <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+ <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
+ slew-rate = <2>;
+ };
+ };
+
+ fmc_pins: fmc@0 {
+ pins {
+ pinmux = <STM32F746_PI10_FUNC_FMC_D31>,
+ <STM32F746_PI9_FUNC_FMC_D30>,
+ <STM32F746_PI7_FUNC_FMC_D29>,
+ <STM32F746_PI6_FUNC_FMC_D28>,
+ <STM32F746_PI3_FUNC_FMC_D27>,
+ <STM32F746_PI2_FUNC_FMC_D26>,
+ <STM32F746_PI1_FUNC_FMC_D25>,
+ <STM32F746_PI0_FUNC_FMC_D24>,
+ <STM32F746_PH15_FUNC_FMC_D23>,
+ <STM32F746_PH14_FUNC_FMC_D22>,
+ <STM32F746_PH13_FUNC_FMC_D21>,
+ <STM32F746_PH12_FUNC_FMC_D20>,
+ <STM32F746_PH11_FUNC_FMC_D19>,
+ <STM32F746_PH10_FUNC_FMC_D18>,
+ <STM32F746_PH9_FUNC_FMC_D17>,
+ <STM32F746_PH8_FUNC_FMC_D16>,
+
+ <STM32F746_PD10_FUNC_FMC_D15>,
+ <STM32F746_PD9_FUNC_FMC_D14>,
+ <STM32F746_PD8_FUNC_FMC_D13>,
+ <STM32F746_PE15_FUNC_FMC_D12>,
+ <STM32F746_PE14_FUNC_FMC_D11>,
+ <STM32F746_PE13_FUNC_FMC_D10>,
+ <STM32F746_PE12_FUNC_FMC_D9>,
+ <STM32F746_PE11_FUNC_FMC_D8>,
+ <STM32F746_PE10_FUNC_FMC_D7>,
+ <STM32F746_PE9_FUNC_FMC_D6>,
+ <STM32F746_PE8_FUNC_FMC_D5>,
+ <STM32F746_PE7_FUNC_FMC_D4>,
+ <STM32F746_PD1_FUNC_FMC_D3>,
+ <STM32F746_PD0_FUNC_FMC_D2>,
+ <STM32F746_PD15_FUNC_FMC_D1>,
+ <STM32F746_PD14_FUNC_FMC_D0>,
+
+ <STM32F746_PI5_FUNC_FMC_NBL3>,
+ <STM32F746_PI4_FUNC_FMC_NBL2>,
+ <STM32F746_PE1_FUNC_FMC_NBL1>,
+ <STM32F746_PE0_FUNC_FMC_NBL0>,
+
+ <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
+ <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
+
+ <STM32F746_PG1_FUNC_FMC_A11>,
+ <STM32F746_PG0_FUNC_FMC_A10>,
+ <STM32F746_PF15_FUNC_FMC_A9>,
+ <STM32F746_PF14_FUNC_FMC_A8>,
+ <STM32F746_PF13_FUNC_FMC_A7>,
+ <STM32F746_PF12_FUNC_FMC_A6>,
+ <STM32F746_PF5_FUNC_FMC_A5>,
+ <STM32F746_PF4_FUNC_FMC_A4>,
+ <STM32F746_PF3_FUNC_FMC_A3>,
+ <STM32F746_PF2_FUNC_FMC_A2>,
+ <STM32F746_PF1_FUNC_FMC_A1>,
+ <STM32F746_PF0_FUNC_FMC_A0>,
+
+ <STM32F746_PH3_FUNC_FMC_SDNE0>,
+ <STM32F746_PH5_FUNC_FMC_SDNWE>,
+ <STM32F746_PF11_FUNC_FMC_SDNRAS>,
+ <STM32F746_PG15_FUNC_FMC_SDNCAS>,
+ <STM32F746_PH2_FUNC_FMC_SDCKE0>,
+ <STM32F746_PG8_FUNC_FMC_SDCLK>;
+ slew-rate = <2>;
+ };
+ };
+
+ qspi_pins: qspi@0 {
+ pins {
+ pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
+ <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
+ <STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>,
+ <STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>,
+ <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
+ <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
+ slew-rate = <2>;
+ };
+ };
+};
+
+&qspi {
+ flash0: mx66l51235l {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+};
compatible = "st,stm32f769-disco", "st,stm32f7";
chosen {
- bootargs = "root=/dev/ram rdinit=/linuxrc";
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &usart1;
- spi0 = &qspi;
- mmc0 = &sdio2;
- /* Aliases for gpios so as to use sequence */
- gpio0 = &gpioa;
- gpio1 = &gpiob;
- gpio2 = &gpioc;
- gpio3 = &gpiod;
- gpio4 = &gpioe;
- gpio5 = &gpiof;
- gpio6 = &gpiog;
- gpio7 = &gpioh;
- gpio8 = &gpioi;
- gpio9 = &gpioj;
- gpio10 = &gpiok;
- };
-
- led1 {
- compatible = "st,led1";
- led-gpio = <&gpioj 5 0>;
- };
-
- button1 {
- compatible = "st,button1";
- button-gpio = <&gpioa 0 0>;
};
};
};
};
- ethernet_mii: mii@0 {
- pins {
- pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
- <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
- <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
- <STM32F746_PA2_FUNC_ETH_MDIO>,
- <STM32F746_PC1_FUNC_ETH_MDC>,
- <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
- <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
- <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
- <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
- slew-rate = <2>;
- };
- };
-
- qspi_pins: qspi@0 {
- pins {
- pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
- <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
- <STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>,
- <STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>,
- <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
- <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
- slew-rate = <2>;
- };
- };
-
- fmc_pins: fmc@0 {
- pins {
- pinmux = <STM32F746_PI10_FUNC_FMC_D31>,
- <STM32F746_PI9_FUNC_FMC_D30>,
- <STM32F746_PI7_FUNC_FMC_D29>,
- <STM32F746_PI6_FUNC_FMC_D28>,
- <STM32F746_PI3_FUNC_FMC_D27>,
- <STM32F746_PI2_FUNC_FMC_D26>,
- <STM32F746_PI1_FUNC_FMC_D25>,
- <STM32F746_PI0_FUNC_FMC_D24>,
- <STM32F746_PH15_FUNC_FMC_D23>,
- <STM32F746_PH14_FUNC_FMC_D22>,
- <STM32F746_PH13_FUNC_FMC_D21>,
- <STM32F746_PH12_FUNC_FMC_D20>,
- <STM32F746_PH11_FUNC_FMC_D19>,
- <STM32F746_PH10_FUNC_FMC_D18>,
- <STM32F746_PH9_FUNC_FMC_D17>,
- <STM32F746_PH8_FUNC_FMC_D16>,
-
- <STM32F746_PD10_FUNC_FMC_D15>,
- <STM32F746_PD9_FUNC_FMC_D14>,
- <STM32F746_PD8_FUNC_FMC_D13>,
- <STM32F746_PE15_FUNC_FMC_D12>,
- <STM32F746_PE14_FUNC_FMC_D11>,
- <STM32F746_PE13_FUNC_FMC_D10>,
- <STM32F746_PE12_FUNC_FMC_D9>,
- <STM32F746_PE11_FUNC_FMC_D8>,
- <STM32F746_PE10_FUNC_FMC_D7>,
- <STM32F746_PE9_FUNC_FMC_D6>,
- <STM32F746_PE8_FUNC_FMC_D5>,
- <STM32F746_PE7_FUNC_FMC_D4>,
- <STM32F746_PD1_FUNC_FMC_D3>,
- <STM32F746_PD0_FUNC_FMC_D2>,
- <STM32F746_PD15_FUNC_FMC_D1>,
- <STM32F746_PD14_FUNC_FMC_D0>,
-
- <STM32F746_PI5_FUNC_FMC_NBL3>,
- <STM32F746_PI4_FUNC_FMC_NBL2>,
- <STM32F746_PE1_FUNC_FMC_NBL1>,
- <STM32F746_PE0_FUNC_FMC_NBL0>,
-
- <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
- <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
-
- <STM32F746_PG1_FUNC_FMC_A11>,
- <STM32F746_PG0_FUNC_FMC_A10>,
- <STM32F746_PF15_FUNC_FMC_A9>,
- <STM32F746_PF14_FUNC_FMC_A8>,
- <STM32F746_PF13_FUNC_FMC_A7>,
- <STM32F746_PF12_FUNC_FMC_A6>,
- <STM32F746_PF5_FUNC_FMC_A5>,
- <STM32F746_PF4_FUNC_FMC_A4>,
- <STM32F746_PF3_FUNC_FMC_A3>,
- <STM32F746_PF2_FUNC_FMC_A2>,
- <STM32F746_PF1_FUNC_FMC_A1>,
- <STM32F746_PF0_FUNC_FMC_A0>,
-
- <STM32F746_PH3_FUNC_FMC_SDNE0>,
- <STM32F746_PH5_FUNC_FMC_SDNWE>,
- <STM32F746_PF11_FUNC_FMC_SDNRAS>,
- <STM32F746_PG15_FUNC_FMC_SDNCAS>,
- <STM32F746_PH2_FUNC_FMC_SDCKE0>,
- <STM32F746_PG8_FUNC_FMC_SDCLK>;
- slew-rate = <2>;
- };
- };
};
&usart1 {
status = "okay";
};
-&fmc {
- pinctrl-0 = <&fmc_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
- bank1: bank@0 {
- st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4
- CAS_3 SDCLK_2 RD_BURST_EN
- RD_PIPE_DL_0>;
- st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2
- TRP_2 TRCD_2>;
- /* refcount = (64msec/total_row_sdram)*freq - 20 */
- st,sdram-refcount = < 1542 >;
- };
-};
-
-&mac {
- status = "okay";
- pinctrl-0 = <ðernet_mii>;
- phy-mode = "rmii";
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&qspi {
- pinctrl-0 = <&qspi_pins>;
- status = "okay";
-
- qflash0: n25q128a {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q128a13", "jedec,spi-nor";
- spi-max-frequency = <108000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- memory-map = <0x90000000 0x1000000>;
- reg = <0>;
- };
-};
-
&sdio2 {
status = "okay";
cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
projects / platform / kernel / u-boot.git / commitdiff