if (IsScalableVector) {
bool UseVMV_V_V = false;
+ bool UseVMV_V_I = false;
MachineBasicBlock::const_iterator DefMBBI;
- unsigned VIOpc;
if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
UseVMV_V_V = true;
// We only need to handle LMUL = 1/2/4/8 here because we only define
// vector register classes for LMUL = 1/2/4/8.
+ unsigned VIOpc;
switch (LMul) {
default:
llvm_unreachable("Impossible LMUL for vector register copy.");
VIOpc = RISCV::PseudoVMV_V_I_M8;
break;
}
- }
- bool UseVMV_V_I = false;
- if (UseVMV_V_V && (DefMBBI->getOpcode() == VIOpc)) {
- UseVMV_V_I = true;
- Opc = VIOpc;
+ if (DefMBBI->getOpcode() == VIOpc) {
+ UseVMV_V_I = true;
+ Opc = VIOpc;
+ }
}
if (NF == 1) {