case ISD::FSUB:
case ISD::FDIV:
case ISD::FREM:
- case ISD::SRA:
return N1; // fold op(undef, arg2) -> undef
case ISD::UDIV:
case ISD::SDIV:
case ISD::UREM:
case ISD::SREM:
+ case ISD::SRA:
case ISD::SRL:
case ISD::SHL:
- if (!VT.isVector())
- return getConstant(0, DL, VT); // fold op(undef, arg2) -> 0
- // For vectors, we can't easily build an all zero vector, just return
- // the LHS.
- return N2;
+ return getConstant(0, DL, VT); // fold op(undef, arg2) -> 0
}
}
}
case ISD::SDIV:
case ISD::UREM:
case ISD::SREM:
+ case ISD::SRA:
+ case ISD::SRL:
+ case ISD::SHL:
return N2; // fold op(arg1, undef) -> undef
case ISD::FADD:
case ISD::FSUB:
break;
case ISD::MUL:
case ISD::AND:
- case ISD::SRL:
- case ISD::SHL:
- if (!VT.isVector())
- return getConstant(0, DL, VT); // fold op(arg1, undef) -> 0
- // For vectors, we can't easily build an all zero vector, just return
- // the LHS.
- return N1;
+ return getConstant(0, DL, VT); // fold op(arg1, undef) -> 0
case ISD::OR:
- if (!VT.isVector())
- return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
- // For vectors, we can't easily build an all one vector, just return
- // the LHS.
- return N1;
- case ISD::SRA:
- return N1;
+ return getAllOnesConstant(DL, VT);
}
}
; subregisters were dropped by the tail duplicator, resulting in invalid
; COPY instructions being generated.
-; CHECK: = extractu(r{{[0-9]+}},#15,#17)
+; CHECK: = asl(r{{[0-9]+}}:{{[0-9]+}},#15)
target triple = "hexagon"
br label %if.end.i
if.else.i: ; preds = %if.then.i
- %shl12.i = shl i64 %0, undef
+ %shl12.i = shl i64 %0, 7
br label %if.end.i
if.end.i: ; preds = %if.else.i, %if.then5.i
%aSig0.0 = phi i64 [ undef, %if.then5.i ], [ %shl12.i, %if.else.i ]
%storemerge43.i = phi i64 [ %shl.i21, %if.then5.i ], [ 0, %if.else.i ]
- %sub15.i = sub nsw i32 -63, undef
+ %sub15.i = sub nsw i32 -63, 8
br label %if.end13
if.else16.i: ; preds = %if.then7
br label %if.end13
if.else: ; preds = %entry
- %or12 = or i64 undef, 281474976710656
+ %or12 = or i64 9, 281474976710656
br label %if.end13
if.end13: ; preds = %if.else, %if.else16.i, %if.end.i
define <4 x i32> @mul_undef_rhs_vec(<4 x i32> %x) {
; CHECK-LABEL: mul_undef_rhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%r = mul <4 x i32> %x, undef
ret <4 x i32> %r
define <4 x i32> @mul_undef_lhs_vec(<4 x i32> %x) {
; CHECK-LABEL: mul_undef_lhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%r = mul <4 x i32> undef, %x
ret <4 x i32> %r
define <4 x i32> @sdiv_undef_lhs_vec(<4 x i32> %x) {
; CHECK-LABEL: sdiv_undef_lhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%r = sdiv <4 x i32> undef, %x
ret <4 x i32> %r
define <4 x i32> @udiv_undef_lhs_vec(<4 x i32> %x) {
; CHECK-LABEL: udiv_undef_lhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%r = udiv <4 x i32> undef, %x
ret <4 x i32> %r
define <4 x i32> @srem_undef_lhs_vec(<4 x i32> %x) {
; CHECK-LABEL: srem_undef_lhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%r = srem <4 x i32> undef, %x
ret <4 x i32> %r
define <4 x i32> @urem_undef_lhs_vec(<4 x i32> %x) {
; CHECK-LABEL: urem_undef_lhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%r = urem <4 x i32> undef, %x
ret <4 x i32> %r
define i32 @ashr_undef_rhs(i32 %x) {
; CHECK-LABEL: ashr_undef_rhs:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%r = ashr i32 %x, undef
ret i32 %r
define i32 @ashr_undef_lhs(i32 %x) {
; CHECK-LABEL: ashr_undef_lhs:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
%r = ashr i32 undef, %x
ret i32 %r
define <4 x i32> @ashr_undef_lhs_vec(<4 x i32> %x) {
; CHECK-LABEL: ashr_undef_lhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%r = ashr <4 x i32> undef, %x
ret <4 x i32> %r
define i32 @lshr_undef_rhs(i32 %x) {
; CHECK-LABEL: lshr_undef_rhs:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
%r = lshr i32 %x, undef
ret i32 %r
define <4 x i32> @lshr_undef_lhs_vec(<4 x i32> %x) {
; CHECK-LABEL: lshr_undef_lhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%r = lshr <4 x i32> undef, %x
ret <4 x i32> %r
define i32 @shl_undef_rhs(i32 %x) {
; CHECK-LABEL: shl_undef_rhs:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
%r = shl i32 %x, undef
ret i32 %r
define <4 x i32> @shl_undef_lhs_vec(<4 x i32> %x) {
; CHECK-LABEL: shl_undef_lhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%r = shl <4 x i32> undef, %x
ret <4 x i32> %r
define <4 x i32> @and_undef_rhs_vec(<4 x i32> %x) {
; CHECK-LABEL: and_undef_rhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%r = and <4 x i32> %x, undef
ret <4 x i32> %r
define <4 x i32> @and_undef_lhs_vec(<4 x i32> %x) {
; CHECK-LABEL: and_undef_lhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: retq
%r = and <4 x i32> undef, %x
ret <4 x i32> %r
define <4 x i32> @or_undef_rhs_vec(<4 x i32> %x) {
; CHECK-LABEL: or_undef_rhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-NEXT: retq
%r = or <4 x i32> %x, undef
ret <4 x i32> %r
define <4 x i32> @or_undef_lhs_vec(<4 x i32> %x) {
; CHECK-LABEL: or_undef_lhs_vec:
; CHECK: # %bb.0:
+; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-NEXT: retq
%r = or <4 x i32> undef, %x
ret <4 x i32> %r