drm/i915: Use paramtrized WRPLL_CTL()

v2: Rebase due to SKL_DPLLx usage

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1442595836-23981-21-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bc7b8fa..9ee9481 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7312,7 +7312,7 @@ enum skl_disp_power_wells {
 /* WRPLL */
 #define WRPLL_CTL1                     0x46040
 #define WRPLL_CTL2                     0x46060
-#define WRPLL_CTL(pll)                 (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
+#define WRPLL_CTL(pll)                 _PIPE(pll, WRPLL_CTL1, WRPLL_CTL2)
 #define  WRPLL_PLL_ENABLE              (1<<31)
 #define  WRPLL_PLL_SSC                 (1<<28)
 #define  WRPLL_PLL_NON_SSC             (2<<28)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a163741..a65bf81 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1112,10 +1112,10 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
                link_clock = 270000;
                break;
        case PORT_CLK_SEL_WRPLL1:
-               link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
+               link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
                break;
        case PORT_CLK_SEL_WRPLL2:
-               link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
+               link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
                break;
        case PORT_CLK_SEL_SPLL:
                pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
@@ -2511,13 +2511,13 @@ static const struct skl_dpll_regs skl_dpll_regs[3] = {
        },
        {
                /* DPLL 2 */
-               .ctl = WRPLL_CTL1,
+               .ctl = WRPLL_CTL(0),
                .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
                .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
        },
        {
                /* DPLL 3 */
-               .ctl = WRPLL_CTL2,
+               .ctl = WRPLL_CTL(1),
                .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
                .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
        },

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9d9e0e8..db66dae 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9277,8 +9277,8 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
 
        I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
        I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
-       I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
-       I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
+       I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
+       I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
        I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
        I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
             "CPU PWM1 enabled\n");