clk: exynos4: export sclk_hdmiphy clock

Export sclk_hdmiphy clock to be usable from DT.

Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com>
Change-Id: I0d1c8d0c2e2e93bd34f9fcdf82154208c2381a73

diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index d7a4bc9..4c62832 100644 (file)
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -47,6 +47,7 @@ Exynos4 SoC and this is specified where applicable.
   mout_core           19
   mout_apll           20
   clkout              21
+  sclk_hdmiphy        22
 
 
             [Clock Gate for Special Clocks]

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index c0ee010..1a3fd05 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -143,7 +143,7 @@ enum exynos4_clks {
        xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
        sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
        aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core,
-       mout_apll, clkout, /* 21 */
+       mout_apll, clkout, sclk_hdmiphy, /* 22 */
 
        /* gate for special clocks (sclk) */
        sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
@@ -351,7 +351,7 @@ struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
 /* fixed rate clocks generated inside the soc */
 struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
        FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
-       FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+       FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
        FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
 };