NITIO_AUTO_INC_REG(counter->counter_index));
ni_tio_set_bits(counter, NITIO_CMD_REG(counter->counter_index),
~0, Gi_Synchronize_Gate_Bit);
- ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index), ~0,
+ ni_tio_set_bits(counter, NITIO_MODE_REG(counter->counter_index), ~0,
0);
counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = 0x0;
write_register(counter,
default:
break;
}
- ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
+ ni_tio_set_bits(counter, NITIO_MODE_REG(counter->counter_index),
mode_reg_mask, mode_reg_values);
if (ni_tio_counting_mode_registers_present(counter_dev)) {
mode_values |= Gi_Rising_Edge_Gating_Bits;
else
mode_values |= Gi_Level_Gating_Bits;
- ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
+ ni_tio_set_bits(counter, NITIO_MODE_REG(counter->counter_index),
mode_mask, mode_values);
}
case 0:
if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
ni_tio_set_bits(counter,
- NITIO_Gi_Mode_Reg(counter->
+ NITIO_MODE_REG(counter->
counter_index),
Gi_Gating_Mode_Mask,
Gi_Gating_Disabled_Bits);
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
const unsigned mode_bits = ni_tio_get_soft_copy(counter,
- NITIO_Gi_Mode_Reg
+ NITIO_MODE_REG
(counter->
counter_index));
const unsigned second_gate_reg =
#define NITIO_AUTO_INC_REG(x) (NITIO_G0_AUTO_INC + (x))
#define NITIO_CMD_REG(x) (NITIO_G0_CMD + (x))
#define NITIO_SW_SAVE_REG(x) (NITIO_G0_SW_SAVE + (x))
+#define NITIO_MODE_REG(x) (NITIO_G0_MODE + (x))
static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned idx)
{
return 0;
}
-static inline enum ni_gpct_register NITIO_Gi_Mode_Reg(unsigned idx)
-{
- switch (idx) {
- case 0:
- return NITIO_G0_MODE;
- case 1:
- return NITIO_G1_MODE;
- case 2:
- return NITIO_G2_MODE;
- case 3:
- return NITIO_G3_MODE;
- }
- return 0;
-}
-
static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(unsigned idx)
{
switch (idx) {