arm: zynq: Add lowlevel initialization to C

Do lowlevel initialization directly in C. Zynq do not
require to do it in asm.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 91618d3..e8f4c19 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -21,9 +21,33 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
 
-inline void lowlevel_init(void) {}
+void lowlevel_init(void)
+{
+       zynq_slcr_unlock();
+       /* remap DDR to zero, FILTERSTART */
+       writel(0, &scu_base->filter_start);
+
+       /* Device config APB, unlock the PCAP */
+       writel(0x757BDF0D, &devcfg_base->unlock);
+       writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
+
+       /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
+       writel(0x1F, &slcr_base->ocm_cfg);
+       /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
+       writel(0x0, &slcr_base->fpga_rst_ctrl);
+       /* TZ_DDR_RAM, Set DDR trust zone non-secure */
+       writel(0xFFFFFFFF, &slcr_base->trust_zone);
+       /* Set urgent bits with register */
+       writel(0x0, &slcr_base->ddr_urgent_sel);
+       /* Urgent write, ports S2/S3 */
+       writel(0xC, &slcr_base->ddr_urgent);
+
+       zynq_slcr_lock();
+}
 
 void reset_cpu(ulong addr)
 {

diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index ad17b27..d0c69da 100644 (file)
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -24,6 +24,8 @@
 #define _ASM_ARCH_HARDWARE_H
 
 #define XPSS_SYS_CTRL_BASEADDR         0xF8000000
+#define XPSS_DEV_CFG_APB_BASEADDR      0xF8007000
+#define XPSS_SCU_BASEADDR              0xF8F00000
 
 /* Reflect slcr offsets */
 struct slcr_regs {
@@ -32,10 +34,52 @@ struct slcr_regs {
        u32 slcr_unlock; /* 0x8 */
        u32 reserved1[125];
        u32 pss_rst_ctrl; /* 0x200 */
-       u32 reserved2[21];
+       u32 reserved2[15];
+       u32 fpga_rst_ctrl; /* 0x240 */
+       u32 reserved3[5];
        u32 reboot_status; /* 0x258 */
+       u32 boot_mode; /* 0x25c */
+       u32 reserved4[116];
+       u32 trust_zone; /* 0x430 */ /* FIXME */
+       u32 reserved5[115];
+       u32 ddr_urgent; /* 0x600 */
+       u32 reserved6[6];
+       u32 ddr_urgent_sel; /* 0x61c */
+       u32 reserved7[188];
+       u32 ocm_cfg; /* 0x910 */
 };
 
 #define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
 
+struct devcfg_regs {
+       u32 ctrl; /* 0x0 */
+       u32 lock; /* 0x4 */
+       u32 cfg; /* 0x8 */
+       u32 int_sts; /* 0xc */
+       u32 int_mask; /* 0x10 */
+       u32 status; /* 0x14 */
+       u32 dma_src_addr; /* 0x18 */
+       u32 dma_dst_addr; /* 0x1c */
+       u32 dma_src_len; /* 0x20 */
+       u32 dma_dst_len; /* 0x24 */
+       u32 rom_shadow; /* 0x28 */
+       u32 reserved1[2];
+       u32 unlock; /* 0x34 */
+       u32 reserved2[18];
+       u32 mctrl; /* 0x80 */
+       u32 reserved3;
+       u32 write_count; /* 0x88 */
+       u32 read_count; /* 0x8c */
+};
+
+#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
+
+struct scu_regs {
+       u32 reserved1[16];
+       u32 filter_start; /* 0x40 */
+       u32 filter_end; /* 0x44 */
+};
+
+#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
+
 #endif /* _ASM_ARCH_HARDWARE_H */