* arm.h (TARGET_VFP): Delete.
(TARGET_VFPD32): Remove references to TARGET_VFP.
(TARGET_VFP3, TARGET_VFP5): Likewise.
(TARGET_VFP_SINGLE, TARGET_VFP_DOUBLE): Likewise.
(TARGET_NEON_FP16): Likewise.
(TARGET_FMA): Likewise.
(TARGET_CRYPTO): Likewise.
(TARGET_NEON): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS): Likewise.
(FUNCTION_ARG_REGNO_P): Likewise.
* arm.c (arm_option_check_internal): Likewise.
(arm_option_override): Likewise.
(use_return_insn): Likewise.
(arm_function_value_regno_p): Likewise.
(arm_apply_result_size): Likewise.
(use_vfp_abi): Likewise.
(arm_legitimate_address_outer_p): Likewise.
(thumb2_legitimate_address_p): Likewise.
(arm_legitimate_index_p): Likewise.
(thumb2_legitimate_index_p): Likewise.
(arm_legitimate_address): Likewise.
(arm_get_vfp_saved_size): Likewise.
(arm_emit_vfp_multi_reg_pop): Likewise.
(arm_get_frame_offsets): Likewise.
(arm_save_coproc_regs): Likewise.
(arm_hard_regno_mode_ok): Likewise.
(arm_expand_epilogue_apcs_frame): Likewise.
(arm_expand_epilogue): Likewise.
(arm_file_start): Likewise.
(arm_conditional_register_usage): Likewise.
(arm_validize_comparison): Use vfp_compare_operand directly.
* arm-builtins.c (arm_init_builtins): Remove references to TARGET_VFP.
(arm_expand_vfp_builtin): Use TARGET_HARD_FLOAT for detecting
unsupported usage.
(arm_atomic_assign_expand_fenv): Likewise.
* arm.md (divsf3): Likewise.
(arm_negsi2): Likewise.
(absdf2): Likewise.
(arm_movdi): Likewise.
(arm_movt): Likewise.
(cbranchsf4): Change predicate to vfp_compare_operand.
(cbranchdf4): Change predicate to vfp_compare_operand.
(cstorehf4): Change predicate to vfp_compare_operand.
(cstoresf4): Change predicate to vfp_compare_operand.
(cstoredf4): Change predicate to vfp_compare_operand.
(vfp_pop_multiple_with_writeback): Remove references to TARGET_VFP.
(movhi_insn_arch4, movhi_bytes): Likewise.
* constraints.md (Dt): Likewise.
(Dp): Likewise.
* iterators.md (SDF): Likewise.
* predicates.md (arm_float_compare_operand): Delete.
(const_double_vcvt_power_of_two_reciprocal): Remove references to
TARGET_VFP.
(const_double_vcvt_power_of_two): Likewise.
* thumb2.md thumb2_movsi_insn): Likewise.
* vfp.md (arm_movhi_vfp, thumb2_movhi_vfp): Likewise.
(movhf_vfp): Likewise.
(arm_movsi_vfp, thumb2_movsi_vfp): Likewise.
(movdi_vfp, movdi_vfp_cortexa8): Likewise.
(movsf_vfp, thumb2_movsf_vfp): Likewise.
(movdf_vfp, thumb2_movdf_vfp): Likewise.
(movsfcc_vfp, abssf2_vfp, negsf2_vfp, addsf3_vfp): Likewise.
(subsf3_vfp, divsf3_vfp): Likewise.
(mulsf3_vfp, mulsf3negsf_vfp, negmulsf3_vfp): Likewise.
(mulsf3addsf_vfp, (mulsf3subsf_vfp, mulsf3negsfaddsf_vfp): Likewise.
(mulsf3negsfsubsf_vfp): Likewise.
(truncsisf2_vfp, fixuns_truncsfsi2, floatsisf2_vfp): Likewise.
(floatunssisf2, sqrtsf2_vfp): Likewise.
(movcc_vfp): Likewise.
(cmpsf_split_vfp, cmpsf_trap_split_vfp): Likewise.
(cmpsf_vfp, cmpsf_trap_vfp): Likewise.
(push_multi_vfp): Likewise.
(set_fpscr, get_fpscr): Likewise.
* arm-c.c (arm_cpu_builtins): Unconditionally define __VFP_FP__.
From-SVN: r241118
2016-10-13 Richard Earsnhaw <rearnsha@arm.com>
+ * arm.h (TARGET_VFP): Delete.
+ (TARGET_VFPD32): Remove references to TARGET_VFP.
+ (TARGET_VFP3, TARGET_VFP5): Likewise.
+ (TARGET_VFP_SINGLE, TARGET_VFP_DOUBLE): Likewise.
+ (TARGET_NEON_FP16): Likewise.
+ (TARGET_FMA): Likewise.
+ (TARGET_CRYPTO): Likewise.
+ (TARGET_NEON): Likewise.
+ (SECONDARY_OUTPUT_RELOAD_CLASS): Likewise.
+ (FUNCTION_ARG_REGNO_P): Likewise.
+ * arm.c (arm_option_check_internal): Likewise.
+ (arm_option_override): Likewise.
+ (use_return_insn): Likewise.
+ (arm_function_value_regno_p): Likewise.
+ (arm_apply_result_size): Likewise.
+ (use_vfp_abi): Likewise.
+ (arm_legitimate_address_outer_p): Likewise.
+ (thumb2_legitimate_address_p): Likewise.
+ (arm_legitimate_index_p): Likewise.
+ (thumb2_legitimate_index_p): Likewise.
+ (arm_legitimate_address): Likewise.
+ (arm_get_vfp_saved_size): Likewise.
+ (arm_emit_vfp_multi_reg_pop): Likewise.
+ (arm_get_frame_offsets): Likewise.
+ (arm_save_coproc_regs): Likewise.
+ (arm_hard_regno_mode_ok): Likewise.
+ (arm_expand_epilogue_apcs_frame): Likewise.
+ (arm_expand_epilogue): Likewise.
+ (arm_file_start): Likewise.
+ (arm_conditional_register_usage): Likewise.
+ (arm_validize_comparison): Use vfp_compare_operand directly.
+ * arm-builtins.c (arm_init_builtins): Remove references to TARGET_VFP.
+ (arm_expand_vfp_builtin): Use TARGET_HARD_FLOAT for detecting
+ unsupported usage.
+ (arm_atomic_assign_expand_fenv): Likewise.
+ * arm.md (divsf3): Likewise.
+ (arm_negsi2): Likewise.
+ (absdf2): Likewise.
+ (arm_movdi): Likewise.
+ (arm_movt): Likewise.
+ (cbranchsf4): Change predicate to vfp_compare_operand.
+ (cbranchdf4): Change predicate to vfp_compare_operand.
+ (cstorehf4): Change predicate to vfp_compare_operand.
+ (cstoresf4): Change predicate to vfp_compare_operand.
+ (cstoredf4): Change predicate to vfp_compare_operand.
+ (vfp_pop_multiple_with_writeback): Remove references to TARGET_VFP.
+ (movhi_insn_arch4, movhi_bytes): Likewise.
+ * constraints.md (Dt): Likewise.
+ (Dp): Likewise.
+ * iterators.md (SDF): Likewise.
+ * predicates.md (arm_float_compare_operand): Delete.
+ (const_double_vcvt_power_of_two_reciprocal): Remove references to
+ TARGET_VFP.
+ (const_double_vcvt_power_of_two): Likewise.
+ * thumb2.md thumb2_movsi_insn): Likewise.
+ * vfp.md (arm_movhi_vfp, thumb2_movhi_vfp): Likewise.
+ (movhf_vfp): Likewise.
+ (arm_movsi_vfp, thumb2_movsi_vfp): Likewise.
+ (movdi_vfp, movdi_vfp_cortexa8): Likewise.
+ (movsf_vfp, thumb2_movsf_vfp): Likewise.
+ (movdf_vfp, thumb2_movdf_vfp): Likewise.
+ (movsfcc_vfp, abssf2_vfp, negsf2_vfp, addsf3_vfp): Likewise.
+ (subsf3_vfp, divsf3_vfp): Likewise.
+ (mulsf3_vfp, mulsf3negsf_vfp, negmulsf3_vfp): Likewise.
+ (mulsf3addsf_vfp, (mulsf3subsf_vfp, mulsf3negsfaddsf_vfp): Likewise.
+ (mulsf3negsfsubsf_vfp): Likewise.
+ (truncsisf2_vfp, fixuns_truncsfsi2, floatsisf2_vfp): Likewise.
+ (floatunssisf2, sqrtsf2_vfp): Likewise.
+ (movcc_vfp): Likewise.
+ (cmpsf_split_vfp, cmpsf_trap_split_vfp): Likewise.
+ (cmpsf_vfp, cmpsf_trap_vfp): Likewise.
+ (push_multi_vfp): Likewise.
+ (set_fpscr, get_fpscr): Likewise.
+ * arm-c.c (arm_cpu_builtins): Unconditionally define __VFP_FP__.
+
+2016-10-13 Richard Earsnhaw <rearnsha@arm.com>
+
* arm.h (TARGET_VFP): Unconditionally define to 1.
(arm_fpu_desc): Remove 'model' field.
(TARGET_FPU_MODEL): Delete.
/* The NEON builtin data can be found in arm_neon_builtins.def and
arm_vfp_builtins.def. The entries in arm_neon_builtins.def require
- TARGET_NEON to be true. The entries in arm_vfp_builtins.def require
- TARGET_VFP to be true. The feature tests are checked when the builtins are
- expanded.
+ TARGET_NEON to be true. The feature tests are checked when the
+ builtins are expanded.
- The mode entries in the following table correspond to
- the "key" type of the instruction variant, i.e. equivalent to that which
- would be specified after the assembler mnemonic, which usually refers to the
- last vector operand. The modes listed per instruction should be the same as
- those defined for that instruction's pattern in neon.md. */
+ The mode entries in the following table correspond to the "key"
+ type of the instruction variant, i.e. equivalent to that which
+ would be specified after the assembler mnemonic, which usually
+ refers to the last vector operand. The modes listed per
+ instruction should be the same as those defined for that
+ instruction's pattern in neon.md. */
static neon_builtin_datum vfp_builtin_data[] =
{
if (TARGET_CRC32)
arm_init_crc32_builtins ();
- if (TARGET_VFP && TARGET_HARD_FLOAT)
+ if (TARGET_HARD_FLOAT)
{
tree ftype_set_fpscr
= build_function_type_list (void_type_node, unsigned_type_node, NULL);
return arm_expand_neon_builtin_1 (fcode, exp, target, d);
}
-/* Expand a VFP builtin, if TARGET_VFP is true. These builtins are treated like
+/* Expand a VFP builtin. These builtins are treated like
neon builtins except that the data is looked up in table
VFP_BUILTIN_DATA. */
static rtx
arm_expand_vfp_builtin (int fcode, tree exp, rtx target)
{
- if (fcode >= ARM_BUILTIN_VFP_BASE && ! TARGET_VFP)
+ if (fcode >= ARM_BUILTIN_VFP_BASE && ! TARGET_HARD_FLOAT)
{
fatal_error (input_location,
"You must enable VFP instructions"
tree new_fenv_var, reload_fenv, restore_fnenv;
tree update_call, atomic_feraiseexcept, hold_fnclex;
- if (!TARGET_VFP || !TARGET_HARD_FLOAT)
+ if (!TARGET_HARD_FLOAT)
return;
/* Generate the equivalent of :
if (TARGET_SOFT_FLOAT)
builtin_define ("__SOFTFP__");
- def_or_undef_macro (pfile, "__VFP_FP__", TARGET_VFP);
+ builtin_define ("__VFP_FP__");
if (TARGET_ARM_FP)
builtin_define_with_int_value ("__ARM_FP", TARGET_ARM_FP);
const struct arm_fpu_desc *fpu_desc = &all_fpus[opts->x_arm_fpu_index];
/* iWMMXt and NEON are incompatible. */
- if (TARGET_IWMMXT && TARGET_VFP
- && ARM_FPU_FSET_HAS (fpu_desc->features, FPU_FL_NEON))
+ if (TARGET_IWMMXT
+ && ARM_FPU_FSET_HAS (fpu_desc->features, FPU_FL_NEON))
error ("iWMMXt and NEON are incompatible");
/* Make sure that the processor choice does not conflict with any of the
/* If soft-float is specified then don't use FPU. */
if (TARGET_SOFT_FLOAT)
arm_fpu_attr = FPU_NONE;
- else if (TARGET_VFP)
- arm_fpu_attr = FPU_VFP;
else
- gcc_unreachable();
+ arm_fpu_attr = FPU_VFP;
if (TARGET_AAPCS_BASED)
{
if (arm_abi == ARM_ABI_IWMMXT)
arm_pcs_default = ARM_PCS_AAPCS_IWMMXT;
else if (arm_float_abi == ARM_FLOAT_ABI_HARD
- && TARGET_HARD_FLOAT
- && TARGET_VFP)
+ && TARGET_HARD_FLOAT)
arm_pcs_default = ARM_PCS_AAPCS_VFP;
else
arm_pcs_default = ARM_PCS_AAPCS;
}
else
{
- if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
+ if (arm_float_abi == ARM_FLOAT_ABI_HARD)
sorry ("-mfloat-abi=hard and VFP");
if (arm_abi == ARM_ABI_APCS)
/* Can't be done if any of the VFP regs are pushed,
since this also requires an insn. */
- if (TARGET_HARD_FLOAT && TARGET_VFP)
+ if (TARGET_HARD_FLOAT)
for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
return 0;
if (regno == ARG_REGISTER (1)
|| (TARGET_32BIT
&& TARGET_AAPCS_BASED
- && TARGET_VFP
&& TARGET_HARD_FLOAT
&& regno == FIRST_VFP_REGNUM)
|| (TARGET_IWMMXT_ABI
if (TARGET_32BIT)
{
- if (TARGET_HARD_FLOAT_ABI && TARGET_VFP)
+ if (TARGET_HARD_FLOAT_ABI)
size += 32;
if (TARGET_IWMMXT_ABI)
size += 8;
if (pcs_variant != ARM_PCS_AAPCS_LOCAL)
return false;
- return (TARGET_32BIT && TARGET_VFP && TARGET_HARD_FLOAT &&
+ return (TARGET_32BIT && TARGET_HARD_FLOAT &&
(TARGET_VFP_DOUBLE || !is_double));
}
return 1;
use_ldrd = (TARGET_LDRD
- && (mode == DImode
- || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
+ && (mode == DImode || mode == DFmode));
if (code == POST_INC || code == PRE_DEC
|| ((code == PRE_INC || code == POST_DEC)
return 1;
use_ldrd = (TARGET_LDRD
- && (mode == DImode
- || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
+ && (mode == DImode || mode == DFmode));
if (code == POST_INC || code == PRE_DEC
|| ((code == PRE_INC || code == POST_DEC)
/* Standard coprocessor addressing modes. */
if (TARGET_HARD_FLOAT
- && TARGET_VFP
&& (mode == SFmode || mode == DFmode))
return (code == CONST_INT && INTVAL (index) < 1024
&& INTVAL (index) > -1024
/* ??? Combine arm and thumb2 coprocessor addressing modes. */
/* Standard coprocessor addressing modes. */
if (TARGET_HARD_FLOAT
- && TARGET_VFP
&& (mode == SFmode || mode == DFmode))
return (code == CONST_INT && INTVAL (index) < 1024
/* Thumb-2 allows only > -256 index range for it's core register
/* VFP addressing modes actually allow greater offsets, but for
now we just stick with the lowest common denominator. */
- if (mode == DImode
- || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
+ if (mode == DImode || mode == DFmode)
{
low_n = n & 0x0f;
n &= ~0x0f;
gcc_assert (REG_P (reg));
gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
- gcc_assert ((mode == HFmode && TARGET_HARD_FLOAT && TARGET_VFP)
+ gcc_assert ((mode == HFmode && TARGET_HARD_FLOAT)
|| mode == SFmode
|| mode == DFmode
|| mode == HImode
saved = 0;
/* Space for saved VFP registers. */
- if (TARGET_HARD_FLOAT && TARGET_VFP)
+ if (TARGET_HARD_FLOAT)
{
count = 0;
for (regno = FIRST_VFP_REGNUM;
REG_NOTES (par) = dwarf;
/* Make sure cfa doesn't leave with IP_REGNUM to allow unwinding fron FP. */
- if (TARGET_VFP && REGNO (base_reg) == IP_REGNUM)
+ if (REGNO (base_reg) == IP_REGNUM)
{
RTX_FRAME_RELATED_P (par) = 1;
add_reg_note (par, REG_CFA_DEF_CFA, hard_frame_pointer_rtx);
func_type = arm_current_func_type ();
/* Space for saved VFP registers. */
if (! IS_VOLATILE (func_type)
- && TARGET_HARD_FLOAT && TARGET_VFP)
+ && TARGET_HARD_FLOAT)
saved += arm_get_vfp_saved_size ();
}
else /* TARGET_THUMB1 */
saved_size += 8;
}
- if (TARGET_HARD_FLOAT && TARGET_VFP)
+ if (TARGET_HARD_FLOAT)
{
start_reg = FIRST_VFP_REGNUM;
{
if (GET_MODE_CLASS (mode) == MODE_CC)
return (regno == CC_REGNUM
- || (TARGET_HARD_FLOAT && TARGET_VFP
+ || (TARGET_HARD_FLOAT
&& regno == VFPCC_REGNUM));
if (regno == CC_REGNUM && GET_MODE_CLASS (mode) != MODE_CC)
start of an even numbered register pair. */
return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
- if (TARGET_HARD_FLOAT && TARGET_VFP
- && IS_VFP_REGNUM (regno))
+ if (TARGET_HARD_FLOAT && IS_VFP_REGNUM (regno))
{
if (mode == SFmode || mode == SImode)
return VFP_REGNO_OK_FOR_SINGLE (regno);
floats_from_frame += 4;
}
- if (TARGET_HARD_FLOAT && TARGET_VFP)
+ if (TARGET_HARD_FLOAT)
{
int start_reg;
rtx ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
}
}
- if (TARGET_HARD_FLOAT && TARGET_VFP)
+ if (TARGET_HARD_FLOAT)
{
/* Generate VFP register multi-pop. */
int end_reg = LAST_VFP_REGNUM + 1;
if (print_tune_info)
arm_print_tune_info ();
- if (! TARGET_SOFT_FLOAT && TARGET_VFP)
+ if (! TARGET_SOFT_FLOAT)
{
if (TARGET_HARD_FLOAT && TARGET_VFP_SINGLE)
arm_emit_eabi_attribute ("Tag_ABI_HardFP_use", 27, 1);
if (TARGET_THUMB1)
fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1;
- if (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP)
+ if (TARGET_32BIT && TARGET_HARD_FLOAT)
{
/* VFPv3 registers are disabled when earlier VFP
versions are selected due to the definition of
/* Fall through. */
case SFmode:
case DFmode:
- if (!arm_float_compare_operand (*op1, mode))
+ if (!vfp_compare_operand (*op1, mode))
*op1 = force_reg (mode, *op1);
- if (!arm_float_compare_operand (*op2, mode))
+ if (!vfp_compare_operand (*op2, mode))
*op2 = force_reg (mode, *op2);
return true;
default:
#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
/* Use hardware floating point calling convention. */
#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
-/* We only support the VFP model these days. */
-#define TARGET_VFP (1)
#define TARGET_IWMMXT (arm_arch_iwmmxt)
#define TARGET_IWMMXT2 (arm_arch_iwmmxt2)
#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
to be more careful with TARGET_NEON as noted below. */
/* FPU is has the full VFPv3/NEON register file of 32 D registers. */
-#define TARGET_VFPD32 (TARGET_VFP && TARGET_FPU_REGS == VFP_REG_D32)
+#define TARGET_VFPD32 (TARGET_FPU_REGS == VFP_REG_D32)
/* FPU supports VFPv3 instructions. */
-#define TARGET_VFP3 (TARGET_VFP && TARGET_FPU_REV >= 3)
+#define TARGET_VFP3 (TARGET_FPU_REV >= 3)
/* FPU supports FPv5 instructions. */
-#define TARGET_VFP5 (TARGET_VFP && TARGET_FPU_REV >= 5)
+#define TARGET_VFP5 (TARGET_FPU_REV >= 5)
/* FPU only supports VFP single-precision instructions. */
-#define TARGET_VFP_SINGLE (TARGET_VFP && TARGET_FPU_REGS == VFP_REG_SINGLE)
+#define TARGET_VFP_SINGLE (TARGET_FPU_REGS == VFP_REG_SINGLE)
/* FPU supports VFP double-precision instructions. */
-#define TARGET_VFP_DOUBLE (TARGET_VFP && TARGET_FPU_REGS != VFP_REG_SINGLE)
+#define TARGET_VFP_DOUBLE (TARGET_FPU_REGS != VFP_REG_SINGLE)
/* FPU supports half-precision floating-point with NEON element load/store. */
-#define TARGET_NEON_FP16 \
- (TARGET_VFP \
- && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON) \
+#define TARGET_NEON_FP16 \
+ (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON) \
&& ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
/* FPU supports VFP half-precision floating-point. */
#define TARGET_FP16 \
- (TARGET_VFP && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
+ (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
/* FPU supports fused-multiply-add operations. */
-#define TARGET_FMA (TARGET_VFP && TARGET_FPU_REV >= 4)
+#define TARGET_FMA (TARGET_FPU_REV >= 4)
/* FPU is ARMv8 compatible. */
-#define TARGET_FPU_ARMV8 (TARGET_VFP && TARGET_FPU_REV >= 8)
+#define TARGET_FPU_ARMV8 (TARGET_FPU_REV >= 8)
/* FPU supports Crypto extensions. */
#define TARGET_CRYPTO \
- (TARGET_VFP && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_CRYPTO))
+ (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_CRYPTO))
/* FPU supports Neon instructions. The setting of this macro gets
revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
and TARGET_HARD_FLOAT to ensure that NEON instructions are
available. */
#define TARGET_NEON \
- (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP \
+ (TARGET_32BIT && TARGET_HARD_FLOAT \
&& ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON))
/* FPU supports ARMv8.1 Adv.SIMD extensions. */
the data layout happens to be consistent for big-endian, so we explicitly allow
that case. */
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
- (TARGET_VFP && TARGET_BIG_END \
+ (TARGET_BIG_END \
&& !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \
&& (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \
|| GET_MODE_SIZE (TO) > UNITS_PER_WORD) \
NO_REGS is returned. */
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
/* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
- ((TARGET_VFP && TARGET_HARD_FLOAT \
- && IS_VFP_CLASS (CLASS)) \
+ ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
? coproc_secondary_reload_class (MODE, X, FALSE) \
: (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
? coproc_secondary_reload_class (MODE, X, TRUE) \
/* If we need to load shorts byte-at-a-time, then we need a scratch. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
/* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
- ((TARGET_VFP && TARGET_HARD_FLOAT \
- && IS_VFP_CLASS (CLASS)) \
+ ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
? coproc_secondary_reload_class (MODE, X, FALSE) : \
(TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
coproc_secondary_reload_class (MODE, X, TRUE) : \
On the ARM, r0-r3 are used to pass args. */
#define FUNCTION_ARG_REGNO_P(REGNO) \
(IN_RANGE ((REGNO), 0, 3) \
- || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
+ || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \
&& IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
|| (TARGET_IWMMXT_ABI \
&& IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
[(set (match_operand:SF 0 "s_register_operand" "")
(div:SF (match_operand:SF 1 "s_register_operand" "")
(match_operand:SF 2 "s_register_operand" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"")
(define_expand "divdf3"
(define_expand "negsf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(neg:SF (match_operand:SF 1 "s_register_operand" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
""
)
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(sqrt:SF (match_operand:SF 1 "s_register_operand" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"")
(define_expand "sqrtdf2"
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, q, m")
(match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,q"))]
"TARGET_32BIT
- && !(TARGET_HARD_FLOAT && TARGET_VFP)
+ && !(TARGET_HARD_FLOAT)
&& !TARGET_IWMMXT
&& ( register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
(define_insn "*arm_movsi_insn"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
(match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk"))]
- "TARGET_ARM && ! TARGET_IWMMXT
- && !(TARGET_HARD_FLOAT && TARGET_VFP)
+ "TARGET_ARM && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
&& ( register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r")
(match_operand:HI 1 "general_operand" "rIk,K,n,r,mi"))]
"TARGET_ARM
- && arm_arch4 && !(TARGET_HARD_FLOAT && TARGET_VFP)
+ && arm_arch4 && !TARGET_HARD_FLOAT
&& (register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode))"
"@
(define_insn "*movhi_bytes"
[(set (match_operand:HI 0 "s_register_operand" "=r,r,r")
(match_operand:HI 1 "arm_rhs_operand" "I,rk,K"))]
- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_VFP)"
+ "TARGET_ARM && !TARGET_HARD_FLOAT"
"@
mov%?\\t%0, %1\\t%@ movhi
mov%?\\t%0, %1\\t%@ movhi
(define_insn "*arm32_movhf"
[(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r")
(match_operand:HF 1 "general_operand" " m,r,r,F"))]
- "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_VFP)
+ "TARGET_32BIT && !TARGET_HARD_FLOAT
&& ( s_register_operand (operands[0], HFmode)
|| s_register_operand (operands[1], HFmode))"
"*
[(set (pc) (if_then_else
(match_operator 0 "expandable_comparison_operator"
[(match_operand:SF 1 "s_register_operand" "")
- (match_operand:SF 2 "arm_float_compare_operand" "")])
+ (match_operand:SF 2 "vfp_compare_operand" "")])
(label_ref (match_operand 3 "" ""))
(pc)))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
[(set (pc) (if_then_else
(match_operator 0 "expandable_comparison_operator"
[(match_operand:DF 1 "s_register_operand" "")
- (match_operand:DF 2 "arm_float_compare_operand" "")])
+ (match_operand:DF 2 "vfp_compare_operand" "")])
(label_ref (match_operand 3 "" ""))
(pc)))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
[(set (match_operand:SI 0 "s_register_operand")
(match_operator:SI 1 "expandable_comparison_operator"
[(match_operand:HF 2 "s_register_operand")
- (match_operand:HF 3 "arm_float_compare_operand")]))]
+ (match_operand:HF 3 "vfp_compare_operand")]))]
"TARGET_VFP_FP16INST"
{
if (!arm_validize_comparison (&operands[1],
[(set (match_operand:SI 0 "s_register_operand" "")
(match_operator:SI 1 "expandable_comparison_operator"
[(match_operand:SF 2 "s_register_operand" "")
- (match_operand:SF 3 "arm_float_compare_operand" "")]))]
+ (match_operand:SF 3 "vfp_compare_operand" "")]))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"emit_insn (gen_cstore_cc (operands[0], operands[1],
operands[2], operands[3])); DONE;"
[(set (match_operand:SI 0 "s_register_operand" "")
(match_operator:SI 1 "expandable_comparison_operator"
[(match_operand:DF 2 "s_register_operand" "")
- (match_operand:DF 3 "arm_float_compare_operand" "")]))]
+ (match_operand:DF 3 "vfp_compare_operand" "")]))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"emit_insn (gen_cstore_cc (operands[0], operands[1],
operands[2], operands[3])); DONE;"
(match_operand:SI 2 "const_int_I_operand" "I")))
(set (match_operand:DF 3 "vfp_hard_register_operand" "")
(mem:DF (match_dup 1)))])]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"*
{
int num_regs = XVECLEN (operands[0], 0);
"@internal
In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
(and (match_code "const_double")
- (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
+ (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
(define_constraint "Dp"
"@internal
In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
(and (match_code "const_double")
- (match_test "TARGET_32BIT && TARGET_VFP
+ (match_test "TARGET_32BIT
&& vfp3_const_double_for_bits (op) > 0")))
(define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
(define_mode_iterator SIDI [SI DI])
;; A list of modes which the VFP unit can handle
-(define_mode_iterator SDF [(SF "TARGET_VFP") (DF "TARGET_VFP_DOUBLE")])
+(define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")])
;; Integer element sizes implemented by IWMMXT.
(define_mode_iterator VMMX [V2SI V4HI V8QI])
(and (match_code "const_double")
(match_test "arm_const_double_rtx (op)"))))
-(define_predicate "arm_float_compare_operand"
- (if_then_else (match_test "TARGET_VFP")
- (match_operand 0 "vfp_compare_operand")
- (match_operand 0 "s_register_operand")))
-
;; True for valid index operands.
(define_predicate "index_operand"
(ior (match_operand 0 "s_register_operand")
(define_predicate "const_double_vcvt_power_of_two_reciprocal"
(and (match_code "const_double")
- (match_test "TARGET_32BIT && TARGET_VFP
- && vfp3_const_double_for_fract_bits (op)")))
+ (match_test "TARGET_32BIT
+ && vfp3_const_double_for_fract_bits (op)")))
(define_predicate "const_double_vcvt_power_of_two"
(and (match_code "const_double")
- (match_test "TARGET_32BIT && TARGET_VFP
+ (match_test "TARGET_32BIT
&& vfp3_const_double_for_bits (op) > 0")))
(define_predicate "neon_struct_operand"
(define_insn "*thumb2_movsi_insn"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l ,*hk,m,*m")
(match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk"))]
- "TARGET_THUMB2 && ! TARGET_IWMMXT
- && !(TARGET_HARD_FLOAT && TARGET_VFP)
+ "TARGET_THUMB2 && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
&& ( register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
"=rk, r, r, m, r, *t, r, *t")
(match_operand:HI 1 "general_operand"
"rIk, K, n, r, mi, r, *t, *t"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
+ "TARGET_ARM && TARGET_HARD_FLOAT
&& !TARGET_VFP_FP16INST
&& (register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode))"
"=rk, r, l, r, m, r, *t, r, *t")
(match_operand:HI 1 "general_operand"
"rk, I, Py, n, r, m, r, *t, *t"))]
- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
+ "TARGET_THUMB2 && TARGET_HARD_FLOAT
&& !TARGET_VFP_FP16INST
&& (register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode))"
(define_insn "*arm_movsi_vfp"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
(match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
- "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
+ "TARGET_ARM && TARGET_HARD_FLOAT
&& ( s_register_operand (operands[0], SImode)
|| s_register_operand (operands[1], SImode))"
"*
(define_insn "*thumb2_movsi_vfp"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r, l,*hk,m, *m,*t, r,*t,*t, *Uv")
(match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))]
- "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
+ "TARGET_THUMB2 && TARGET_HARD_FLOAT
&& ( s_register_operand (operands[0], SImode)
|| s_register_operand (operands[1], SImode))"
"*
(define_insn "*movdi_vfp"
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w, Uv")
(match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8
+ "TARGET_32BIT && TARGET_HARD_FLOAT && arm_tune != cortexa8
&& ( register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))
&& !(TARGET_NEON && CONST_INT_P (operands[1])
(define_insn "*movdi_vfp_cortexa8"
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv")
(match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8
+ "TARGET_32BIT && TARGET_HARD_FLOAT && arm_tune == cortexa8
&& ( register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))
&& !(TARGET_NEON && CONST_INT_P (operands[1])
[(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
(match_operand:HF 1 "general_operand" " m,r,t,r,r,t,F"))]
"TARGET_32BIT
- && TARGET_HARD_FLOAT && TARGET_VFP
+ && TARGET_HARD_FLOAT
&& !TARGET_NEON_FP16
&& !TARGET_VFP_FP16INST
&& ( s_register_operand (operands[0], HFmode)
(define_insn "*movsf_vfp"
[(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t ,Uv,r ,m,t,r")
(match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
+ "TARGET_ARM && TARGET_HARD_FLOAT
&& ( s_register_operand (operands[0], SFmode)
|| s_register_operand (operands[1], SFmode))"
"*
(define_insn "*thumb2_movsf_vfp"
[(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t ,Uv,r ,m,t,r")
(match_operand:SF 1 "general_operand" " ?r,t,Dv,UvE,t, mE,r,t,r"))]
- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
+ "TARGET_THUMB2 && TARGET_HARD_FLOAT
&& ( s_register_operand (operands[0], SFmode)
|| s_register_operand (operands[1], SFmode))"
"*
(define_insn "*movdf_vfp"
[(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,w ,Uv,r, m,w,r")
(match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,G,UvF,w ,mF,r,w,r"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
+ "TARGET_ARM && TARGET_HARD_FLOAT
&& ( register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode))"
"*
(define_insn "*thumb2_movdf_vfp"
[(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,w ,Uv,r ,m,w,r")
(match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,G,UvF,w, mF,r, w,r"))]
- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
+ "TARGET_THUMB2 && TARGET_HARD_FLOAT
&& ( register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode))"
"*
[(match_operand 4 "cc_register" "") (const_int 0)])
(match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
(match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_ARM && TARGET_HARD_FLOAT"
"@
vmov%D3.f32\\t%0, %2
vmov%d3.f32\\t%0, %1
[(match_operand 4 "cc_register" "") (const_int 0)])
(match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
(match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP && !arm_restrict_it"
+ "TARGET_THUMB2 && TARGET_HARD_FLOAT && !arm_restrict_it"
"@
it\\t%D3\;vmov%D3.f32\\t%0, %2
it\\t%d3\;vmov%d3.f32\\t%0, %1
(define_insn "*abssf2_vfp"
[(set (match_operand:SF 0 "s_register_operand" "=t")
(abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vabs%?.f32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(define_insn "*negsf2_vfp"
[(set (match_operand:SF 0 "s_register_operand" "=t,?r")
(neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"@
vneg%?.f32\\t%0, %1
eor%?\\t%0, %1, #-2147483648"
[(set (match_operand:SF 0 "s_register_operand" "=t")
(plus:SF (match_operand:SF 1 "s_register_operand" "t")
(match_operand:SF 2 "s_register_operand" "t")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vadd%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
[(set (match_operand:SF 0 "s_register_operand" "=t")
(minus:SF (match_operand:SF 1 "s_register_operand" "t")
(match_operand:SF 2 "s_register_operand" "t")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vsub%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
[(set (match_operand:SF 0 "s_register_operand" "=&t,t")
(div:SF (match_operand:SF 1 "s_register_operand" "t,t")
(match_operand:SF 2 "s_register_operand" "t,t")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vdiv%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
[(set (match_operand:SF 0 "s_register_operand" "=t")
(mult:SF (match_operand:SF 1 "s_register_operand" "t")
(match_operand:SF 2 "s_register_operand" "t")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
[(set (match_operand:SF 0 "s_register_operand" "=t")
(mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
(match_operand:SF 2 "s_register_operand" "t")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && !flag_rounding_math"
+ "TARGET_32BIT && TARGET_HARD_FLOAT && !flag_rounding_math"
"vnmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
[(set (match_operand:SF 0 "s_register_operand" "=t")
(neg:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
(match_operand:SF 2 "s_register_operand" "t"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vnmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
(match_operand:SF 3 "s_register_operand" "t"))
(match_operand:SF 1 "s_register_operand" "0")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vmla%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
(match_operand:SF 3 "s_register_operand" "t"))
(match_operand:SF 1 "s_register_operand" "0")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vnmls%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(minus:SF (match_operand:SF 1 "s_register_operand" "0")
(mult:SF (match_operand:SF 2 "s_register_operand" "t")
(match_operand:SF 3 "s_register_operand" "t"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vmls%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(neg:SF (match_operand:SF 2 "s_register_operand" "t"))
(match_operand:SF 3 "s_register_operand" "t"))
(match_operand:SF 1 "s_register_operand" "0")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vnmla%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(define_insn "*truncsisf2_vfp"
[(set (match_operand:SI 0 "s_register_operand" "=t")
(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.s32.f32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(define_insn "fixuns_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "=t")
(unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.u32.f32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(define_insn "*floatsisf2_vfp"
[(set (match_operand:SF 0 "s_register_operand" "=t")
(float:SF (match_operand:SI 1 "s_register_operand" "t")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.f32.s32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(define_insn "floatunssisf2"
[(set (match_operand:SF 0 "s_register_operand" "=t")
(unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.f32.u32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(define_insn "*sqrtsf2_vfp"
[(set (match_operand:SF 0 "s_register_operand" "=&t,t")
(sqrt:SF (match_operand:SF 1 "s_register_operand" "t,t")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vsqrt%?.f32\\t%0, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(define_insn "*movcc_vfp"
[(set (reg CC_REGNUM)
(reg VFPCC_REGNUM))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"vmrs%?\\tAPSR_nzcv, FPSCR"
[(set_attr "conds" "set")
(set_attr "type" "f_flag")]
[(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:SF 0 "s_register_operand" "t")
(match_operand:SF 1 "vfp_compare_operand" "tG")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"#"
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
[(set (reg:CCFP VFPCC_REGNUM)
(compare:CCFP (match_dup 0)
(match_dup 1)))
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:SF 0 "s_register_operand" "t")
(match_operand:SF 1 "vfp_compare_operand" "tG")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"#"
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
[(set (reg:CCFPE VFPCC_REGNUM)
(compare:CCFPE (match_dup 0)
(match_dup 1)))
[(set (reg:CCFP VFPCC_REGNUM)
(compare:CCFP (match_operand:SF 0 "s_register_operand" "t,t")
(match_operand:SF 1 "vfp_compare_operand" "t,G")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"@
vcmp%?.f32\\t%0, %1
vcmp%?.f32\\t%0, #0"
[(set (reg:CCFPE VFPCC_REGNUM)
(compare:CCFPE (match_operand:SF 0 "s_register_operand" "t,t")
(match_operand:SF 1 "vfp_compare_operand" "t,G")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"@
vcmpe%?.f32\\t%0, %1
vcmpe%?.f32\\t%0, #0"
[(set (match_operand:BLK 0 "memory_operand" "=m")
(unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")]
UNSPEC_PUSH_MULT))])]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
"* return vfp_output_vstmd (operands);"
[(set_attr "type" "f_stored")]
)
;; Write Floating-point Status and Control Register.
(define_insn "set_fpscr"
[(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)]
- "TARGET_VFP && TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT"
"mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR"
[(set_attr "type" "mrs")])
(define_insn "get_fpscr"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))]
- "TARGET_VFP && TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT"
"mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR"
[(set_attr "type" "mrs")])