* Added support for the Cortex-A715 CPU.
* Added support for the Cortex-X3 CPU.
+* Added support for assembly for RME MEC (Memory Encryption Contexts).
Changes to the AMDGPU Backend
-----------------------------
"Don't place a BTI instruction "
"after a return-twice">;
+def FeatureMEC : SubtargetFeature<"mec", "HasMEC",
+ "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>;
+
//===----------------------------------------------------------------------===//
// Architectures.
//
def HasV9_0aOps : SubtargetFeature<
"v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions",
- [HasV8_5aOps, FeatureSVE2]>;
+ [HasV8_5aOps, FeatureMEC, FeatureSVE2]>;
def HasV9_1aOps : SubtargetFeature<
"v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions",
def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>;
}
+let Requires = [{ {AArch64::FeatureMEC} }] in {
+def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b000>;
+def : DC<"CIPAE", 0b100, 0b0111, 0b1110, 0b111>;
+}
+
//===----------------------------------------------------------------------===//
// IC (instruction cache maintenance) instruction options.
//===----------------------------------------------------------------------===//
def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>;
}
+// v9a Memory Encryption Contexts Extension registers
+let Requires = [{ {AArch64::FeatureMEC} }] in {
+def : ROSysReg<"MECIDR_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b111>;
+def : RWSysReg<"MECID_P0_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b000>;
+def : RWSysReg<"MECID_A0_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b001>;
+def : RWSysReg<"MECID_P1_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b010>;
+def : RWSysReg<"MECID_A1_EL2", 0b11, 0b100, 0b1010, 0b1000, 0b011>;
+def : RWSysReg<"VMECID_P_EL2", 0b11, 0b100, 0b1010, 0b1001, 0b000>;
+def : RWSysReg<"VMECID_A_EL2", 0b11, 0b100, 0b1010, 0b1001, 0b001>;
+def : RWSysReg<"MECID_RL_A_EL3", 0b11, 0b110, 0b1010, 0b1010, 0b001>;
+}
+
// v9-a Scalable Matrix Extension (SME) registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureSME} }] in {
{"sme2p1", {AArch64::FeatureSME2p1}},
{"hbc", {AArch64::FeatureHBC}},
{"mops", {AArch64::FeatureMOPS}},
+ {"mec", {AArch64::FeatureMEC}},
// FIXME: Unsupported extensions
{"lor", {}},
{"rdma", {}},
--- /dev/null
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mec < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-MEC %s
+
+ mrs x0, MECIDR_EL2
+// CHECK: mrs x0, MECIDR_EL2 // encoding: [0xe0,0xa8,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+ mrs x0, MECID_P0_EL2
+// CHECK: mrs x0, MECID_P0_EL2 // encoding: [0x00,0xa8,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+ mrs x0, MECID_A0_EL2
+// CHECK: mrs x0, MECID_A0_EL2 // encoding: [0x20,0xa8,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+ mrs x0, MECID_P1_EL2
+// CHECK: mrs x0, MECID_P1_EL2 // encoding: [0x40,0xa8,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+ mrs x0, MECID_A1_EL2
+// CHECK: mrs x0, MECID_A1_EL2 // encoding: [0x60,0xa8,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+ mrs x0, VMECID_P_EL2
+// CHECK: mrs x0, VMECID_P_EL2 // encoding: [0x00,0xa9,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+ mrs x0, VMECID_A_EL2
+// CHECK: mrs x0, VMECID_A_EL2 // encoding: [0x20,0xa9,0x3c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+ mrs x0, MECID_RL_A_EL3
+// CHECK: mrs x0, MECID_RL_A_EL3 // encoding: [0x20,0xaa,0x3e,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register
+ msr MECID_P0_EL2, x0
+// CHECK: msr MECID_P0_EL2, x0 // encoding: [0x00,0xa8,0x1c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+ msr MECID_A0_EL2, x0
+// CHECK: msr MECID_A0_EL2, x0 // encoding: [0x20,0xa8,0x1c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+ msr MECID_P1_EL2, x0
+// CHECK: msr MECID_P1_EL2, x0 // encoding: [0x40,0xa8,0x1c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+ msr MECID_A1_EL2, x0
+// CHECK: msr MECID_A1_EL2, x0 // encoding: [0x60,0xa8,0x1c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+ msr VMECID_P_EL2, x0
+// CHECK: msr VMECID_P_EL2, x0 // encoding: [0x00,0xa9,0x1c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+ msr VMECID_A_EL2, x0
+// CHECK: msr VMECID_A_EL2, x0 // encoding: [0x20,0xa9,0x1c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+ msr MECID_RL_A_EL3, x0
+// CHECK: msr MECID_RL_A_EL3, x0 // encoding: [0x20,0xaa,0x1e,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
+
+ dc cigdpae, x0
+// CHECK: dc cigdpae, x0 // encoding: [0x00,0x7e,0x0c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIGDPAE requires: mec
+ dc cipae, x0
+// CHECK: dc cipae, x0 // encoding: [0xe0,0x7e,0x0c,0xd5]
+// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIPAE requires: mec
--- /dev/null
+# RUN: llvm-mc -triple=aarch64 -mattr=+mec -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v9a -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -disassemble %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-MEC
+
+[0xe0,0xa8,0x3c,0xd5]
+# CHECK: mrs x0, MECIDR_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_7
+[0x00,0xa8,0x3c,0xd5]
+# CHECK: mrs x0, MECID_P0_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_0
+[0x20,0xa8,0x3c,0xd5]
+# CHECK: mrs x0, MECID_A0_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_1
+[0x40,0xa8,0x3c,0xd5]
+# CHECK: mrs x0, MECID_P1_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_2
+[0x60,0xa8,0x3c,0xd5]
+# CHECK: mrs x0, MECID_A1_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_3
+[0x00,0xa9,0x3c,0xd5]
+# CHECK: mrs x0, VMECID_P_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C9_0
+[0x20,0xa9,0x3c,0xd5]
+# CHECK: mrs x0, VMECID_A_EL2
+# CHECK-NO-MEC: mrs x0, S3_4_C10_C9_1
+[0x20,0xaa,0x3e,0xd5]
+# CHECK: mrs x0, MECID_RL_A_EL3
+# CHECK-NO-MEC: mrs x0, S3_6_C10_C10_1
+[0x00,0xa8,0x1c,0xd5]
+# CHECK: msr MECID_P0_EL2, x0
+# CHECK-NO-MEC: msr S3_4_C10_C8_0, x0
+[0x20,0xa8,0x1c,0xd5]
+# CHECK: msr MECID_A0_EL2, x0
+# CHECK-NO-MEC: msr S3_4_C10_C8_1, x0
+[0x40,0xa8,0x1c,0xd5]
+# CHECK: msr MECID_P1_EL2, x0
+# CHECK-NO-MEC: msr S3_4_C10_C8_2, x0
+[0x60,0xa8,0x1c,0xd5]
+# CHECK: msr MECID_A1_EL2, x0
+# CHECK-NO-MEC: msr S3_4_C10_C8_3, x0
+[0x00,0xa9,0x1c,0xd5]
+# CHECK: msr VMECID_P_EL2, x0
+# CHECK-NO-MEC: msr S3_4_C10_C9_0, x0
+[0x20,0xa9,0x1c,0xd5]
+# CHECK: msr VMECID_A_EL2, x0
+# CHECK-NO-MEC: msr S3_4_C10_C9_1, x0
+[0x20,0xaa,0x1e,0xd5]
+# CHECK: msr MECID_RL_A_EL3, x0
+# CHECK-NO-MEC: msr S3_6_C10_C10_1, x0
+[0x00,0x7e,0x0c,0xd5]
+# CHECK: dc cigdpae, x0
+# CHECK-NO-MEC: sys #4, c7, c14, #0, x0
+[0xe0,0x7e,0x0c,0xd5]
+# CHECK: dc cipae, x0
+# CHECK-NO-MEC: sys #4, c7, c14, #7, x0