Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  ARM1136: Fix cache range checks
  mx6: Make pad name macro consistent with the datasheet
  mx28: Fix elftosb source link in README.mx28_common
  doc: README.mx28_common: Add missing entry into Contents

Signed-off-by: Wolfgang Denk <wd@denx.de>

diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
index c2636b1..a9991e7 100644 (file)
--- a/arch/nds32/cpu/n1213/ag101/cpu.c
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -82,115 +82,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
        /*NOTREACHED*/
 }
-
-static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
-{
-       if (cache == ICACHE)
-               return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
-                                       >> ICM_CFG_OFF_ISZ) - 1);
-       else
-               return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
-                                       >> DCM_CFG_OFF_DSZ) - 1);
-}
-
-void dcache_flush_range(unsigned long start, unsigned long end)
-{
-       unsigned long line_size;
-
-       line_size = CACHE_LINE_SIZE(DCACHE);
-
-       while (end > start) {
-               __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
-               __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
-               start += line_size;
-       }
-}
-
-void icache_inval_range(unsigned long start, unsigned long end)
-{
-       unsigned long line_size;
-
-       line_size = CACHE_LINE_SIZE(ICACHE);
-       while (end > start) {
-               __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
-               start += line_size;
-       }
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-       dcache_flush_range(addr, addr + size);
-       icache_inval_range(addr, addr + size);
-}
-
-void icache_enable(void)
-{
-       __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "ori    $p0, $p0, 0x01\n\t"
-               "mtsr   $p0, $mr8\n\t"
-               "isb\n\t"
-       );
-}
-
-void icache_disable(void)
-{
-       __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "li     $p1, ~0x01\n\t"
-               "and    $p0, $p0, $p1\n\t"
-               "mtsr   $p0, $mr8\n\t"
-               "isb\n\t"
-       );
-}
-
-int icache_status(void)
-{
-       int ret;
-
-        __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "andi   %0,  $p0, 0x01\n\t"
-               : "=r" (ret)
-               :
-               : "memory"
-       );
-
-        return ret;
-}
-
-void dcache_enable(void)
-{
-        __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "ori    $p0, $p0, 0x02\n\t"
-               "mtsr   $p0, $mr8\n\t"
-               "isb\n\t"
-       );
-}
-
-void dcache_disable(void)
-{
-        __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "li     $p1, ~0x02\n\t"
-               "and    $p0, $p0, $p1\n\t"
-               "mtsr   $p0, $mr8\n\t"
-               "isb\n\t"
-       );
-}
-
-int dcache_status(void)
-{
-       int ret;
-
-       __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "andi   %0, $p0, 0x02\n\t"
-               : "=r" (ret)
-               :
-               : "memory"
-        );
-
-        return ret;
-}

diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c
index ed88b52..252b69d 100644 (file)
--- a/arch/nds32/cpu/n1213/ag102/cpu.c
+++ b/arch/nds32/cpu/n1213/ag102/cpu.c
@@ -81,115 +81,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
        /*NOTREACHED*/
 }
-
-static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
-{
-       if (cache == ICACHE)
-               return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
-                                       >> ICM_CFG_OFF_ISZ) - 1);
-       else
-               return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
-                                       >> DCM_CFG_OFF_DSZ) - 1);
-}
-
-void dcache_flush_range(unsigned long start, unsigned long end)
-{
-       unsigned long line_size;
-
-       line_size = CACHE_LINE_SIZE(DCACHE);
-
-       while (end > start) {
-               __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
-               __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
-               start += line_size;
-       }
-}
-
-void icache_inval_range(unsigned long start, unsigned long end)
-{
-       unsigned long line_size;
-
-       line_size = CACHE_LINE_SIZE(ICACHE);
-       while (end > start) {
-               __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
-               start += line_size;
-       }
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-       dcache_flush_range(addr, addr + size);
-       icache_inval_range(addr, addr + size);
-}
-
-void icache_enable(void)
-{
-       __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "ori    $p0, $p0, 0x01\n\t"
-               "mtsr   $p0, $mr8\n\t"
-               "isb\n\t"
-       );
-}
-
-void icache_disable(void)
-{
-       __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "li     $p1, ~0x01\n\t"
-               "and    $p0, $p0, $p1\n\t"
-               "mtsr   $p0, $mr8\n\t"
-               "isb\n\t"
-       );
-}
-
-int icache_status(void)
-{
-       int ret;
-
-        __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "andi   %0,  $p0, 0x01\n\t"
-               : "=r" (ret)
-               :
-               : "memory"
-       );
-
-        return ret;
-}
-
-void dcache_enable(void)
-{
-        __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "ori    $p0, $p0, 0x02\n\t"
-               "mtsr   $p0, $mr8\n\t"
-               "isb\n\t"
-       );
-}
-
-void dcache_disable(void)
-{
-        __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "li     $p1, ~0x02\n\t"
-               "and    $p0, $p0, $p1\n\t"
-               "mtsr   $p0, $mr8\n\t"
-               "isb\n\t"
-       );
-}
-
-int dcache_status(void)
-{
-       int ret;
-
-       __asm__ __volatile__ (
-               "mfsr   $p0, $mr8\n\t"
-               "andi   %0, $p0, 0x02\n\t"
-               : "=r" (ret)
-               :
-               : "memory"
-        );
-
-        return ret;
-}

diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
index e5c31c3..581a2e7 100644 (file)
--- a/arch/nds32/lib/Makefile
+++ b/arch/nds32/lib/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(ARCH).o
 
-OBJS   := board.o bootm.o interrupts.o
+OBJS   := board.o bootm.o cache.o interrupts.o
 
 all:   $(LIB)
 

diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c
new file mode 100644 (file)
index 0000000..0f1a886
--- /dev/null
+++ b/arch/nds32/lib/cache.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2012 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307         USA
+ *
+ */
+
+#include <common.h>
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+       if (cache == ICACHE)
+               return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+                                       >> ICM_CFG_OFF_ISZ) - 1);
+       else
+               return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+                                       >> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+       unsigned long line_size;
+
+       line_size = CACHE_LINE_SIZE(DCACHE);
+
+       while (end > start) {
+               asm volatile (
+                       "\n\tcctl %0, L1D_VA_WB"
+                       "\n\tcctl %0, L1D_VA_INVAL"
+                       :
+                       : "r" (start)
+               );
+               start += line_size;
+       }
+}
+
+void invalidate_icache_range(unsigned long start, unsigned long end)
+{
+       unsigned long line_size;
+
+       line_size = CACHE_LINE_SIZE(ICACHE);
+       while (end > start) {
+               asm volatile (
+                       "\n\tcctl %0, L1I_VA_INVAL"
+                       :
+                       : "r"(start)
+               );
+               start += line_size;
+       }
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+       unsigned long line_size;
+
+       line_size = CACHE_LINE_SIZE(DCACHE);
+       while (end > start) {
+               asm volatile (
+                       "\n\tcctl %0, L1D_VA_INVAL"
+                       :
+                       : "r"(start)
+               );
+               start += line_size;
+       }
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+       flush_dcache_range(addr, addr + size);
+       invalidate_icache_range(addr, addr + size);
+}
+
+void icache_enable(void)
+{
+       asm volatile (
+               "mfsr   $p0, $mr8\n\t"
+               "ori    $p0, $p0, 0x01\n\t"
+               "mtsr   $p0, $mr8\n\t"
+               "isb\n\t"
+       );
+}
+
+void icache_disable(void)
+{
+       asm volatile (
+               "mfsr   $p0, $mr8\n\t"
+               "li     $p1, ~0x01\n\t"
+               "and    $p0, $p0, $p1\n\t"
+               "mtsr   $p0, $mr8\n\t"
+               "isb\n\t"
+       );
+}
+
+int icache_status(void)
+{
+       int ret;
+
+       asm volatile (
+               "mfsr   $p0, $mr8\n\t"
+               "andi   %0,  $p0, 0x01\n\t"
+               : "=r" (ret)
+               :
+               : "memory"
+       );
+
+       return ret;
+}
+
+void dcache_enable(void)
+{
+       asm volatile (
+               "mfsr   $p0, $mr8\n\t"
+               "ori    $p0, $p0, 0x02\n\t"
+               "mtsr   $p0, $mr8\n\t"
+               "isb\n\t"
+       );
+}
+
+void dcache_disable(void)
+{
+       asm volatile (
+               "mfsr   $p0, $mr8\n\t"
+               "li     $p1, ~0x02\n\t"
+               "and    $p0, $p0, $p1\n\t"
+               "mtsr   $p0, $mr8\n\t"
+               "isb\n\t"
+       );
+}
+
+int dcache_status(void)
+{
+       int ret;
+
+       asm volatile (
+               "mfsr   $p0, $mr8\n\t"
+               "andi   %0, $p0, 0x02\n\t"
+               : "=r" (ret)
+               :
+               : "memory"
+       );
+
+       return ret;
+}

diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index 012ab6b..687f5e9 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -42,7 +42,7 @@ COBJS-$(CONFIG_PCIE) += pcie.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 
 # Stub implementations of cache management functions for USB
-COBJS-$(CONFIG_USB_EHCI) += cache.o
+COBJS-y += cache.o
 
 ifdef CONFIG_FSL_DDR2
 COBJS_LN-$(CONFIG_MPC8349) += ddr-gen2.o

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 7d65aa7..34f6c54 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -131,7 +131,7 @@ COBJS       += tlb.o
 COBJS  += traps.o
 
 # Stub implementations of cache management functions for USB
-COBJS-$(CONFIG_USB_EHCI) += cache.o
+COBJS += cache.o
 
 SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))

diff --git a/include/common.h b/include/common.h
index be9c278..39859d3 100644 (file)
--- a/include/common.h
+++ b/include/common.h
@@ -39,7 +39,6 @@ typedef volatile unsigned char        vu_char;
 #include <linux/bitops.h>
 #include <linux/types.h>
 #include <linux/string.h>
-#include <linux/compiler.h>
 #include <asm/ptrace.h>
 #include <stdarg.h>
 #if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
@@ -959,7 +958,7 @@ int cpu_release(int nr, int argc, char * const argv[]);
  */
 #define DEFINE_ALIGN_BUFFER(type, name, size, align)                   \
        static char __##name[roundup(size * sizeof(type), align)]       \
-                       __aligned(align);                               \
+                       __attribute__((aligned(align)));                                \
                                                                        \
        static type *name = (type *)__##name
 #define DEFINE_CACHE_ALIGN_BUFFER(type, name, size)                    \