Updating InstructionSet_BMI1/2 to be controlled by the COMPlus_EnableAVX flag and...

Commit migrated from https://github.com/dotnet/coreclr/commit/52f9c8a5258267168c97ebb54bce729b26ea3c30

diff --git a/src/coreclr/src/jit/compiler.cpp b/src/coreclr/src/jit/compiler.cpp
index 8f803b9..f28394b 100644 (file)
--- a/src/coreclr/src/jit/compiler.cpp
+++ b/src/coreclr/src/jit/compiler.cpp
@@ -2367,14 +2367,18 @@ static bool configEnableISA(InstructionSet isa)
             return false;
     }
 #else
-    // We have a retail config switch that can disable AVX/FMA/AVX2 instructions
-    if ((isa == InstructionSet_AVX) || (isa == InstructionSet_FMA) || (isa == InstructionSet_AVX2))
-    {
-        return JitConfig.EnableAVX() != 0;
-    }
-    else
+    // We have a retail config switch that can disable instruction sets reliant on the VEX encoding
+    switch (isa)
     {
-        return true;
+        case InstructionSet_AVX:
+        case InstructionSet_FMA:
+        case InstructionSet_AVX2:
+        case InstructionSet_BMI1:
+        case InstructionSet_BMI2:
+            return JitConfig.EnableAVX() != 0;
+
+        default:
+            return true;
     }
 #endif
 }
@@ -2437,20 +2441,6 @@ void Compiler::compSetProcessor()
                 opts.setSupportedISA(InstructionSet_AES);
             }
         }
-        if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_BMI1))
-        {
-            if (configEnableISA(InstructionSet_BMI1))
-            {
-                opts.setSupportedISA(InstructionSet_BMI1);
-            }
-        }
-        if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_BMI2))
-        {
-            if (configEnableISA(InstructionSet_BMI2))
-            {
-                opts.setSupportedISA(InstructionSet_BMI2);
-            }
-        }
         if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_LZCNT))
         {
             if (configEnableISA(InstructionSet_LZCNT))
@@ -2508,7 +2498,7 @@ void Compiler::compSetProcessor()
             }
         }
 
-        // There are currently two sets of flags that control AVX, FMA, and AVX2 support:
+        // There are currently two sets of flags that control instruction sets that require the VEX encoding:
         // These are the general EnableAVX flag and the individual ISA flags. We need to
         // check both for any given isa.
         if (JitConfig.EnableAVX())
@@ -2534,6 +2524,20 @@ void Compiler::compSetProcessor()
                     opts.setSupportedISA(InstructionSet_AVX2);
                 }
             }
+            if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_BMI1))
+            {
+                if (configEnableISA(InstructionSet_BMI1))
+                {
+                    opts.setSupportedISA(InstructionSet_BMI1);
+                }
+            }
+            if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_BMI2))
+            {
+                if (configEnableISA(InstructionSet_BMI2))
+                {
+                    opts.setSupportedISA(InstructionSet_BMI2);
+                }
+            }
         }
     }
 

diff --git a/src/coreclr/src/jit/compiler.h b/src/coreclr/src/jit/compiler.h
index ca2d426..2248b32 100644 (file)
--- a/src/coreclr/src/jit/compiler.h
+++ b/src/coreclr/src/jit/compiler.h
@@ -2172,11 +2172,8 @@ public:
                                                    GenTree*       op1,
                                                    GenTree*       op2,
                                                    NamedIntrinsic hwIntrinsicID);
-    GenTreeHWIntrinsic* gtNewScalarHWIntrinsicNode(var_types      type,
-                                                   GenTree*       op1,
-                                                   GenTree*       op2,
-                                                   GenTree*       op3,
-                                                   NamedIntrinsic hwIntrinsicID);
+    GenTreeHWIntrinsic* gtNewScalarHWIntrinsicNode(
+        var_types type, GenTree* op1, GenTree* op2, GenTree* op3, NamedIntrinsic hwIntrinsicID);
     GenTree* gtNewMustThrowException(unsigned helper, var_types type, CORINFO_CLASS_HANDLE clsHnd);
     CORINFO_CLASS_HANDLE gtGetStructHandleForHWSIMD(var_types simdType, var_types simdBaseType);
 #endif // FEATURE_HW_INTRINSICS

diff --git a/src/coreclr/src/jit/gentree.cpp b/src/coreclr/src/jit/gentree.cpp
index d2e06f9..fc1250c 100644 (file)
--- a/src/coreclr/src/jit/gentree.cpp
+++ b/src/coreclr/src/jit/gentree.cpp
@@ -17512,11 +17512,8 @@ GenTreeHWIntrinsic* Compiler::gtNewScalarHWIntrinsicNode(var_types      type,
     return new (this, GT_HWIntrinsic) GenTreeHWIntrinsic(type, op1, op2, hwIntrinsicID, TYP_UNKNOWN, 0);
 }
 
-GenTreeHWIntrinsic* Compiler::gtNewScalarHWIntrinsicNode(var_types      type,
-                                                         GenTree*       op1,
-                                                         GenTree*       op2,
-                                                         GenTree*       op3,
-                                                         NamedIntrinsic hwIntrinsicID)
+GenTreeHWIntrinsic* Compiler::gtNewScalarHWIntrinsicNode(
+    var_types type, GenTree* op1, GenTree* op2, GenTree* op3, NamedIntrinsic hwIntrinsicID)
 {
     SetOpLclRelatedToSIMDIntrinsic(op1);
     SetOpLclRelatedToSIMDIntrinsic(op2);

diff --git a/src/coreclr/src/jit/hwintrinsicxarch.cpp b/src/coreclr/src/jit/hwintrinsicxarch.cpp
index 3d29159..7009624 100644 (file)
--- a/src/coreclr/src/jit/hwintrinsicxarch.cpp
+++ b/src/coreclr/src/jit/hwintrinsicxarch.cpp
@@ -1295,8 +1295,8 @@ GenTree* Compiler::impBMI1Intrinsic(NamedIntrinsic        intrinsic,
         {
             assert(sig->numArgs == 2);
 
-            GenTree*  op2      = impPopStack().val;
-            GenTree*  op1      = impPopStack().val;
+            GenTree* op2 = impPopStack().val;
+            GenTree* op1 = impPopStack().val;
 
             return gtNewScalarHWIntrinsicNode(callType, op1, op2, intrinsic);
         }