The board is unmaintained and maintainer doesn't respond.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Unknown / orphaned boards:
Board CPU Last known maintainer / Comment
.........................................................................
- cradle xscale/pxa Kyle Harris <kharris@nexus-tech.net> / dead address
lubbock xscale/pxa Kyle Harris <kharris@nexus-tech.net> / dead address
imx31_phycore_eet i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := cradle.o flash.o
-
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/pxa-regs.h>
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-
-/* local prototypes */
-void set_led (int led, int color);
-void error_code_halt (int code);
-int init_sio (int led, unsigned long base);
-inline void cradle_outb (unsigned short val, unsigned long base,
- unsigned long reg);
-inline unsigned char cradle_inb (unsigned long base, unsigned long reg);
-inline void sleep (int i);
-
-inline void
-/**********************************************************/
-sleep (int i)
-/**********************************************************/
-{
- while (i--) {
- udelay (1000000);
- }
-}
-
-void
-/**********************************************************/
-error_code_halt (int code)
-/**********************************************************/
-{
- while (1) {
- led_code (code, RED);
- sleep (1);
- led_code (0, OFF);
- sleep (1);
- }
-}
-
-void
-/**********************************************************/
-led_code (int code, int color)
-/**********************************************************/
-{
- int i;
-
- code &= 0xf; /* only 4 leds */
-
- for (i = 0; i < 4; i++) {
- if (code & (1 << i)) {
- set_led (i, color);
- } else {
- set_led (i, OFF);
- }
- }
-}
-
-void
-/**********************************************************/
-set_led (int led, int color)
-/**********************************************************/
-{
- int shift = led * 2;
- unsigned long mask = 0x3 << shift;
-
- writel(mask, GPCR2); /* clear bits */
- writel((color << shift), GPSR2); /* set bits */
- udelay (5000);
-}
-
-inline void
-/**********************************************************/
-cradle_outb (unsigned short val, unsigned long base, unsigned long reg)
-/**********************************************************/
-{
- *(volatile unsigned short *) (base + (reg * 2)) = val;
-}
-
-inline unsigned char
-/**********************************************************/
-cradle_inb (unsigned long base, unsigned long reg)
-/**********************************************************/
-{
- unsigned short val;
-
- val = *(volatile unsigned short *) (base + (reg * 2));
- return (val & 0xff);
-}
-
-int
-/**********************************************************/
-init_sio (int led, unsigned long base)
-/**********************************************************/
-{
- unsigned char val;
-
- set_led (led, YELLOW);
- val = cradle_inb (base, CRADLE_SIO_INDEX);
- val = cradle_inb (base, CRADLE_SIO_INDEX);
- if (val != 0) {
- set_led (led, RED);
- return -1;
- }
-
- /* map SCC2 to COM1 */
- cradle_outb (0x01, base, CRADLE_SIO_INDEX);
- cradle_outb (0x00, base, CRADLE_SIO_DATA);
-
- /* enable SCC2 extended regs */
- cradle_outb (0x40, base, CRADLE_SIO_INDEX);
- cradle_outb (0xa0, base, CRADLE_SIO_DATA);
-
- /* enable SCC2 clock multiplier */
- cradle_outb (0x51, base, CRADLE_SIO_INDEX);
- cradle_outb (0x04, base, CRADLE_SIO_DATA);
-
- /* enable SCC2 */
- cradle_outb (0x00, base, CRADLE_SIO_INDEX);
- cradle_outb (0x04, base, CRADLE_SIO_DATA);
-
- /* map SCC2 DMA to channel 0 */
- cradle_outb (0x4f, base, CRADLE_SIO_INDEX);
- cradle_outb (0x09, base, CRADLE_SIO_DATA);
-
- /* read ID from SIO to check operation */
- cradle_outb (0xe4, base, 0x3f8 + 0x3);
- val = cradle_inb (base, 0x3f8 + 0x0);
- if ((val & 0xf0) != 0x20) {
- set_led (led, RED);
- /* disable SCC2 */
- cradle_outb (0, base, CRADLE_SIO_INDEX);
- cradle_outb (0, base, CRADLE_SIO_DATA);
- return -1;
- }
- /* set back to bank 0 */
- cradle_outb (0, base, 0x3f8 + 0x3);
- set_led (led, GREEN);
- return 0;
-}
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int
-/**********************************************************/
-board_late_init (void)
-/**********************************************************/
-{
- return (0);
-}
-
-int
-/**********************************************************/
-board_init (void)
-/**********************************************************/
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- led_code (0xf, YELLOW);
-
- /* arch number of HHP Cradle */
- gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- /* Init SIOs to enable SCC2 */
- udelay (100000); /* delay makes it look neat */
- init_sio (0, CRADLE_SIO1_PHYS);
- udelay (100000);
- init_sio (1, CRADLE_SIO2_PHYS);
- udelay (100000);
- init_sio (2, CRADLE_SIO3_PHYS);
- udelay (100000);
- set_led (3, GREEN);
-
- return 1;
-}
-
-extern void pxa_dram_init(void);
-int dram_init(void)
-{
- pxa_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#define FLASH_BANK_SIZE 0x400000
-#define MAIN_SECT_SIZE 0x20000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-
-/*-----------------------------------------------------------------------
- */
-
-ulong flash_init (void)
-{
- int i, j;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- ulong flashbase = 0;
-
- flash_info[i].flash_id =
- (INTEL_MANUFACT & FLASH_VENDMASK) |
- (INTEL_ID_28F128J3 & FLASH_TYPEMASK);
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
- switch (i) {
- case 0:
- flashbase = PHYS_FLASH_1;
- break;
- case 1:
- flashbase = PHYS_FLASH_2;
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- for (j = 0; j < flash_info[i].sector_count; j++) {
- flash_info[i].start[j] =
- flashbase + j * MAIN_SECT_SIZE;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i, j;
-
- for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) {
- switch (info->flash_id & FLASH_VENDMASK) {
- case (INTEL_MANUFACT & FLASH_VENDMASK):
- printf ("Intel: ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
- printf ("28F320J3A (32Mbit)\n");
- break;
- case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
- printf ("28F128J3 (128Mbit)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- goto Done;
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- info++;
- }
-
-Done: ;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- int rc = ERR_OK;
- ulong start;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return ERR_UNKNOWN_FLASH_TYPE;
-
- if ((s_first < 0) || (s_first > s_last)) {
- return ERR_INVAL;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) !=
- (INTEL_MANUFACT & FLASH_VENDMASK)) {
- return ERR_UNKNOWN_FLASH_VENDOR;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot)
- return ERR_PROTECTED;
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
- flag = disable_interrupts ();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
-
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- if (info->protect[sect] == 0) { /* not protected */
- vu_short *addr = (vu_short *) (info->start[sect]);
-
- *addr = 0x20; /* erase setup */
- *addr = 0xD0; /* erase confirm */
-
- while ((*addr & 0x80) != 0x80) {
- if (get_timer(start) >
- CONFIG_SYS_FLASH_ERASE_TOUT) {
- *addr = 0xB0; /* suspend erase */
- *addr = 0xFF; /* reset to read mode */
- rc = ERR_TIMOUT;
- goto outahere;
- }
- }
-
- /* clear status register command */
- *addr = 0x50;
- /* reset to read mode */
- *addr = 0xFF;
- }
- printf ("ok.\n");
- }
- if (ctrlc ())
- printf ("User Interrupt!\n");
-
-outahere:
-
- /* allow flash to settle - wait 10 ms */
- udelay_masked (10000);
-
- if (flag)
- enable_interrupts ();
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash
- */
-
-static int write_word (flash_info_t * info, ulong dest, ushort data)
-{
- vu_short *addr = (vu_short *) dest, val;
- int rc = ERR_OK;
- int flag;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased
- */
- if ((*addr & data) != data)
- return ERR_NOT_ERASED;
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
- flag = disable_interrupts ();
-
- /* clear status register command */
- *addr = 0x50;
-
- /* program set-up command */
- *addr = 0x40;
-
- /* latch address/data */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait while polling the status register */
- while (((val = *addr) & 0x80) != 0x80) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- rc = ERR_TIMOUT;
- /* suspend program command */
- *addr = 0xB0;
- goto outahere;
- }
- }
-
- if (val & 0x1A) { /* check for error */
- printf ("\nFlash write error %02x at address %08lx\n",
- (int) val, (unsigned long) dest);
- if (val & (1 << 3)) {
- printf ("Voltage range error.\n");
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
- if (val & (1 << 1)) {
- printf ("Device protect error.\n");
- rc = ERR_PROTECTED;
- goto outahere;
- }
- if (val & (1 << 4)) {
- printf ("Programming error.\n");
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
- rc = ERR_PROG_ERROR;
- goto outahere;
- }
-
-outahere:
- /* read array command */
- *addr = 0xFF;
-
- if (flag)
- enable_interrupts ();
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash.
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- ushort data;
- int l;
- int i, rc;
-
- wp = (addr & ~1); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *) cp << 8);
- }
- for (; i < 2 && cnt > 0; ++i) {
- data = (data >> 8) | (*src++ << 8);
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 2; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *) cp << 8);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 2;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 2) {
- data = *((vu_short *) src);
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- src += 2;
- wp += 2;
- cnt -= 2;
- }
-
- if (cnt == 0) {
- return ERR_OK;
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
- data = (data >> 8) | (*src++ << 8);
- --cnt;
- }
- for (; i < 2; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *) cp << 8);
- }
-
- return write_word (info, wp, data);
-}
dvlhost arm ixp
balloon3 arm pxa
colibri_pxa270 arm pxa
-cradle arm pxa
lubbock arm pxa
palmld arm pxa
palmtc arm pxa
Board Arch CPU removed Commit last known maintainer/contact
=============================================================================
+cradle arm pxa 4e24f8a 2011-25-11 Kyle Harris <kharris@nexus-tech.net>
cerf250 arm pxa a3f1241 2011-25-11 Prakash Kumar <prakash@embedx.com>
mpq101 powerpc mpc85xx - 2011-10-23 Alex Dubov <oakad@yahoo.com>
ixdpg425 arm ixp 0ca8eb7 2011-09-22 Stefan Roese <sr@denx.de>
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
-#define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */
-
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_TEXT_BASE 0x0
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE 0x10000300
-#define CONFIG_SMC91111_EXT_PHY
-#define CONFIG_SMC_USE_32_BIT
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200"
-#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
-#define CONFIG_NETMASK 255.255.0.0
-#define CONFIG_IPADDR 192.168.0.21
-#define CONFIG_SERVERIP 192.168.0.250
-#define CONFIG_BOOTCOMMAND "bootm 40000"
-#define CONFIG_CMDLINE_TAG
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
-
- /* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x04000000
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x00020000 /* absolute address for now */
-#define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
-
-/******************************************************************************
- *
- * CPU specific defines
- *
- ******************************************************************************/
-
-/*
- * GPIO settings
- *
- * GPIO pin assignments
- * GPIO Name Dir Out AF
- * 0 NC
- * 1 NC
- * 2 SIRQ1 I
- * 3 SIRQ2 I
- * 4 SIRQ3 I
- * 5 DMAACK1 O 0
- * 6 DMAACK2 O 0
- * 7 DMAACK3 O 0
- * 8 TC1 O 0
- * 9 TC2 O 0
- * 10 TC3 O 0
- * 11 nDMAEN O 1
- * 12 AENCTRL O 0
- * 13 PLDTC O 0
- * 14 ETHIRQ I
- * 15 NC
- * 16 NC
- * 17 NC
- * 18 RDY I
- * 19 DMASIO I
- * 20 ETHIRQ NC
- * 21 NC
- * 22 PGMEN O 1 FIXME for debug only enable flash
- * 23 NC
- * 24 NC
- * 25 NC
- * 26 NC
- * 27 NC
- * 28 NC
- * 29 NC
- * 30 NC
- * 31 NC
- * 32 NC
- * 33 NC
- * 34 FFRXD I 01
- * 35 FFCTS I 01
- * 36 FFDCD I 01
- * 37 FFDSR I 01
- * 38 FFRI I 01
- * 39 FFTXD O 1 10
- * 40 FFDTR O 0 10
- * 41 FFRTS O 0 10
- * 42 RS232FOFF O 0 00
- * 43 NC
- * 44 NC
- * 45 IRSL0 O 0
- * 46 IRRX0 I 01
- * 47 IRTX0 O 0 10
- * 48 NC
- * 49 nIOWE O 0
- * 50 NC
- * 51 NC
- * 52 NC
- * 53 NC
- * 54 NC
- * 55 NC
- * 56 NC
- * 57 NC
- * 58 DKDIRQ I
- * 59 NC
- * 60 NC
- * 61 NC
- * 62 NC
- * 63 NC
- * 64 COMLED O 0
- * 65 COMLED O 0
- * 66 COMLED O 0
- * 67 COMLED O 0
- * 68 COMLED O 0
- * 69 COMLED O 0
- * 70 COMLED O 0
- * 71 COMLED O 0
- * 72 NC
- * 73 NC
- * 74 NC
- * 75 NC
- * 76 NC
- * 77 NC
- * 78 CSIO O 1
- * 79 NC
- * 80 CSETH O 1
- *
- * NOTE: All NC's are defined to be outputs
- *
- */
-/* Pin direction control */
-/* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
-#define CONFIG_SYS_GPDR0_VAL 0xfff3bf02
-#define CONFIG_SYS_GPDR1_VAL 0xfbffbf83
-#define CONFIG_SYS_GPDR2_VAL 0x0001ffff
-/* Set and Clear registers */
-#define CONFIG_SYS_GPSR0_VAL 0x00400800
-#define CONFIG_SYS_GPSR1_VAL 0x00000480
-#define CONFIG_SYS_GPSR2_VAL 0x00014000
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x00000000
-#define CONFIG_SYS_GPCR2_VAL 0x00000000
-/* Edge detect registers (these are set by the kernel) */
-#define CONFIG_SYS_GRER0_VAL 0x00000000
-#define CONFIG_SYS_GRER1_VAL 0x00000000
-#define CONFIG_SYS_GRER2_VAL 0x00000000
-#define CONFIG_SYS_GFER0_VAL 0x00000000
-#define CONFIG_SYS_GFER1_VAL 0x00000000
-#define CONFIG_SYS_GFER2_VAL 0x00000000
-/* Alternate function registers */
-#define CONFIG_SYS_GAFR0_L_VAL 0x00000000
-#define CONFIG_SYS_GAFR0_U_VAL 0x00000010
-#define CONFIG_SYS_GAFR1_L_VAL 0x900a9550
-#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
-#define CONFIG_SYS_GAFR2_L_VAL 0x20000000
-#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
-
-/*
- * Clocks, power control and interrupts
- */
-#define CONFIG_SYS_PSSR_VAL 0x00000020
-#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */
-#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */
-#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
-
-/* FIXME
- *
- * RTC settings
- * Watchdog
- *
- */
-
-/*
- * Memory settings
- *
- * FIXME Can ethernet be burst read and/or write?? This is set for lubbock
- * Verify timings on all
- */
-#define CONFIG_SYS_MSC0_VAL 0x000023FA /* flash bank (cs0) */
-/*#define CONFIG_SYS_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */
-#define CONFIG_SYS_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */
-#define CONFIG_SYS_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */
-#ifdef REDBOOT_WAY
-#define CONFIG_SYS_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
-#define CONFIG_SYS_MDMRS_VAL 0x00000000
-#define CONFIG_SYS_MDREFR_VAL 0x00018018
-#else
-#define CONFIG_SYS_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
-#define CONFIG_SYS_MDMRS_VAL 0x00000000
-#define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */
-#endif
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x00000000
-
-/*
- * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
- */
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00010504
-#define CONFIG_SYS_MCMEM1_VAL 0x00010504
-#define CONFIG_SYS_MCATT0_VAL 0x00010504
-#define CONFIG_SYS_MCATT1_VAL 0x00010504
-#define CONFIG_SYS_MCIO0_VAL 0x00004715
-#define CONFIG_SYS_MCIO1_VAL 0x00004715
-
-/* Board specific defines */
-
-/* LED defines */
-#define YELLOW 0x03
-#define RED 0x02
-#define GREEN 0x01
-#define OFF 0x00
-#define LED_IRDA0 0
-#define LED_IRDA1 2
-#define LED_IRDA2 4
-#define LED_IRDA3 6
-
-/* SuperIO defines */
-#define CRADLE_SIO_INDEX 0x2e
-#define CRADLE_SIO_DATA 0x2f
-
-/* IO defines */
-#define CRADLE_CPLD_PHYS 0x08000000
-#define CRADLE_SIO1_PHYS 0x08100000
-#define CRADLE_SIO2_PHYS 0x08200000
-#define CRADLE_SIO3_PHYS 0x08300000
-#define CRADLE_ETH_PHYS 0x10000000
-
-#ifndef __ASSEMBLY__
-
-/* global prototypes */
-void led_code(int code, int color);
-
-#endif
-
-#endif /* __CONFIG_H */
projects / kernel / u-boot.git / commitdiff