When processing __attribute__ ((target("arch=XXX"))), we should clear
the ISA bits in x_ix86_isa_flags first to avoid leaking ISA from
command line.
gcc/
PR target/67995
* config/i386/i386.c (ix86_valid_target_attribute_tree): If
arch= is set, clear all bits in x_ix86_isa_flags, except for
ISA_64BIT, ABI_64, ABI_X32, and CODE16.
gcc/testsuite/
PR target/67995
* gcc.target/i386/pr67995-1.c: New test.
* gcc.target/i386/pr67995-2.c: Likewise.
* gcc.target/i386/pr67995-3.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228967
138bc75d-0d04-0410-961f-
82ee72b054a4
+2015-10-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/67995
+ * config/i386/i386.c (ix86_valid_target_attribute_tree): If
+ arch= is set, clear all bits in x_ix86_isa_flags, except for
+ ISA_64BIT, ABI_64, ABI_X32, and CODE16.
+
2015-10-19 Joost VandeVondele <vondele@gnu.gcc.org>
PR middle-end/68002
/* If we are using the default tune= or arch=, undo the string assigned,
and use the default. */
if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
- opts->x_ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
+ {
+ opts->x_ix86_arch_string
+ = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
+
+ /* If arch= is set, clear all bits in x_ix86_isa_flags,
+ except for ISA_64BIT, ABI_64, ABI_X32, and CODE16. */
+ opts->x_ix86_isa_flags &= (OPTION_MASK_ISA_64BIT
+ | OPTION_MASK_ABI_64
+ | OPTION_MASK_ABI_X32
+ | OPTION_MASK_CODE16);
+
+ }
else if (!orig_arch_specified)
opts->x_ix86_arch_string = NULL;
+2015-10-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/67995
+ * gcc.target/i386/pr67995-1.c: New test.
+ * gcc.target/i386/pr67995-2.c: Likewise.
+ * gcc.target/i386/pr67995-3.c: Likewise.
+
2015-10-19 Joost VandeVondele <vondele@gnu.gcc.org>
PR middle-end/68002
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=haswell" } */
+
+unsigned int
+__attribute__ ((target("arch=core2")))
+__x86_rdrand(void)
+{
+ unsigned int retries = 100;
+ unsigned int val;
+
+ while (__builtin_ia32_rdrand32_step(&val) == 0) /* { dg-error "needs isa option" } */
+ if (--retries == 0)
+ return 0;
+
+ return val;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=core2" } */
+
+unsigned int
+__attribute__ ((target("arch=haswell")))
+__x86_rdrand(void)
+{
+ unsigned int retries = 100;
+ unsigned int val;
+
+ while (__builtin_ia32_rdrand32_step(&val) == 0)
+ if (--retries == 0)
+ return 0;
+
+ return val;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=core2" } */
+
+unsigned int
+__attribute__ ((target("rdrnd")))
+__x86_rdrand(void)
+{
+ unsigned int retries = 100;
+ unsigned int val;
+
+ while (__builtin_ia32_rdrand32_step(&val) == 0)
+ if (--retries == 0)
+ return 0;
+
+ return val;
+}