enable cache ctrl in circle target

Change-Id: I6b292830548875843212b329a437e2e88b5d124f

diff --git a/packaging/libtbm-exynos.spec b/packaging/libtbm-exynos.spec
index c8903b8..49ed653 100644 (file)
--- a/packaging/libtbm-exynos.spec
+++ b/packaging/libtbm-exynos.spec
@@ -23,9 +23,12 @@ descriptionion: Tizen Buffer manager backend module for exynos
 
 %build
 
-%reconfigure --prefix=%{_prefix} --libdir=%{_libdir}/bufmgr --disable-cachectrl \
+%reconfigure --prefix=%{_prefix} --libdir=%{_libdir}/bufmgr \
 %if "%_repository" == "target-circle"
              --enable-align-eight \
+            --enable-cachecrtl \
+%else
+            --disable-cachectrl \
 %endif
             CFLAGS="${CFLAGS} -Wall -Werror" LDFLAGS="${LDFLAGS} -Wl,--hash-style=both -Wl,--as-needed"
 

diff --git a/src/tbm_bufmgr_exynos.c b/src/tbm_bufmgr_exynos.c
index 630c719..6f81ac4 100644 (file)
--- a/src/tbm_bufmgr_exynos.c
+++ b/src/tbm_bufmgr_exynos.c
@@ -391,7 +391,7 @@ _exynos_cache_flush(tbm_bufmgr_exynos bufmgr_exynos, tbm_bo_exynos bo_exynos, in
        if (flags & TBM_EXYNOS_CACHE_ALL)
                cache_op.flags |= EXYNOS_DRM_ALL_CACHES_CORES;
 
-       ret = drmCommandWriteRead(fd, DRM_EXYNOS_GEM_CACHE_OP, &cache_op,
+       ret = drmCommandWriteRead(bufmgr_exynos->fd, DRM_EXYNOS_GEM_CACHE_OP, &cache_op,
                                  sizeof(cache_op));
        if (ret) {
                TBM_EXYNOS_LOG("error fail to flush the cache.\n");
@@ -538,7 +538,7 @@ static int
 _bufmgr_init_cache_state(tbm_bufmgr_exynos bufmgr_exynos)
 {
 #ifdef ENABLE_CACHECRTL
-       EXYNOS_RETURN_IF_FAIL(bufmgr_exynos != NULL);
+       EXYNOS_RETURN_VAL_IF_FAIL(bufmgr_exynos != NULL, 0);
 
        if (bufmgr_exynos->use_dma_fence)
                return 1;

diff --git a/src/tbm_bufmgr_tgl.h b/src/tbm_bufmgr_tgl.h
index fee35d5..f1baa14 100644 (file)
--- a/src/tbm_bufmgr_tgl.h
+++ b/src/tbm_bufmgr_tgl.h
@@ -69,4 +69,57 @@ typedef enum {
 #define TGL_IOC_SET_DATA                       _IOW(TGL_IOC_BASE, _TGL_SET_DATA, struct tgl_user_data *)
 #define TGL_IOC_GET_DATA                       _IOW(TGL_IOC_BASE, _TGL_GET_DATA, struct tgl_user_data *)
 
+#ifdef ENABLE_CACHECRTL
+
+/* indicate cache units. */
+enum e_drm_exynos_gem_cache_sel {
+       EXYNOS_DRM_L1_CACHE             = 1 << 0,
+       EXYNOS_DRM_L2_CACHE             = 1 << 1,
+       EXYNOS_DRM_ALL_CORES            = 1 << 2,
+       EXYNOS_DRM_ALL_CACHES           = EXYNOS_DRM_L1_CACHE |
+                                               EXYNOS_DRM_L2_CACHE,
+       EXYNOS_DRM_ALL_CACHES_CORES     = EXYNOS_DRM_L1_CACHE |
+                                               EXYNOS_DRM_L2_CACHE |
+                                               EXYNOS_DRM_ALL_CORES,
+       EXYNOS_DRM_CACHE_SEL_MASK       = EXYNOS_DRM_ALL_CACHES_CORES
+};
+
+/* indicate cache operation types. */
+enum e_drm_exynos_gem_cache_op {
+       EXYNOS_DRM_CACHE_INV_ALL        = 1 << 3,
+       EXYNOS_DRM_CACHE_INV_RANGE      = 1 << 4,
+       EXYNOS_DRM_CACHE_CLN_ALL        = 1 << 5,
+       EXYNOS_DRM_CACHE_CLN_RANGE      = 1 << 6,
+       EXYNOS_DRM_CACHE_FSH_ALL        = EXYNOS_DRM_CACHE_INV_ALL |
+                                               EXYNOS_DRM_CACHE_CLN_ALL,
+       EXYNOS_DRM_CACHE_FSH_RANGE      = EXYNOS_DRM_CACHE_INV_RANGE |
+                                               EXYNOS_DRM_CACHE_CLN_RANGE,
+       EXYNOS_DRM_CACHE_OP_MASK        = EXYNOS_DRM_CACHE_FSH_ALL |
+                                               EXYNOS_DRM_CACHE_FSH_RANGE
+};
+
+/**
+ * A structure for cache operation.
+ *
+ * @usr_addr: user space address.
+ *     P.S. it SHOULD BE user space.
+ * @size: buffer size for cache operation.
+ * @flags: select cache unit and cache operation.
+ * @gem_handle: a handle to a gem object.
+ *     this gem handle is needed for cache range operation to L2 cache.
+ */
+struct drm_exynos_gem_cache_op {
+       uint64_t usr_addr;
+       unsigned int size;
+       unsigned int flags;
+       unsigned int gem_handle;
+};
+
+#define DRM_EXYNOS_GEM_CACHE_OP                0x12
+
+#define DRM_IOCTL_EXYNOS_GEM_CACHE_OP  DRM_IOWR(DRM_COMMAND_BASE + \
+               DRM_EXYNOS_GEM_CACHE_OP, struct drm_exynos_gem_cache_op)
+
+#endif
+
 #endif                                                 /* __TBM_BUFMGR_TGL_H__ */