+2009-05-29 Jakub Jelinek <jakub@redhat.com>
+
+ * config/i386/i386.md (prefix_data16, prefix_rep): Set to 0 for
+ TYPE_SSE{MULADD,4ARG,IADD1,CVT1} by default.
+ (prefix_rex): For UNIT_MMX don't imply the prefix by default
+ if MODE_DI.
+ (prefix_extra): Default to 2 for TYPE_SSE{MULADD,4ARG} and
+ to 1 for TYPE_SSE{IADD1,CVT1}.
+ (prefix_vex_imm8): Removed.
+ (length_vex): Only pass 1 as second argument to
+ ix86_attr_length_vex_default if prefix_extra is 0.
+ (modrm): For TYPE_INCDEC only set to 0 if not TARGET_64BIT.
+ (length): For prefix vex computation use length_immediate
+ attribute instead of prefix_vex_imm8.
+ (cmpqi_ext_3_insn, cmpqi_ext_3_insn_rex64,
+ addqi_ext_1, addqi_ext_1_rex64, *testqi_ext_0, andqi_ext_0,
+ *andqi_ext_0_cc, *iorqi_ext_0, *xorqi_ext_0, *xorqi_cc_ext_1,
+ *xorqi_cc_ext_1_rex64): Override modrm attribute to 1.
+ (extendsidi2_rex64, extendhidi2, extendqidi2, extendhisi2,
+ *extendhisi2_zext, extendqihi2, extendqisi2, *extendqisi2_zext): Emit
+ a space in between the operands.
+ (*anddi_1_rex64, *andsi_1): Likewise. Override prefix_rex to 1
+ if one operand is 0xff and the other one si, di, bp or sp.
+ (*andhi_1): Override prefix_rex to 1 if one operand is 0xff and the
+ other one si, di, bp or sp.
+ (*btsq, *btrq, *btcq, *btdi_rex64, *btsi): Add mode attribute.
+ (*ffssi_1, *ffsdi_1, ctzsi2, ctzdi2): Add
+ type and mode attributes.
+ (*bsr, *bsr_rex64, *bsrhi): Add type attribute.
+ (*cmpfp_i_mixed, *cmpfp_iu_mixed): For TYPE_SSECOMI, clear
+ prefix_rep attribute and set prefix_data16 attribute iff MODE_DF.
+ (*cmpfp_i_sse, *cmpfp_iu_sse): Clear prefix_rep attribute and set
+ prefix_data16 attribute iff MODE_DF.
+ (*movsi_1): For TYPE_SSEMOV MODE_SI set prefix_data16 attribute.
+ (fix_trunc<mode>di_sse): Set prefix_rex attribute.
+ (*adddi_4_rex64, *addsi_4): Use const128_operand instead of
+ constm128_operand in length_immediate computation.
+ (*addhi_4): Likewise. Fix mode attribute to MODE_HI.
+ (anddi_1_rex64): Use movzbl/movzwl instead of movzbq/movzwq.
+ (*avx_ashlti3, sse2_ashlti3, *avx_lshrti3, sse2_lshrti3): Set
+ length_immediate attribute to 1.
+ (x86_fnstsw_1, x86_fnstcw_1, x86_fldcw_1): Fix length attribute.
+ (*movdi_1_rex64): Override prefix_rex or prefix_data16 attributes
+ for certain alternatives.
+ (*movdf_nointeger, *movdf_integer_rex64, *movdf_integer): Override
+ prefix_data16 attribute if MODE_V1DF.
+ (*avx_setcc<mode>, *sse_setcc<mode>, *sse5_setcc<mode>): Set
+ length_immediate to 1.
+ (set_got_rex64, set_rip_rex64): Remove length attribute, set
+ length_address to 4, set mode attribute to MODE_DI.
+ (set_got_offset_rex64): Likewise. Set length_immediate to 0.
+ (fxam<mode>2_i387): Set length attribute to 4.
+ (*prefetch_sse, *prefetch_sse_rex, *prefetch_3dnow,
+ *prefetch_3dnow_rex): Override length_address attribute.
+ (sse4_2_crc32<mode>): Override prefix_data16 and prefix_rex
+ attributes.
+ * config/i386/predicates.md (ext_QIreg_nomode_operand): New predicate.
+ (constm128_operand): Removed.
+ * config/i386/i386.c (memory_address_length): For
+ disp && !index && !base in 64-bit mode account for SIB byte if
+ print_operand_address can't optimize disp32 into disp32(%rip)
+ and UNSPEC doesn't imply (%rip) addressing. Add 1 to length
+ for fs: or gs: segment.
+ (ix86_attr_length_immediate_default): When checking if shortform
+ is possible, truncate immediate to the length of the non-shortened
+ immediate.
+ (ix86_attr_length_address_default): Ignore MEM_P operands
+ with X constraint.
+ (ix86_attr_length_vex_default): Only check for DImode on
+ GENERAL_REG_P operands.
+ * config/i386/sse.md (<sse>_comi, <sse>_ucomi): Clear
+ prefix_rep attribute, set prefix_data16 attribute iff MODE_DF.
+ (sse_cvttps2pi): Clear prefix_rep attribute.
+ (sse2_cvttps2dq, *sse2_cvtpd2dq, sse2_cvtps2pd): Clear prefix_data16
+ attribute.
+ (*sse2_cvttpd2dq): Don't clear prefix_rep attribute.
+ (*avx_ashr<mode>3, ashr<mode>3, *avx_lshr<mode>3, lshr<mode>3,
+ *avx_ashl<mode>3, ashl<mode>3): Set length_immediate attribute to 1
+ iff operand 2 is const_int_operand.
+ (*vec_dupv4si, avx_shufpd256_1, *avx_shufpd_<mode>,
+ sse2_shufpd_<mode>): Set length_immediate attribute to 1.
+ (sse2_pshufd_1): Likewise. Set prefix attribute to maybe_vex
+ instead of vex.
+ (sse2_pshuflw_1, sse2_pshufhw_1): Set length_immediate to 1 and clear
+ prefix_data16.
+ (sse2_unpckhpd, sse2_unpcklpd, sse2_storehpd, *vec_concatv2df): Set
+ prefix_data16 attribute for movlpd and movhpd instructions.
+ (sse2_loadhpd, sse2_loadlpd, sse2_movsd): Likewise. Override
+ length_immediate for shufpd instruction.
+ (sse2_movntsi, sse3_lddqu): Clear prefix_data16 attribute.
+ (avx_cmpp<avxmodesuffixf2c><mode>3,
+ avx_cmps<ssemodesuffixf2c><mode>3, *avx_maskcmp<mode>3,
+ <sse>_maskcmp<mode>3, <sse>_vmmaskcmp<mode>3,
+ avx_shufps256_1, *avx_shufps_<mode>, sse_shufps_<mode>,
+ *vec_dupv4sf_avx, *vec_dupv4sf): Set
+ length_immediate attribute to 1.
+ (*avx_cvtsi2ssq, *avx_cvtsi2sdq): Set length_vex attribute to 4.
+ (sse_cvtsi2ssq, sse2_cvtsi2sdq): Set prefix_rex attribute to 1.
+ (sse2_cvtpi2pd, sse_loadlps, sse2_storelpd): Override
+ prefix_data16 attribute for the first alternative to 1.
+ (*avx_loadlps): Override length_immediate for the first alternative.
+ (*vec_concatv2sf_avx): Override length_immediate and prefix_extra
+ attributes for second alternative.
+ (*vec_concatv2sf_sse4_1): Override length_immediate and
+ prefix_data16 attributes for second alternative.
+ (*vec_setv4sf_avx, *avx_insertps, vec_extract_lo_<mode>,
+ vec_extract_hi_<mode>, vec_extract_lo_v16hi,
+ vec_extract_hi_v16hi, vec_extract_lo_v32qi,
+ vec_extract_hi_v32qi): Set prefix_extra and length_immediate to 1.
+ (*vec_setv4sf_sse4_1, sse4_1_insertps, *sse4_1_extractps): Set
+ prefix_data16 and length_immediate to 1.
+ (*avx_mulv2siv2di3, *avx_mulv4si3, sse4_2_gtv2di3): Set prefix_extra
+ to 1.
+ (*avx_<code><mode>3, *avx_eq<mode>3, *avx_gt<mode>3): Set
+ prefix_extra attribute for variants that don't have 0f prefix
+ alone.
+ (*avx_pinsr<ssevecsize>): Likewise. Set length_immediate to 1.
+ (*sse4_1_pinsrb, *sse2_pinsrw, *sse4_1_pinsrd, *sse4_1_pextrb,
+ *sse4_1_pextrb_memory, *sse2_pextrw, *sse4_1_pextrw_memory,
+ *sse4_1_pextrd): Set length_immediate to 1.
+ (*sse4_1_pinsrd): Likewise. Set prefix_extra to 1.
+ (*sse4_1_pinsrq, *sse4_1_pextrq): Set prefix_rex and length_immediate
+ to 1.
+ (*vec_extractv2di_1_rex64_avx, *vec_extractv2di_1_rex64,
+ *vec_extractv2di_1_avx, *vec_extractv2di_1_sse2): Override
+ length_immediate to 1 for second alternative.
+ (*vec_concatv2si_avx, *vec_concatv2di_rex64_avx): Override
+ prefix_extra and length_immediate attributes for the first
+ alternative.
+ (vec_concatv2si_sse4_1): Override length_immediate to 1 for the
+ first alternative.
+ (*vec_concatv2di_rex64_sse4_1): Likewise. Override prefix_rex
+ to 1 for the first and third alternative.
+ (*vec_concatv2di_rex64_sse): Override prefix_rex to 1 for the second
+ alternative.
+ (*sse2_maskmovdqu, *sse2_maskmovdqu_rex64): Override length_vex
+ attribute.
+ (*sse_sfence, sse2_mfence, sse2_lfence): Override length_address
+ attribute to 0.
+ (*avx_phaddwv8hi3, *avx_phadddv4si3, *avx_phaddswv8hi3,
+ *avx_phsubwv8hi3, *avx_phsubdv4si3, *avx_phsubswv8hi,
+ *avx_pmaddubsw128, *avx_pmulhrswv8hi3, *avx_pshufbv16qi3,
+ *avx_psign<mode>3): Set prefix_extra attribute to 1.
+ (ssse3_phaddwv4hi3, ssse3_phadddv2si3, ssse3_phaddswv4hi3,
+ ssse3_phsubwv4hi3, ssse3_phsubdv2si3, ssse3_phsubswv4hi3,
+ ssse3_pmaddubsw, *ssse3_pmulhrswv4hi, ssse3_pshufbv8qi3,
+ ssse3_psign<mode>3): Override prefix_rex attribute.
+ (*avx_palignrti): Override prefix_extra and length_immediate
+ to 1.
+ (ssse3_palignrti): Override length_immediate to 1.
+ (ssse3_palignrdi): Override length_immediate to 1, override
+ prefix_rex attribute.
+ (abs<mode>2): Override prefix_rep to 0, override prefix_rex
+ attribute.
+ (sse4a_extrqi): Override length_immediate to 2.
+ (sse4a_insertqi): Likewise. Override prefix_data16 to 0.
+ (sse4a_insertq): Override prefix_data16 to 0.
+ (avx_blendp<avxmodesuffixf2c><avxmodesuffix>,
+ avx_blendvp<avxmodesuffixf2c><avxmodesuffix>,
+ avx_dpp<avxmodesuffixf2c><avxmodesuffix>, *avx_mpsadbw,
+ *avx_pblendvb, *avx_pblendw, avx_roundp<avxmodesuffixf2c>256,
+ avx_rounds<avxmodesuffixf2c>256): Override prefix_extra
+ and length_immediate to 1.
+ (sse4_1_blendp<ssemodesuffixf2c>, sse4_1_dpp<ssemodesuffixf2c>,
+ sse4_2_pcmpestr, sse4_2_pcmpestri, sse4_2_pcmpestrm,
+ sse4_2_pcmpestr_cconly, sse4_2_pcmpistr, sse4_2_pcmpistri,
+ sse4_2_pcmpistrm, sse4_2_pcmpistr_cconly): Override prefix_data16
+ and length_immediate to 1.
+ (sse4_1_blendvp<ssemodesuffixf2c>): Override prefix_data16 to 1.
+ (sse4_1_mpsadbw, sse4_1_pblendw): Override length_immediate to 1.
+ (*avx_packusdw, avx_vtestp<avxmodesuffixf2c><avxmodesuffix>,
+ avx_ptest256): Override prefix_extra to 1.
+ (sse4_1_roundp<ssemodesuffixf2c>, sse4_1_rounds<ssemodesuffixf2c>):
+ Override prefix_data16 and length_immediate to 1.
+ (sse5_pperm_zero_v16qi_v8hi, sse5_pperm_sign_v16qi_v8hi,
+ sse5_pperm_zero_v8hi_v4si, sse5_pperm_sign_v8hi_v4si,
+ sse5_pperm_zero_v4si_v2di, sse5_pperm_sign_v4si_v2di,
+ sse5_vrotl<mode>3, sse5_ashl<mode>3, sse5_lshl<mode>3): Override
+ prefix_data16 to 0 and prefix_extra to 2.
+ (sse5_rotl<mode>3, sse5_rotr<mode>3): Override length_immediate to 1.
+ (sse5_frcz<mode>2, sse5_vmfrcz<mode>2): Don't override prefix_extra
+ attribute.
+ (*sse5_vmmaskcmp<mode>3, sse5_com_tf<mode>3,
+ sse5_maskcmp<mode>3, sse5_maskcmp<mode>3, sse5_maskcmp_uns<mode>3):
+ Override prefix_data16 and prefix_rep to 0, length_immediate to 1
+ and prefix_extra to 2.
+ (sse5_maskcmp_uns2<mode>3, sse5_pcom_tf<mode>3): Override
+ prefix_data16 to 0, length_immediate to 1 and prefix_extra to 2.
+ (*avx_aesenc, *avx_aesenclast, *avx_aesdec, *avx_aesdeclast,
+ avx_vpermilvar<mode>3,
+ avx_vbroadcasts<avxmodesuffixf2c><avxmodesuffix>,
+ avx_vbroadcastss256, avx_vbroadcastf128_p<avxmodesuffixf2c>256,
+ avx_maskloadp<avxmodesuffixf2c><avxmodesuffix>,
+ avx_maskstorep<avxmodesuffixf2c><avxmodesuffix>):
+ Override prefix_extra to 1.
+ (aeskeygenassist, pclmulqdq): Override length_immediate to 1.
+ (*vpclmulqdq, avx_vpermil<mode>, avx_vperm2f128<mode>3,
+ vec_set_lo_<mode>, vec_set_hi_<mode>, vec_set_lo_v16hi,
+ vec_set_hi_v16hi, vec_set_lo_v32qi, vec_set_hi_v32qi): Override
+ prefix_extra and length_immediate to 1.
+ (*avx_vzeroall, avx_vzeroupper, avx_vzeroupper_rex64): Override
+ modrm to 0.
+ (*vec_concat<mode>_avx): Override prefix_extra and length_immediate
+ to 1 for the first alternative.
+ * config/i386/mmx.md (*mov<mode>_internal_rex64): Override
+ prefix_rep, prefix_data16 and/or prefix_rex attributes in certain
+ cases.
+ (*mov<mode>_internal_avx, *movv2sf_internal_rex64,
+ *movv2sf_internal_avx, *movv2sf_internal): Override
+ prefix_rep attribute for certain alternatives.
+ (*mov<mode>_internal): Override prefix_rep or prefix_data16
+ attributes for certain alternatives.
+ (*movv2sf_internal_rex64_avx): Override prefix_rep and length_vex
+ attributes for certain alternatives.
+ (*mmx_addv2sf3, *mmx_subv2sf3, *mmx_mulv2sf3,
+ *mmx_<code>v2sf3_finite, *mmx_<code>v2sf3, mmx_rcpv2sf2,
+ mmx_rcpit1v2sf3, mmx_rcpit2v2sf3, mmx_rsqrtv2sf2, mmx_rsqit1v2sf3,
+ mmx_haddv2sf3, mmx_hsubv2sf3, mmx_addsubv2sf3,
+ *mmx_eqv2sf3, mmx_gtv2sf3, mmx_gev2sf3, mmx_pf2id, mmx_pf2iw,
+ mmx_pi2fw, mmx_floatv2si2, mmx_pswapdv2sf2, *mmx_pmulhrwv4hi3,
+ mmx_pswapdv2si2): Set prefix_extra attribute to 1.
+ (mmx_ashr<mode>3, mmx_lshr<mode>3, mmx_ashl<mode>3): Set
+ length_immediate to 1 if operand 2 is const_int_operand.
+ (*mmx_pinsrw, mmx_pextrw, mmx_pshufw_1, *vec_dupv4hi,
+ *vec_extractv2si_1): Set length_immediate
+ attribute to 1.
+ (*mmx_uavgv8qi3): Override prefix_extra attribute to 1 if
+ using old 3DNOW insn rather than SSE/3DNOW_A.
+ (mmx_emms, mmx_femms): Clear modrm attribute.
+
2009-05-29 Martin Jambor <mjambor@suse.cz>
* tree-sra.c: New implementation of SRA.
;; Set when length prefix is used.
(define_attr "prefix_data16" ""
- (if_then_else (ior (eq_attr "mode" "HI")
- (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI")))
- (const_int 1)
- (const_int 0)))
+ (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
+ (const_int 0)
+ (eq_attr "mode" "HI")
+ (const_int 1)
+ (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI"))
+ (const_int 1)
+ ]
+ (const_int 0)))
;; Set when string REP prefix is used.
(define_attr "prefix_rep" ""
- (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
- (const_int 1)
- (const_int 0)))
+ (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
+ (const_int 0)
+ (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
+ (const_int 1)
+ ]
+ (const_int 0)))
;; Set when 0f opcode prefix is used.
(define_attr "prefix_0f" ""
(cond [(ne (symbol_ref "!TARGET_64BIT") (const_int 0))
(const_int 0)
(and (eq_attr "mode" "DI")
- (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
+ (and (eq_attr "type" "!push,pop,call,callv,leave,ibr")
+ (eq_attr "unit" "!mmx")))
(const_int 1)
(and (eq_attr "mode" "QI")
(ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
]
(const_int 0)))
-;; There are also additional prefixes in SSSE3.
-(define_attr "prefix_extra" "" (const_int 0))
+;; There are also additional prefixes in 3DNOW, SSSE3 or SSE5.
+;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
+;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
+;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
+(define_attr "prefix_extra" ""
+ (cond [(eq_attr "type" "ssemuladd,sse4arg")
+ (const_int 2)
+ (eq_attr "type" "sseiadd1,ssecvt1")
+ (const_int 1)
+ ]
+ (const_int 0)))
;; Prefix used: original, VEX or maybe VEX.
(define_attr "prefix" "orig,vex,maybe_vex"
(const_string "vex")
(const_string "orig")))
-;; There is a 8bit immediate for VEX.
-(define_attr "prefix_vex_imm8" "" (const_int 0))
-
;; VEX W bit is used.
(define_attr "prefix_vex_w" "" (const_int 0))
;; The length of VEX prefix
+;; Only instructions with 0f prefix can have 2 byte VEX prefix,
+;; 0f38/0f3a prefixes can't. In i386.md 0f3[8a] is
+;; still prefix_0f 1, with prefix_extra 1.
(define_attr "length_vex" ""
- (if_then_else (eq_attr "prefix_0f" "1")
+ (if_then_else (and (eq_attr "prefix_0f" "1")
+ (eq_attr "prefix_extra" "0"))
(if_then_else (eq_attr "prefix_vex_w" "1")
(symbol_ref "ix86_attr_length_vex_default (insn, 1, 1)")
(symbol_ref "ix86_attr_length_vex_default (insn, 1, 0)"))
(eq_attr "unit" "i387")
(const_int 0)
(and (eq_attr "type" "incdec")
- (ior (match_operand:SI 1 "register_operand" "")
- (match_operand:HI 1 "register_operand" "")))
+ (and (eq (symbol_ref "TARGET_64BIT") (const_int 0))
+ (ior (match_operand:SI 1 "register_operand" "")
+ (match_operand:HI 1 "register_operand" ""))))
(const_int 0)
(and (eq_attr "type" "push")
(not (match_operand 1 "memory_operand" "")))
(and (eq_attr "prefix" "maybe_vex")
(ne (symbol_ref "TARGET_AVX") (const_int 0))))
(plus (attr "length_vex")
- (plus (attr "prefix_vex_imm8")
+ (plus (attr "length_immediate")
(plus (attr "modrm")
(attr "length_address"))))]
(plus (plus (attr "modrm")
"!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "cmpqi_ext_3_insn_rex64"
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*cmpqi_ext_4"
(unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
"TARGET_80387"
"fnstsw\t%0"
- [(set_attr "length" "2")
+ [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "SI")
(set_attr "unit" "i387")])
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
+ (set (attr "prefix_rep")
+ (if_then_else (eq_attr "type" "ssecomi")
+ (const_string "0")
+ (const_string "*")))
+ (set (attr "prefix_data16")
+ (cond [(eq_attr "type" "fcmp")
+ (const_string "*")
+ (eq_attr "mode" "DF")
+ (const_string "1")
+ ]
+ (const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
+ (set_attr "prefix_rep" "0")
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "DF")
+ (const_string "1")
+ (const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
+ (set (attr "prefix_rep")
+ (if_then_else (eq_attr "type" "ssecomi")
+ (const_string "0")
+ (const_string "*")))
+ (set (attr "prefix_data16")
+ (cond [(eq_attr "type" "fcmp")
+ (const_string "*")
+ (eq_attr "mode" "DF")
+ (const_string "1")
+ ]
+ (const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
+ (set_attr "prefix_rep" "0")
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "DF")
+ (const_string "1")
+ (const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
(if_then_else (eq_attr "alternative" "0,1,2,3,4,5")
(const_string "orig")
(const_string "maybe_vex")))
+ (set (attr "prefix_data16")
+ (if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "SI"))
+ (const_string "1")
+ (const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "2,3")
(const_string "DI")
(and (eq_attr "alternative" "2") (eq_attr "type" "imov"))
(const_string "8")
(const_string "*")))
+ (set_attr "prefix_rex" "*,*,*,*,*,*,*,1,*,1,*,*,*,*,*,*,*,*,*")
+ (set_attr "prefix_data16" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,1,*,*,*")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "11,12,13,14,15,16")
(const_string "maybe_vex")
(if_then_else (eq_attr "alternative" "0,1,2,3,4")
(const_string "orig")
(const_string "maybe_vex")))
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "V1DF")
+ (const_string "1")
+ (const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
(if_then_else (eq_attr "alternative" "0,1,2,3,4")
(const_string "orig")
(const_string "maybe_vex")))
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "V1DF")
+ (const_string "1")
+ (const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
}
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "V1DF")
+ (const_string "1")
+ (const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
"TARGET_64BIT"
"@
{cltq|cdqe}
- movs{lq|x}\t{%1,%0|%0, %1}"
+ movs{lq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")
(set_attr "prefix_0f" "0")
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
"TARGET_64BIT"
- "movs{wq|x}\t{%1,%0|%0, %1}"
+ "movs{wq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")])
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
"TARGET_64BIT"
- "movs{bq|x}\t{%1,%0|%0, %1}"
+ "movs{bq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")])
case 0:
return "{cwtl|cwde}";
default:
- return "movs{wl|x}\t{%1,%0|%0, %1}";
+ return "movs{wl|x}\t{%1, %0|%0, %1}";
}
}
[(set_attr "type" "imovx")
case 0:
return "{cwtl|cwde}";
default:
- return "movs{wl|x}\t{%1,%k0|%k0, %1}";
+ return "movs{wl|x}\t{%1, %k0|%k0, %1}";
}
}
[(set_attr "type" "imovx")
case 0:
return "{cbtw|cbw}";
default:
- return "movs{bw|x}\t{%1,%0|%0, %1}";
+ return "movs{bw|x}\t{%1, %0|%0, %1}";
}
}
[(set_attr "type" "imovx")
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
""
- "movs{bl|x}\t{%1,%0|%0, %1}"
+ "movs{bl|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
(zero_extend:DI
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
"TARGET_64BIT"
- "movs{bl|x}\t{%1,%k0|%k0, %1}"
+ "movs{bl|x}\t{%1, %k0|%k0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
\f
"%vcvtts<ssemodefsuffix>2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "maybe_vex")
+ (set_attr "prefix_rex" "1")
(set_attr "mode" "<MODE>")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")])
(unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))]
"TARGET_80387"
"fnstcw\t%0"
- [(set_attr "length" "2")
+ [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "HI")
(set_attr "unit" "i387")])
(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
"TARGET_80387"
"fldcw\t%0"
- [(set_attr "length" "2")
+ [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "HI")
(set_attr "unit" "i387")
(set_attr "athlon_decode" "vector")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "constm128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
(set_attr "mode" "DI")])
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "constm128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI")])
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "constm128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "SI")])
+ (set_attr "mode" "HI")])
(define_insn "*addhi_5"
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*addqi_ext_1_rex64"
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*addqi_ext_2"
[(set_attr "type" "test")
(set_attr "mode" "QI")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "pent_pair" "np")])
(define_insn "*testqi_ext_1"
operands[1] = gen_lowpart (mode, operands[1]);
if (mode == QImode)
- return "movz{bq|x}\t{%1,%0|%0, %1}";
+ return "movz{bl|x}\t{%1, %k0|%k0, %1}";
else
- return "movz{wq|x}\t{%1,%0|%0, %1}";
+ return "movz{wl|x}\t{%1, %k0|%k0, %1}";
}
default:
}
[(set_attr "type" "alu,alu,alu,imovx")
(set_attr "length_immediate" "*,*,*,0")
- (set_attr "mode" "SI,DI,DI,DI")])
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "type" "imovx")
+ (and (ne (symbol_ref "INTVAL (operands[2]) == 0xff") (const_int 0))
+ (match_operand 1 "ext_QIreg_nomode_operand" "")))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "SI,DI,DI,SI")])
(define_insn "*anddi_2"
[(set (reg FLAGS_REG)
operands[1] = gen_lowpart (mode, operands[1]);
if (mode == QImode)
- return "movz{bl|x}\t{%1,%0|%0, %1}";
+ return "movz{bl|x}\t{%1, %0|%0, %1}";
else
- return "movz{wl|x}\t{%1,%0|%0, %1}";
+ return "movz{wl|x}\t{%1, %0|%0, %1}";
}
default:
}
}
[(set_attr "type" "alu,alu,imovx")
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "type" "imovx")
+ (and (ne (symbol_ref "INTVAL (operands[2]) == 0xff") (const_int 0))
+ (match_operand 1 "ext_QIreg_nomode_operand" "")))
+ (const_string "1")
+ (const_string "*")))
(set_attr "length_immediate" "*,*,0")
(set_attr "mode" "SI")])
}
[(set_attr "type" "alu,alu,imovx")
(set_attr "length_immediate" "*,*,0")
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "type" "imovx")
+ (match_operand 1 "ext_QIreg_nomode_operand" ""))
+ (const_string "1")
+ (const_string "*")))
(set_attr "mode" "HI,HI,SI")])
(define_insn "*andhi_2"
"and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
;; Generated by peephole translating test to and. This shows up
"and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*andqi_ext_1"
"or{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*iorqi_ext_1"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*xorqi_ext_1"
"!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*xorqi_cc_ext_1_rex64"
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_expand "xorqi_cc_ext_1"
}
[(set_attr "type" "sseishft")
(set_attr "prefix" "vex")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_ashlti3"
}
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*ashlti3_1"
}
[(set_attr "type" "sseishft")
(set_attr "prefix" "vex")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_lshrti3"
}
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*lshrti3_1"
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
"bts{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "*btrq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
"btr{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "*btcq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
"btc{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
;; Allow Nocona to avoid these instructions if a register is available.
"TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
"bt{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "*btsi"
[(set (reg:CCC FLAGS_REG)
"TARGET_USE_BT || optimize_function_for_size_p (cfun)"
"bt{l}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "SI")])
\f
;; Store-flag instructions.
"vcmp%D1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecmp")
(set_attr "prefix" "vex")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
(define_insn "*sse_setcc<mode>"
"SSE_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
"cmp%D1s<ssemodefsuffix>\t{%3, %0|%0, %3}"
[(set_attr "type" "ssecmp")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
(define_insn "*sse5_setcc<mode>"
"TARGET_SSE5"
"com%Y1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse4arg")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
\f
"TARGET_64BIT"
"lea{q}\t{_GLOBAL_OFFSET_TABLE_(%%rip), %0|%0, _GLOBAL_OFFSET_TABLE_[rip]}"
[(set_attr "type" "lea")
- (set_attr "length" "6")])
+ (set_attr "length_address" "4")
+ (set_attr "mode" "DI")])
(define_insn "set_rip_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
"TARGET_64BIT"
"lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
[(set_attr "type" "lea")
- (set_attr "length" "6")])
+ (set_attr "length_address" "4")
+ (set_attr "mode" "DI")])
(define_insn "set_got_offset_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
"TARGET_64BIT"
"movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
[(set_attr "type" "imov")
- (set_attr "length" "11")])
+ (set_attr "length_immediate" "0")
+ (set_attr "length_address" "8")
+ (set_attr "mode" "DI")])
(define_expand "epilogue"
[(const_int 0)]
(ctz:SI (match_dup 1)))]
""
"bsf{l}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "SI")])
(define_expand "ffsdi2"
[(set (match_dup 2) (const_int -1))
(ctz:DI (match_dup 1)))]
"TARGET_64BIT"
"bsf{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "ctzsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(clobber (reg:CC FLAGS_REG))]
""
"bsf{l}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "SI")])
(define_insn "ctzdi2"
[(set (match_operand:DI 0 "register_operand" "=r")
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"bsf{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_expand "clzsi2"
[(parallel
(clobber (reg:CC FLAGS_REG))]
""
"bsr{l}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
(set_attr "mode" "SI")])
(define_insn "popcount<mode>2"
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"bsr{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
(set_attr "mode" "DI")])
(define_expand "clzhi2"
(clobber (reg:CC FLAGS_REG))]
""
"bsr{w}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
(set_attr "mode" "HI")])
(define_expand "paritydi2"
"TARGET_USE_FANCY_MATH_387"
"fxam\n\tfnstsw\t%0"
[(set_attr "type" "multi")
+ (set_attr "length" "4")
(set_attr "unit" "i387")
(set_attr "mode" "<MODE>")])
}
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "prefetch")
+ (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_insn "*prefetch_sse_rex"
}
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "prefetch")
+ (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_insn "*prefetch_3dnow"
return "prefetchw\t%a0";
}
[(set_attr "type" "mmx")
+ (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_insn "*prefetch_3dnow_rex"
return "prefetchw\t%a0";
}
[(set_attr "type" "mmx")
+ (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_expand "stack_protect_set"
[(set_attr "type" "sselog1")
(set_attr "prefix_rep" "1")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_data16")
+ (if_then_else (match_operand:HI 2 "" "")
+ (const_string "1")
+ (const_string "*")))
+ (set (attr "prefix_rex")
+ (if_then_else (match_operand:QI 2 "ext_QIreg_operand" "")
+ (const_string "1")
+ (const_string "*")))
(set_attr "mode" "SI")])
(define_insn "sse4_2_crc32di"
;; GCC machine description for MMX and 3dNOW! instructions
-;; Copyright (C) 2005, 2007, 2008
+;; Copyright (C) 2005, 2007, 2008, 2009
;; Free Software Foundation, Inc.
;;
;; This file is part of GCC.
%vmovq\t{%1, %0|%0, %1}"
[(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,ssemov")
(set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*")
+ (set_attr "prefix_rep" "*,*,*,*,*,1,1,*,1,*,*,*")
+ (set_attr "prefix_data16" "*,*,*,*,*,*,*,*,*,1,1,1")
+ (set (attr "prefix_rex")
+ (if_then_else (eq_attr "alternative" "8,9")
+ (symbol_ref "x86_extended_reg_mentioned_p (insn)")
+ (const_string "*")))
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "7,8,9,10,11")
(const_string "maybe_vex")
#"
[(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,*,*")
(set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*")
+ (set_attr "prefix_rep" "*,*,*,1,1,*,*,*,*,*")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "5,6,7")
(const_string "vex")
#"
[(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov,*,*")
(set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*,*,*,*")
+ (set_attr "prefix_rep" "*,*,*,1,1,*,1,*,*,*,*,*,*,*")
+ (set_attr "prefix_data16" "*,*,*,*,*,*,*,1,*,*,*,*,*,*")
(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
(define_expand "movv2sf"
vmovq\t{%1, %0|%0, %1}"
[(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,sselog1,ssemov,ssemov,ssemov,ssemov")
(set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*,*")
+ (set_attr "prefix_rep" "*,*,*,*,*,1,1,*,*,*,*,*,*")
+ (set_attr "length_vex" "*,*,*,*,*,*,*,*,*,*,*,4,4")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "7,8,9,10,11,12")
(const_string "vex")
movd\t{%1, %0|%0, %1}"
[(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,sselog1,ssemov,ssemov,ssemov,ssemov")
(set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*,*")
+ (set_attr "prefix_rep" "*,*,*,*,*,1,1,*,*,*,*,*,*")
(set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
(define_insn "*movv2sf_internal_avx"
#"
[(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,*,*")
(set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*")
+ (set_attr "prefix_rep" "*,*,*,1,1,*,*,*,*,*,*")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "5,6,7,8")
(const_string "vex")
#"
[(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,*,*")
(set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*")
+ (set_attr "prefix_rep" "*,*,*,1,1,*,*,*,*,*,*")
(set_attr "mode" "DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
;; %%% This multiword shite has got to go.
"TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
"pfadd\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_expand "mmx_subv2sf3"
pfsub\t{%2, %0|%0, %2}
pfsubr\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_expand "mmx_mulv2sf3"
"TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
"pfmul\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxmul")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
&& ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
"pf<maxminfprefix>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "*mmx_<code>v2sf3"
"TARGET_3DNOW"
"pf<maxminfprefix>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_rcpv2sf2"
"TARGET_3DNOW"
"pfrcp\t{%1, %0|%0, %1}"
[(set_attr "type" "mmx")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_rcpit1v2sf3"
"TARGET_3DNOW"
"pfrcpit1\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_rcpit2v2sf3"
"TARGET_3DNOW"
"pfrcpit2\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_rsqrtv2sf2"
"TARGET_3DNOW"
"pfrsqrt\t{%1, %0|%0, %1}"
[(set_attr "type" "mmx")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_rsqit1v2sf3"
"TARGET_3DNOW"
"pfrsqit1\t{%2, %0|%0, %2}"
[(set_attr "type" "mmx")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_haddv2sf3"
"TARGET_3DNOW"
"pfacc\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_hsubv2sf3"
"TARGET_3DNOW_A"
"pfnacc\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_addsubv2sf3"
"TARGET_3DNOW_A"
"pfpnacc\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
"TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
"pfcmpeq\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxcmp")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_gtv2sf3"
"TARGET_3DNOW"
"pfcmpgt\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxcmp")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_gev2sf3"
"TARGET_3DNOW"
"pfcmpge\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxcmp")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
"TARGET_3DNOW"
"pf2id\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxcvt")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_pf2iw"
"TARGET_3DNOW_A"
"pf2iw\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxcvt")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_pi2fw"
"TARGET_3DNOW_A"
"pi2fw\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxcvt")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "mmx_floatv2si2"
"TARGET_3DNOW"
"pi2fd\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxcvt")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
"TARGET_3DNOW_A"
"pswapd\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxcvt")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
(define_insn "*vec_dupv2sf"
"TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
"pmulhrw\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxmul")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_expand "sse2_umulv1siv1di3"
"TARGET_MMX"
"psra<mmxvecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
+ (set (attr "length_immediate")
+ (if_then_else (match_operand 2 "const_int_operand" "")
+ (const_string "1")
+ (const_string "0")))
(set_attr "mode" "DI")])
(define_insn "mmx_lshr<mode>3"
"TARGET_MMX"
"psrl<mmxvecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
+ (set (attr "length_immediate")
+ (if_then_else (match_operand 2 "const_int_operand" "")
+ (const_string "1")
+ (const_string "0")))
(set_attr "mode" "DI")])
(define_insn "mmx_ashl<mode>3"
"TARGET_MMX"
"psll<mmxvecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxshft")
+ (set (attr "length_immediate")
+ (if_then_else (match_operand 2 "const_int_operand" "")
+ (const_string "1")
+ (const_string "0")))
(set_attr "mode" "DI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
}
[(set_attr "type" "mmxcvt")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "DI")])
(define_insn "mmx_pextrw"
"TARGET_SSE || TARGET_3DNOW_A"
"pextrw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "mmxcvt")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "DI")])
(define_expand "mmx_pshufw"
return "pshufw\t{%2, %1, %0|%0, %1, %2}";
}
[(set_attr "type" "mmxcvt")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "DI")])
(define_insn "mmx_pswapdv2si2"
"TARGET_3DNOW_A"
"pswapd\t{%1, %0|%0, %1}"
[(set_attr "type" "mmxcvt")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
(define_insn "*vec_dupv4hi"
"TARGET_SSE || TARGET_3DNOW_A"
"pshufw\t{$0, %0, %0|%0, %0, 0}"
[(set_attr "type" "mmxcvt")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "DI")])
(define_insn "*vec_dupv2si"
#
#"
[(set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,mmxmov,ssemov,imov")
+ (set_attr "length_immediate" "*,*,1,*,*,*,*")
(set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")])
(define_split
return "pavgusb\t{%2, %0|%0, %2}";
}
[(set_attr "type" "mmxshft")
+ (set (attr "prefix_extra")
+ (if_then_else
+ (eq (symbol_ref "(TARGET_SSE || TARGET_3DNOW_A)") (const_int 0))
+ (const_string "1")
+ (const_string "*")))
(set_attr "mode" "DI")])
(define_expand "mmx_uavgv4hi3"
"TARGET_MMX"
"emms"
[(set_attr "type" "mmx")
+ (set_attr "modrm" "0")
(set_attr "memory" "unknown")])
(define_insn "mmx_femms"
"TARGET_3DNOW"
"femms"
[(set_attr "type" "mmx")
+ (set_attr "modrm" "0")
(set_attr "memory" "none")])
"TARGET_SSE2"
"movnti\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "prefix_data16" "0")
(set_attr "mode" "V2DF")])
(define_insn "avx_lddqu<avxmodesuffix>"
"lddqu\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
(set_attr "movu" "1")
+ (set_attr "prefix_data16" "0")
(set_attr "prefix_rep" "1")
(set_attr "mode" "TI")])
"TARGET_AVX"
"vcmpp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssecmp")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
"TARGET_AVX"
"vcmps<ssemodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssecmp")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<ssescalarmode>")])
"vcmp%D3p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecmp")
(set_attr "prefix" "vex")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<avxvecmode>")])
(define_insn "<sse>_maskcmp<mode>3"
&& !TARGET_SSE5"
"cmp%D3<ssemodesuffixf4>\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecmp")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
(define_insn "<sse>_vmmaskcmp<mode>3"
"SSE_VEC_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
"cmp%D3s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecmp")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<ssescalarmode>")])
(define_insn "<sse>_comi"
"%vcomis<ssemodefsuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecomi")
(set_attr "prefix" "maybe_vex")
+ (set_attr "prefix_rep" "0")
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "DF")
+ (const_string "1")
+ (const_string "0")))
(set_attr "mode" "<MODE>")])
(define_insn "<sse>_ucomi"
"%vucomis<ssemodefsuffix>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecomi")
(set_attr "prefix" "maybe_vex")
+ (set_attr "prefix_rep" "0")
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "DF")
+ (const_string "1")
+ (const_string "0")))
(set_attr "mode" "<MODE>")])
(define_expand "vcond<mode>"
"cvttps2pi\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "unit" "mmx")
+ (set_attr "prefix_rep" "0")
(set_attr "mode" "SF")])
(define_insn "*avx_cvtsi2ss"
"TARGET_AVX && TARGET_64BIT"
"vcvtsi2ssq\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseicvt")
+ (set_attr "length_vex" "4")
(set_attr "prefix" "vex")
(set_attr "mode" "SF")])
"TARGET_SSE && TARGET_64BIT"
"cvtsi2ssq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseicvt")
+ (set_attr "prefix_rex" "1")
(set_attr "athlon_decode" "vector,double")
(set_attr "amdfam10_decode" "vector,double")
(set_attr "mode" "SF")])
"cvttps2dq\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix_rep" "1")
+ (set_attr "prefix_data16" "0")
(set_attr "mode" "TI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
"cvtpi2pd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "unit" "mmx,*")
+ (set_attr "prefix_data16" "1,*")
(set_attr "mode" "V2DF")])
(define_insn "sse2_cvtpd2pi"
"TARGET_AVX && TARGET_64BIT"
"vcvtsi2sdq\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseicvt")
+ (set_attr "length_vex" "4")
(set_attr "prefix" "vex")
(set_attr "mode" "DF")])
"TARGET_SSE2 && TARGET_64BIT"
"cvtsi2sdq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseicvt")
+ (set_attr "prefix_rex" "1")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "double,direct")
(set_attr "amdfam10_decode" "vector,double")])
: \"cvtpd2dq\t{%1, %0|%0, %1}\";"
[(set_attr "type" "ssecvt")
(set_attr "prefix_rep" "1")
+ (set_attr "prefix_data16" "0")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")
(set_attr "amdfam10_decode" "double")])
"* return TARGET_AVX ? \"vcvttpd2dq{x}\t{%1, %0|%0, %1}\"
: \"cvttpd2dq\t{%1, %0|%0, %1}\";"
[(set_attr "type" "ssecvt")
- (set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")
(set_attr "amdfam10_decode" "double")])
[(set_attr "type" "ssecvt")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V2DF")
+ (set_attr "prefix_data16" "0")
(set_attr "amdfam10_decode" "direct")])
(define_expand "vec_unpacks_hi_v4sf"
return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V4SF")])
return "shufps\t{%3, %2, %0|%0, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "V4SF")])
(define_insn "sse_storehps"
vmovlps\t{%2, %1, %0|%0, %1, %2}
vmovlps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog,ssemov,ssemov")
+ (set_attr "length_immediate" "1,*,*")
(set_attr "prefix" "vex")
(set_attr "mode" "V4SF,V2SF,V2SF")])
movlps\t{%2, %0|%0, %2}
movlps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog,ssemov,ssemov")
+ (set_attr "length_immediate" "1,*,*")
(set_attr "mode" "V4SF,V2SF,V2SF")])
(define_insn "*avx_movss"
"TARGET_AVX"
"vshufps\t{$0, %1, %1, %0|%0, %1, %1, 0}"
[(set_attr "type" "sselog1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V4SF")])
"TARGET_SSE"
"shufps\t{$0, %0, %0|%0, %0, 0}"
[(set_attr "type" "sselog1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "V4SF")])
(define_insn "*vec_concatv2sf_avx"
punpckldq\t{%2, %0|%0, %2}
movd\t{%1, %0|%0, %1}"
[(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
+ (set_attr "length_immediate" "*,1,*,*,*")
+ (set_attr "prefix_extra" "*,1,*,*,*")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "3,4")
(const_string "orig")
punpckldq\t{%2, %0|%0, %2}
movd\t{%1, %0|%0, %1}"
[(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
+ (set_attr "prefix_data16" "*,1,*,*,*")
(set_attr "prefix_extra" "*,1,*,*,*")
+ (set_attr "length_immediate" "*,1,*,*,*")
(set_attr "mode" "V4SF,V4SF,SF,DI,DI")])
;; ??? In theory we can match memory for the MMX alternative, but allowing
return "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V4SF")])
return "insertps\t{%3, %2, %0|%0, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "V4SF")])
(define_insn "*avx_insertps"
"vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "V4SF")])
(define_insn "sse4_1_insertps"
"TARGET_SSE4_1"
"insertps\t{%3, %2, %0|%0, %2, %3}";
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "V4SF")])
(define_split
"TARGET_AVX"
"vextractf128\t{$0x0, %1, %0|%0, %1, 0x0}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,store")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,store")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,store")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,store")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,store")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,store")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,store")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,store")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_SSE4_1"
"%vextractps\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V4SF")])
movlpd\t{%H1, %0|%0, %H1}
movhpd\t{%1, %0|%0, %1}"
[(set_attr "type" "sselog,ssemov,ssemov")
+ (set_attr "prefix_data16" "*,1,1")
(set_attr "mode" "V2DF,V1DF,V1DF")])
(define_insn "avx_movddup256"
movhpd\t{%2, %0|%0, %2}
movlpd\t{%2, %H0|%H0, %2}"
[(set_attr "type" "sselog,ssemov,ssemov")
+ (set_attr "prefix_data16" "*,1,1")
(set_attr "mode" "V2DF,V1DF,V1DF")])
(define_expand "avx_shufpd256"
return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V4DF")])
return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V2DF")])
return "shufpd\t{%3, %2, %0|%0, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "V2DF")])
;; Avoid combining registers from different units in a single alternative,
#
#"
[(set_attr "type" "ssemov,sselog1,ssemov,fmov,imov")
+ (set_attr "prefix_data16" "1,*,*,*,*")
(set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
(define_split
#
#"
[(set_attr "type" "ssemov,ssemov,ssemov,fmov,imov")
+ (set_attr "prefix_data16" "1,*,*,*,*")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V1DF,DF,DF,DF,DF")])
#
#"
[(set_attr "type" "ssemov,sselog,sselog,ssemov,fmov,imov")
+ (set_attr "prefix_data16" "1,*,*,*,*,*")
+ (set_attr "length_immediate" "*,*,1,*,*,*")
(set_attr "mode" "V1DF,V2DF,V2DF,DF,DF,DF")])
(define_split
#
#"
[(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov,fmov,imov")
+ (set_attr "prefix_data16" "*,1,*,*,1,*,*,*")
+ (set_attr "length_immediate" "*,*,*,1,*,*,*,*")
(set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,DF,DF,DF")])
(define_split
movhps\t{%H1, %0|%0, %H1}
movhps\t{%1, %H0|%H0, %1}"
[(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
+ (set_attr "prefix_data16" "*,1,1,*,*,*")
+ (set_attr "length_immediate" "*,*,*,1,*,*")
(set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,V1DF")])
(define_insn "*vec_dupv2df_sse3"
movlhps\t{%2, %0|%0, %2}
movhps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog,ssemov,ssemov,ssemov,ssemov")
+ (set_attr "prefix_data16" "*,1,*,*,*")
(set_attr "mode" "V2DF,V1DF,DF,V4SF,V2SF")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
"TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
"vpmuldq\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseimul")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
"vpmulld\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseimul")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"vpsra<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
(set_attr "prefix" "vex")
+ (set (attr "length_immediate")
+ (if_then_else (match_operand 2 "const_int_operand" "")
+ (const_string "1")
+ (const_string "0")))
(set_attr "mode" "TI")])
(define_insn "ashr<mode>3"
"psra<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
+ (set (attr "length_immediate")
+ (if_then_else (match_operand 2 "const_int_operand" "")
+ (const_string "1")
+ (const_string "0")))
(set_attr "mode" "TI")])
(define_insn "*avx_lshr<mode>3"
"vpsrl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
(set_attr "prefix" "vex")
+ (set (attr "length_immediate")
+ (if_then_else (match_operand 2 "const_int_operand" "")
+ (const_string "1")
+ (const_string "0")))
(set_attr "mode" "TI")])
(define_insn "lshr<mode>3"
"psrl<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
+ (set (attr "length_immediate")
+ (if_then_else (match_operand 2 "const_int_operand" "")
+ (const_string "1")
+ (const_string "0")))
(set_attr "mode" "TI")])
(define_insn "*avx_ashl<mode>3"
"vpsll<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
(set_attr "prefix" "vex")
+ (set (attr "length_immediate")
+ (if_then_else (match_operand 2 "const_int_operand" "")
+ (const_string "1")
+ (const_string "0")))
(set_attr "mode" "TI")])
(define_insn "ashl<mode>3"
"psll<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
+ (set (attr "length_immediate")
+ (if_then_else (match_operand 2 "const_int_operand" "")
+ (const_string "1")
+ (const_string "0")))
(set_attr "mode" "TI")])
(define_expand "vec_shl_<mode>"
"TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"vp<maxminiprefix><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set (attr "prefix_extra")
+ (if_then_else
+ (ne (symbol_ref "<MODE>mode != ((<CODE> == SMAX || <CODE> == SMIN) ? V8HImode : V16QImode)")
+ (const_int 0))
+ (const_string "1")
+ (const_string "0")))
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"TARGET_AVX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
"vpcmpeq<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecmp")
+ (set (attr "prefix_extra")
+ (if_then_else (match_operand:V2DI 0 "" "")
+ (const_string "1")
+ (const_string "*")))
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"TARGET_AVX"
"vpcmpgt<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecmp")
+ (set (attr "prefix_extra")
+ (if_then_else (match_operand:V2DI 0 "" "")
+ (const_string "1")
+ (const_string "*")))
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"TARGET_SSE4_2"
"pcmpgtq\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecmp")
+ (set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
(define_expand "vcond<mode>"
return "vpinsr<ssevecsize>\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
}
[(set_attr "type" "sselog")
+ (set (attr "prefix_extra")
+ (if_then_else (match_operand:V8HI 0 "register_operand" "")
+ (const_string "0")
+ (const_string "1")))
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
}
[(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*sse2_pinsrw"
}
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
;; It must come before sse2_loadld since it is preferred.
}
[(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*avx_pinsrq"
return "vpinsrq\t{%3, %2, %1, %0|%0, %1, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
return "pinsrq\t{%3, %2, %0|%0, %2, %3}";
}
[(set_attr "type" "sselog")
+ (set_attr "prefix_rex" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*sse4_1_pextrb"
"%vpextrb\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
"%vpextrb\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
"%vpextrw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
"%vpextrw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
"%vpextrd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
"TARGET_SSE4_1 && TARGET_64BIT"
"%vpextrq\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_rex" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
}
[(set_attr "type" "sselog1")
(set_attr "prefix_data16" "1")
- (set_attr "prefix" "vex")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_expand "sse2_pshuflw"
return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
}
[(set_attr "type" "sselog")
+ (set_attr "prefix_data16" "0")
(set_attr "prefix_rep" "1")
(set_attr "prefix" "maybe_vex")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_expand "sse2_pshufhw"
}
[(set_attr "type" "sselog")
(set_attr "prefix_rep" "1")
+ (set_attr "prefix_data16" "0")
(set_attr "prefix" "maybe_vex")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_expand "sse2_loadd"
vmovq\t{%H1, %0|%0, %H1}
vmov{q}\t{%H1, %0|%0, %H1}"
[(set_attr "type" "ssemov,sseishft,ssemov,imov")
+ (set_attr "length_immediate" "*,1,*,*")
(set_attr "memory" "*,none,*,*")
(set_attr "prefix" "vex")
(set_attr "mode" "V2SF,TI,TI,DI")])
movq\t{%H1, %0|%0, %H1}
mov{q}\t{%H1, %0|%0, %H1}"
[(set_attr "type" "ssemov,sseishft,ssemov,imov")
+ (set_attr "length_immediate" "*,1,*,*")
(set_attr "atom_unit" "*,sishuf,*,*")
(set_attr "memory" "*,none,*,*")
(set_attr "mode" "V2SF,TI,TI,DI")])
vpsrldq\t{$8, %1, %0|%0, %1, 8}
vmovq\t{%H1, %0|%0, %H1}"
[(set_attr "type" "ssemov,sseishft,ssemov")
+ (set_attr "length_immediate" "*,1,*")
(set_attr "memory" "*,none,*")
(set_attr "prefix" "vex")
(set_attr "mode" "V2SF,TI,TI")])
psrldq\t{$8, %0|%0, 8}
movq\t{%H1, %0|%0, %H1}"
[(set_attr "type" "ssemov,sseishft,ssemov")
+ (set_attr "length_immediate" "*,1,*")
(set_attr "atom_unit" "*,sishuf,*")
(set_attr "memory" "*,none,*")
(set_attr "mode" "V2SF,TI,TI")])
shufps\t{$0, %0, %0|%0, %0, 0}"
[(set_attr "type" "sselog1")
(set_attr "prefix" "maybe_vex,orig")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI,V4SF")])
(define_insn "*vec_dupv2di_avx"
punpckldq\t{%2, %0|%0, %2}
movd\t{%1, %0|%0, %1}"
[(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
+ (set_attr "prefix_extra" "1,*,*,*,*")
+ (set_attr "length_immediate" "1,*,*,*,*")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "3,4")
(const_string "orig")
movd\t{%1, %0|%0, %1}"
[(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
(set_attr "prefix_extra" "1,*,*,*,*")
+ (set_attr "length_immediate" "1,*,*,*,*")
(set_attr "mode" "TI,TI,TI,DI,DI")])
;; ??? In theory we can match memory for the MMX alternative, but allowing
vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
vmovhps\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov")
+ (set_attr "prefix_extra" "1,*,*,*,*,*")
+ (set_attr "length_immediate" "1,*,*,*,*,*")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "3")
(const_string "orig")
movlhps\t{%2, %0|%0, %2}
movhps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
+ (set_attr "prefix_rex" "1,*,1,*,*,*,*")
(set_attr "prefix_extra" "1,*,*,*,*,*,*")
+ (set_attr "length_immediate" "1,*,*,*,*,*,*")
(set_attr "mode" "TI,TI,TI,TI,TI,V4SF,V2SF")])
(define_insn "*vec_concatv2di_rex64_sse"
movlhps\t{%2, %0|%0, %2}
movhps\t{%2, %0|%0, %2}"
[(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
+ (set_attr "prefix_rex" "*,1,*,*,*,*")
(set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF")])
(define_expand "vec_unpacku_hi_v16qi"
"%vmaskmovdqu\t{%2, %1|%1, %2}"
[(set_attr "type" "ssemov")
(set_attr "prefix_data16" "1")
+ ;; The implicit %rdi operand confuses default length_vex computation.
+ (set_attr "length_vex" "3")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
"%vmaskmovdqu\t{%2, %1|%1, %2}"
[(set_attr "type" "ssemov")
(set_attr "prefix_data16" "1")
+ ;; The implicit %rdi operand confuses default length_vex computation.
+ (set (attr "length_vex")
+ (symbol_ref ("REGNO (operands[2]) >= FIRST_REX_SSE_REG ? 3 + 1 : 2 + 1")))
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
"TARGET_SSE || TARGET_3DNOW_A"
"sfence"
[(set_attr "type" "sse")
+ (set_attr "length_address" "0")
(set_attr "atom_sse_attr" "fence")
(set_attr "memory" "unknown")])
"TARGET_64BIT || TARGET_SSE2"
"mfence"
[(set_attr "type" "sse")
+ (set_attr "length_address" "0")
(set_attr "atom_sse_attr" "fence")
(set_attr "memory" "unknown")])
"TARGET_SSE2"
"lfence"
[(set_attr "type" "sse")
+ (set_attr "length_address" "0")
(set_attr "atom_sse_attr" "lfence")
(set_attr "memory" "unknown")])
"TARGET_AVX"
"vphaddw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "*avx_phadddv4si3"
"TARGET_AVX"
"vphaddd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "*avx_phaddswv8hi3"
"TARGET_AVX"
"vphaddsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "*avx_phsubwv8hi3"
"TARGET_AVX"
"vphsubw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "*avx_phsubdv4si3"
"TARGET_AVX"
"vphsubd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "*avx_phsubswv8hi3"
"TARGET_AVX"
"vphsubsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "*avx_pmaddubsw128"
"TARGET_AVX"
"vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
[(set_attr "type" "sseiadd")
(set_attr "atom_unit" "simul")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_expand "ssse3_pmulhrswv8hi3"
"TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
"vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseimul")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"pmulhrsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "*avx_pshufbv16qi3"
"TARGET_AVX"
"vpshufb\t{%2, %1, %0|%0, %1, %2}";
[(set_attr "type" "sselog1")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"pshufb\t{%2, %0|%0, %2}";
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "*avx_psign<mode>3"
"TARGET_AVX"
"vpsign<ssevecsize>\t{%2, %1, %0|%0, %1, %2}";
[(set_attr "type" "sselog1")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"psign<mmxvecsize>\t{%2, %0|%0, %2}";
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "*avx_palignrti"
return "vpalignr\t{%3, %2, %1, %0|%0, %1, %2, %3}";
}
[(set_attr "type" "sseishft")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
(set_attr "atom_unit" "sishuf")
(set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "ssse3_palignrdi"
[(set_attr "type" "sseishft")
(set_attr "atom_unit" "sishuf")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
+ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
(define_insn "abs<mode>2"
"TARGET_SSSE3"
"pabs<mmxvecsize>\t{%1, %0|%0, %1}";
[(set_attr "type" "sselog1")
+ (set_attr "prefix_rep" "0")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
(set_attr "mode" "DI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
"extrq\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse")
(set_attr "prefix_data16" "1")
+ (set_attr "length_immediate" "2")
(set_attr "mode" "TI")])
(define_insn "sse4a_extrq"
"TARGET_SSE4A"
"insertq\t{%4, %3, %2, %0|%0, %2, %3, %4}"
[(set_attr "type" "sseins")
+ (set_attr "prefix_data16" "0")
(set_attr "prefix_rep" "1")
+ (set_attr "length_immediate" "2")
(set_attr "mode" "TI")])
(define_insn "sse4a_insertq"
"TARGET_SSE4A"
"insertq\t{%2, %0|%0, %2}"
[(set_attr "type" "sseins")
+ (set_attr "prefix_data16" "0")
(set_attr "prefix_rep" "1")
(set_attr "mode" "TI")])
"TARGET_AVX"
"vblendp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemov")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])
"TARGET_AVX"
"vblendvp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemov")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])
"TARGET_SSE4_1"
"blendp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssemov")
+ (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
(define_insn "sse4_1_blendvp<ssemodesuffixf2c>"
"TARGET_SSE4_1"
"blendvp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssemov")
+ (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "mode" "<MODE>")])
"vdpp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemul")
(set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<avxvecmode>")])
(define_insn "sse4_1_dpp<ssemodesuffixf2c>"
"TARGET_SSE4_1"
"dpp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssemul")
+ (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
(define_insn "sse4_1_movntdqa"
"vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "sselog1")
(set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "sse4_1_mpsadbw"
"mpsadbw\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*avx_packusdw"
"TARGET_AVX"
"vpackusdw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"TARGET_AVX"
"vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemov")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "vex")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "sse4_1_pblendw"
"pblendw\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "sse4_1_phminposuw"
"TARGET_AVX"
"vtestp<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecomi")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
"TARGET_AVX"
"vptest\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecomi")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
"TARGET_AVX"
"vroundp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
"TARGET_ROUND"
"%vroundp<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")])
"TARGET_AVX"
"vrounds<ssemodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
"TARGET_ROUND"
"rounds<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,load")
(set_attr "mode" "TI")])
(set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,load")
(set_attr "mode" "TI")])
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "memory" "none,load")
(set_attr "mode" "TI")])
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,load,none,load")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,load")
(set_attr "mode" "TI")])
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "memory" "none,load")
(set_attr "mode" "TI")])
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "memory" "none,load")
(set_attr "mode" "TI")])
[(set_attr "type" "sselog")
(set_attr "prefix_data16" "1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "memory" "none,load,none,load")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
|| register_operand (operands[2], V16QImode))"
"pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
[(set_attr "type" "sseadd")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
(define_insn "sse5_pperm_sign_v16qi_v8hi"
|| register_operand (operands[2], V16QImode))"
"pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
[(set_attr "type" "sseadd")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
(define_insn "sse5_pperm_zero_v8hi_v4si"
|| register_operand (operands[2], V16QImode))"
"pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
[(set_attr "type" "sseadd")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
(define_insn "sse5_pperm_sign_v8hi_v4si"
|| register_operand (operands[2], V16QImode))"
"pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
[(set_attr "type" "sseadd")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
(define_insn "sse5_pperm_zero_v4si_v2di"
|| register_operand (operands[2], V16QImode))"
"pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
[(set_attr "type" "sseadd")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
(define_insn "sse5_pperm_sign_v4si_v2di"
|| register_operand (operands[2], V16QImode))"
"pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
[(set_attr "type" "sseadd")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
;; SSE5 pack instructions that combine two vectors into a smaller vector
"TARGET_SSE5"
"prot<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "sse5_rotr<mode>3"
return \"prot<ssevecsize>\t{%3, %1, %0|%0, %1, %3}\";
}
[(set_attr "type" "sseishft")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_expand "vrotr<mode>3"
"TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 3, true, 1, false)"
"prot<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
;; SSE5 packed shift instructions.
"TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 3, true, 1, false)"
"psha<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
(define_insn "sse5_lshl<mode>3"
"TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 3, true, 1, false)"
"pshl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseishft")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_extra" "2")
(set_attr "mode" "TI")])
;; SSE2 doesn't have some shift varients, so define versions for SSE5
"TARGET_SSE5"
"frcz<ssemodesuffixf4>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt1")
- (set_attr "prefix_extra" "1")
(set_attr "mode" "<MODE>")])
;; scalar insns
"TARGET_SSE5"
"frcz<ssemodesuffixf2s>\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecvt1")
- (set_attr "prefix_extra" "1")
(set_attr "mode" "<MODE>")])
(define_insn "sse5_cvtph2ps"
"TARGET_SSE5"
"com%Y1<ssemodesuffixf2s>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse4arg")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_rep" "0")
+ (set_attr "prefix_extra" "2")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<ssescalarmode>")])
;; We don't have a comparison operator that always returns true/false, so
return ret;
}
[(set_attr "type" "ssecmp")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_rep" "0")
+ (set_attr "prefix_extra" "2")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
(define_insn "sse5_maskcmp<mode>3"
"TARGET_SSE5"
"com%Y1<ssemodesuffixf4>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecmp")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_rep" "0")
+ (set_attr "prefix_extra" "2")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
(define_insn "sse5_maskcmp<mode>3"
"TARGET_SSE5"
"pcom%Y1<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sse4arg")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_rep" "0")
+ (set_attr "prefix_extra" "2")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "sse5_maskcmp_uns<mode>3"
"TARGET_SSE5"
"pcom%Y1u<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecmp")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_rep" "0")
+ (set_attr "prefix_extra" "2")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
;; Version of pcom*u* that is called from the intrinsics that allows pcomequ*
"TARGET_SSE5"
"pcom%Y1u<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecmp")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_extra" "2")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
;; Pcomtrue and pcomfalse support. These are useless instructions, but are
: "pcomfalse<ssevecsize>\t{%2, %1, %0|%0, %1, %2}");
}
[(set_attr "type" "ssecmp")
+ (set_attr "prefix_data16" "0")
+ (set_attr "prefix_extra" "2")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*avx_aesenc"
"TARGET_AES && TARGET_AVX"
"vaesenc\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog1")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"TARGET_AES && TARGET_AVX"
"vaesenclast\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog1")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"TARGET_AES && TARGET_AVX"
"vaesdec\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog1")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"TARGET_AES && TARGET_AVX"
"vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog1")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"%vaeskeygenassist\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
"TARGET_PCLMUL && TARGET_AVX"
"vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "sselog1")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "TI")])
"pclmulqdq\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_expand "avx_vzeroall"
"TARGET_AVX"
"vzeroall"
[(set_attr "type" "sse")
+ (set_attr "modrm" "0")
(set_attr "memory" "none")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
"TARGET_AVX && !TARGET_64BIT"
"vzeroupper"
[(set_attr "type" "sse")
+ (set_attr "modrm" "0")
(set_attr "memory" "none")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
"TARGET_AVX && TARGET_64BIT"
"vzeroupper"
[(set_attr "type" "sse")
+ (set_attr "modrm" "0")
(set_attr "memory" "none")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
"TARGET_AVX"
"vpermilp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
"TARGET_AVX"
"vpermilp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
"TARGET_AVX"
"vperm2f128\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vbroadcasts<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxscalarmode>")])
"TARGET_AVX"
"vbroadcastss\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "SF")])
"TARGET_AVX"
"vbroadcastf128\t{%1, %0|%0, %1}"
[(set_attr "type" "ssemov")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V4SF")])
"TARGET_AVX"
"vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
[(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "V8SF")])
"TARGET_AVX"
"vmaskmovp<avxmodesuffixf2c>\t{%1, %2, %0|%0, %2, %1}"
[(set_attr "type" "sselog1")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
"TARGET_AVX"
"vmaskmovp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog1")
+ (set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
}
}
[(set_attr "type" "sselog,ssemov")
+ (set_attr "prefix_extra" "1,*")
+ (set_attr "length_immediate" "1,*")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])