A warm reset using reset button may put icache and registers
in non-coherent state.
Flush the icache and reset all registers for every hart.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
csrr a6, CSR_MHARTID
blt zero, a6, _wait_for_boot_hart
+ li ra, 0
+ call _reset_regs
/* Zero-out BSS */
la a4, _bss_start
la a5, _bss_end
.globl _reset_regs
_reset_regs:
+ /* flush the instruction cache */
+ fence.i
/* Reset all registers except ra, a0,a1 */
li sp, 0
li gp, 0