iris: Fix aux usage of depth buffer prepare/finish
authorNanley Chery <nanley.g.chery@intel.com>
Wed, 16 Dec 2020 22:57:14 +0000 (14:57 -0800)
committerMarge Bot <eric+marge@anholt.net>
Wed, 10 Feb 2021 20:48:01 +0000 (20:48 +0000)
Prepare/finish a framebuffer's depth buffer with the aux usage that's
appropriate for the given miplevel instead of wrongly assuming that
compression is always enabled. Enables code simplifications later on.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8853>

src/gallium/drivers/iris/iris_context.h
src/gallium/drivers/iris/iris_resolve.c
src/gallium/drivers/iris/iris_resource.h
src/gallium/drivers/iris/iris_state.c

index eb7699a841f79f681a19f0801e90f0fa04b89654..c93b053367089b9cf254b04733ae7c6aa810b5ed 100644 (file)
@@ -707,6 +707,9 @@ struct iris_context {
        */
       enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
 
+      /** Aux usage of the fb's depth buffer (which may or may not exist). */
+      enum isl_aux_usage hiz_usage;
+
       enum gen_urb_deref_block_size urb_deref_block_size;
 
       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
index eb94d3111c7ee46340f8bbd8c65740e0b2a4d674..75f5e3a1afb0cc282bd18b70e84c8408b204922b 100644 (file)
@@ -201,10 +201,9 @@ iris_predraw_resolve_framebuffer(struct iris_context *ice,
             zs_surf->u.tex.last_layer - zs_surf->u.tex.first_layer + 1;
 
          if (z_res) {
-            iris_resource_prepare_depth(ice, batch, z_res,
-                                        zs_surf->u.tex.level,
-                                        zs_surf->u.tex.first_layer,
-                                        num_layers);
+            iris_resource_prepare_render(ice, z_res, zs_surf->u.tex.level,
+                                         zs_surf->u.tex.first_layer,
+                                         num_layers, ice->state.hiz_usage);
             iris_emit_buffer_barrier_for(batch, z_res->bo,
                                          IRIS_DOMAIN_DEPTH_WRITE);
          }
@@ -293,10 +292,10 @@ iris_postdraw_update_resolve_tracking(struct iris_context *ice,
          zs_surf->u.tex.last_layer - zs_surf->u.tex.first_layer + 1;
 
       if (z_res) {
-         if (may_have_resolved_depth) {
-            iris_resource_finish_depth(ice, z_res, zs_surf->u.tex.level,
-                                       zs_surf->u.tex.first_layer, num_layers,
-                                       ice->state.depth_writes_enabled);
+         if (may_have_resolved_depth && ice->state.depth_writes_enabled) {
+            iris_resource_finish_render(ice, z_res, zs_surf->u.tex.level,
+                                        zs_surf->u.tex.first_layer,
+                                        num_layers, ice->state.hiz_usage);
          }
       }
 
@@ -1042,25 +1041,3 @@ iris_resource_finish_render(struct iris_context *ice,
    iris_resource_finish_write(ice, res, level, start_layer, layer_count,
                               aux_usage);
 }
-
-void
-iris_resource_prepare_depth(struct iris_context *ice,
-                            struct iris_batch *batch,
-                            struct iris_resource *res, uint32_t level,
-                            uint32_t start_layer, uint32_t layer_count)
-{
-   iris_resource_prepare_access(ice, res, level, 1, start_layer,
-                                layer_count, res->aux.usage, !!res->aux.bo);
-}
-
-void
-iris_resource_finish_depth(struct iris_context *ice,
-                           struct iris_resource *res, uint32_t level,
-                           uint32_t start_layer, uint32_t layer_count,
-                           bool depth_written)
-{
-   if (depth_written) {
-      iris_resource_finish_write(ice, res, level, start_layer, layer_count,
-                                 res->aux.usage);
-   }
-}
index 7d2ff0aebc67fc880ee6fc807525b635db1742ac..0bbf90f4a333776eed4790ebf4234cc5ed1bee67 100644 (file)
@@ -513,12 +513,4 @@ void iris_resource_finish_render(struct iris_context *ice,
                                  struct iris_resource *res, uint32_t level,
                                  uint32_t start_layer, uint32_t layer_count,
                                  enum isl_aux_usage aux_usage);
-void iris_resource_prepare_depth(struct iris_context *ice,
-                                 struct iris_batch *batch,
-                                 struct iris_resource *res, uint32_t level,
-                                 uint32_t start_layer, uint32_t layer_count);
-void iris_resource_finish_depth(struct iris_context *ice,
-                                struct iris_resource *res, uint32_t level,
-                                uint32_t start_layer, uint32_t layer_count,
-                                bool depth_written);
 #endif
index f120249da3fce6611216bb9969bc7b5af4380cee..3fc172dca4a7c64bb4ca4c34b508923346c5ca86 100644 (file)
@@ -3167,6 +3167,8 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
             info.hiz_surf = &zres->aux.surf;
             info.hiz_address = zres->aux.bo->gtt_offset + zres->aux.offset;
          }
+
+         ice->state.hiz_usage = info.hiz_usage;
       }
 
       if (stencil_res) {