// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2015-2019 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/sdram_rk3036.h>
-#include <asm/arch-rockchip/timer.h>
+
+#define TIMER_LOAD_COUNT_L 0x00
+#define TIMER_LOAD_COUNT_H 0x04
+#define TIMER_CONTROL_REG 0x10
+#define TIMER_EN 0x1
+#define TIMER_FMODE (0 << 1)
+#define TIMER_RMODE (1 << 1)
+
+void rockchip_stimer_init(void)
+{
+ asm volatile("mcr p15, 0, %0, c14, c0, 0"
+ : : "r"(COUNTER_FREQUENCY));
+
+ writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
+ writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
+ TIMER_CONTROL_REG);
+}
void board_init_f(ulong dummy)
{
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
- rockchip_timer_init();
+
+ /* Init secure timer */
+ rockchip_stimer_init();
+ /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
+ timer_init();
+
sdram_init();
/* return to maskrom */
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0
+#define COUNTER_FREQUENCY 24000000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK 24000000
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800