board: bsh: imx8mn_bsh_smm_s2/s2pro: enable DM_SERIAL
authorMichael Trimarchi <michael@amarulasolutions.com>
Mon, 18 Apr 2022 06:53:36 +0000 (08:53 +0200)
committerStefano Babic <sbabic@denx.de>
Thu, 21 Apr 2022 13:18:25 +0000 (15:18 +0200)
Enable DM_SERIAL for both U_Boot and the SPL. The uart4 and its pinmux
are already marked with u-boot,dm-spl but we need to move the call to
preloader_console_init() after spl_init() to avoid a board hang
as dm can't be used until after spl_init().

Remove the manual config of the UART pinmux now that it is no longer
needed.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
board/bsh/imx8mn_smm_s2/spl.c
configs/imx8mn_bsh_smm_s2_defconfig
configs/imx8mn_bsh_smm_s2pro_defconfig

index 5f04731..0f61acc 100644 (file)
@@ -40,14 +40,8 @@ void spl_board_init(void)
                puts("Failed to find clock node. Check device tree\n");
 }
 
-#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
 #define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
 
-static const iomux_v3_cfg_t uart_pads[] = {
-       IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-       IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 static const iomux_v3_cfg_t wdog_pads[] = {
        IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
@@ -59,7 +53,6 @@ int board_early_init_f(void)
        imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
        set_wdog_reset(wdog);
 
-       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
        init_uart_clk(3);
 
        if (IS_ENABLED(CONFIG_NAND_MXS)) {
@@ -82,14 +75,14 @@ void board_init_f(ulong dummy)
 
        timer_init();
 
-       preloader_console_init();
-
        ret = spl_init();
        if (ret) {
                debug("spl_init() failed: %d\n", ret);
                hang();
        }
 
+       preloader_console_init();
+
        /* DDR initialization */
        spl_dram_init();
 
index 3d67079..e864685 100644 (file)
@@ -80,6 +80,7 @@ CONFIG_SPL_DM_PMIC_BD71837=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
index c5809f5..dfc9c93 100644 (file)
@@ -77,6 +77,7 @@ CONFIG_SPL_DM_PMIC_BD71837=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y