* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2

	operands.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 57a4f01..ac5e82c 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2011-05-19  Nick Clifton  <nickc@redhat.com>
+
+       * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
+       operands.
+

 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 
        * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 
        * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.

diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index eea427c..67ba562 100644 (file)
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -1205,10 +1205,10 @@ const struct v850_opcode v850_opcodes[] =
 { "cmovf.s",   two (0x07e0, 0x0400),   two (0x07e0, 0x07f1),   {FFF, R1, R2, R3_NOTR0},                0, PROCESSOR_V850E2V3 },
 /* Default value for FFF is 0(not defined in spec).  */
 { "cmovf.s",   two (0x07e0, 0x0400),   two (0x07e0, 0x07ff),   {R1, R2, R3_NOTR0},                     0, PROCESSOR_V850E2V3 },
 { "cmovf.s",   two (0x07e0, 0x0400),   two (0x07e0, 0x07f1),   {FFF, R1, R2, R3_NOTR0},                0, PROCESSOR_V850E2V3 },
 /* Default value for FFF is 0(not defined in spec).  */
 { "cmovf.s",   two (0x07e0, 0x0400),   two (0x07e0, 0x07ff),   {R1, R2, R3_NOTR0},                     0, PROCESSOR_V850E2V3 },

-{ "cmpf.d",    two (0x07e0, 0x0430),   two (0x0fe1, 0x87f1),   {FLOAT_CCCC, R1_EVEN, R2_EVEN, FFF},    0, PROCESSOR_V850E2V3 },
-{ "cmpf.d",    two (0x07e0, 0x0430),   two (0x0fe1, 0x87ff),   {FLOAT_CCCC, R1_EVEN, R2_EVEN},         0, PROCESSOR_V850E2V3 },
-{ "cmpf.s",    two (0x07e0, 0x0420),   two (0x07e0, 0x87f1),   {FLOAT_CCCC, R1, R2, FFF},              0, PROCESSOR_V850E2V3 },
-{ "cmpf.s",    two (0x07e0, 0x0420),   two (0x07e0, 0x87ff),   {FLOAT_CCCC, R1, R2},                   0, PROCESSOR_V850E2V3 },
+{ "cmpf.d",    two (0x07e0, 0x0430),   two (0x0fe1, 0x87f1),   {FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF},    0, PROCESSOR_V850E2V3 },
+{ "cmpf.d",    two (0x07e0, 0x0430),   two (0x0fe1, 0x87ff),   {FLOAT_CCCC, R2_EVEN, R1_EVEN},         0, PROCESSOR_V850E2V3 },
+{ "cmpf.s",    two (0x07e0, 0x0420),   two (0x07e0, 0x87f1),   {FLOAT_CCCC, R2, R1, FFF},              0, PROCESSOR_V850E2V3 },
+{ "cmpf.s",    two (0x07e0, 0x0420),   two (0x07e0, 0x87ff),   {FLOAT_CCCC, R2, R1},                   0, PROCESSOR_V850E2V3 },

 { "cvtf.dl",   two (0x07e4, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
 { "cvtf.ds",   two (0x07e3, 0x0452),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
 { "cvtf.dul",  two (0x07f4, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
 { "cvtf.dl",   two (0x07e4, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },
 { "cvtf.ds",   two (0x07e3, 0x0452),   two (0x0fff, 0x07ff),   {R2_EVEN, R3},                          0, PROCESSOR_V850E2V3 },
 { "cvtf.dul",  two (0x07f4, 0x0454),   two (0x0fff, 0x0fff),   {R2_EVEN, R3_EVEN},                     0, PROCESSOR_V850E2V3 },