The AArch64 TLSDESC to IE relaxation code uses a bit mask intended to
ensure that destination register in a relaxed ldr instruction is
always X0. The mask has an off by one error resulting in the most
significant bit of the destination register being retained in the
relaxed instruction. The issue generally appears when the compiler
emits TLS accesses code under high register pressure resulting in a
broken code sequence.
+2014-04-15 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * (elfNN_aarch64_tls_relax): Fix instruction mask.
+
2014-04-14 Alan Modra <amodra@gmail.com>
* elf32-ppc.c (BA): Define
2014-04-14 Alan Modra <amodra@gmail.com>
* elf32-ppc.c (BA): Define
ldr xd, [x0, #:tlsdesc_lo12:var] => ldr x0, [x0, #:gottprel_lo12:var]
*/
insn = bfd_getl32 (contents + rel->r_offset);
ldr xd, [x0, #:tlsdesc_lo12:var] => ldr x0, [x0, #:gottprel_lo12:var]
*/
insn = bfd_getl32 (contents + rel->r_offset);
bfd_putl32 (insn, contents + rel->r_offset);
return bfd_reloc_continue;
}
bfd_putl32 (insn, contents + rel->r_offset);
return bfd_reloc_continue;
}
+2014-04-15 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * ld-aarch64/tls-relax-gdesc-ie.s (var): Adjust test case
+ to include all 5 bits of LDR destination register.
+
2014-04-10 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
* ld-avr/norelax_diff.d: New testcase.
2014-04-10 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
* ld-avr/norelax_diff.d: New testcase.
.word 2
.text
adrp x0, :tlsdesc:var
.word 2
.text
adrp x0, :tlsdesc:var
- ldr x1, [x0, #:tlsdesc_lo12:var]
+ ldr x17, [x0, #:tlsdesc_lo12:var]
add x0, x0, :tlsdesc_lo12:var
.tlsdesccall var
blr x1
add x0, x0, :tlsdesc_lo12:var
.tlsdesccall var
blr x1