arm64: dts: imx8mm: Enable CPLD_Dn pull down resistor on MX8Menlo

Enable CPLD_Dn pull down resistor instead of pull up to avoid
intefering with CPLD power off functionality.

Fixes: 510c527b4ff57 ("arm64: dts: imx8mm: Add i.MX8M Mini Toradex Verdin based Menlo board")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
index 32f6f2f..43e8985 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
@@ -250,21 +250,21 @@
                /* SODIMM 96 */
                MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4                        0x1c4
                /* CPLD_D[7] */
                /* SODIMM 96 */
                MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4                        0x1c4
                /* CPLD_D[7] */

-               MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5                        0x1c4
+               MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5                        0x184

                /* CPLD_D[6] */
                /* CPLD_D[6] */

-               MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0                        0x1c4
+               MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0                        0x184

                /* CPLD_D[5] */
                /* CPLD_D[5] */

-               MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11                        0x1c4
+               MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11                        0x184

                /* CPLD_D[4] */
                /* CPLD_D[4] */

-               MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12                       0x1c4
+               MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12                       0x184

                /* CPLD_D[3] */
                /* CPLD_D[3] */

-               MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13                       0x1c4
+               MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13                       0x184

                /* CPLD_D[2] */
                /* CPLD_D[2] */

-               MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14                       0x1c4
+               MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14                       0x184

                /* CPLD_D[1] */
                /* CPLD_D[1] */

-               MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15                       0x1c4
+               MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15                       0x184

                /* CPLD_D[0] */
                /* CPLD_D[0] */

-               MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16                       0x1c4
+               MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16                       0x184

                /* KBD_intK */
                MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27                       0x1c4
                /* DISP_reset */
                /* KBD_intK */
                MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27                       0x1c4
                /* DISP_reset */