reset: Create subdirectory for StarFive drivers

This moves the StarFive JH7100 reset driver to a new subdirectory in
preparation for adding more StarFive reset drivers.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 1346770..b2e2ce8 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19661,7 +19661,7 @@ STARFIVE JH7100 RESET CONTROLLER DRIVER
 M:     Emil Renner Berthing <kernel@esmil.dk>
 S:     Maintained
 F:     Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
 M:     Emil Renner Berthing <kernel@esmil.dk>
 S:     Maintained
 F:     Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml

-F:     drivers/reset/reset-starfive-jh7100.c
+F:     drivers/reset/starfive/reset-starfive-jh7100.c

 F:     include/dt-bindings/reset/starfive-jh7100.h
 
 STARFIVE SOC DRIVERS
 F:     include/dt-bindings/reset/starfive-jh7100.h
 
 STARFIVE SOC DRIVERS

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 6ae5aa4..6aa8f24 100644 (file)
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -232,13 +232,6 @@ config RESET_SOCFPGA
          This enables the reset driver for the SoCFPGA ARMv7 platforms. This
          driver gets initialized early during platform init calls.
 
          This enables the reset driver for the SoCFPGA ARMv7 platforms. This
          driver gets initialized early during platform init calls.
 

-config RESET_STARFIVE_JH7100
-       bool "StarFive JH7100 Reset Driver"
-       depends on ARCH_STARFIVE || COMPILE_TEST
-       default ARCH_STARFIVE
-       help
-         This enables the reset controller driver for the StarFive JH7100 SoC.
-

 config RESET_SUNPLUS
        bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
        default ARCH_SUNPLUS
 config RESET_SUNPLUS
        bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
        default ARCH_SUNPLUS


@@ -320,6 +313,7 @@ config RESET_ZYNQ
        help
          This enables the reset controller driver for Xilinx Zynq SoCs.
 
        help
          This enables the reset controller driver for Xilinx Zynq SoCs.
 

+source "drivers/reset/starfive/Kconfig"

 source "drivers/reset/sti/Kconfig"
 source "drivers/reset/hisilicon/Kconfig"
 source "drivers/reset/tegra/Kconfig"
 source "drivers/reset/sti/Kconfig"
 source "drivers/reset/hisilicon/Kconfig"
 source "drivers/reset/tegra/Kconfig"

diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 3e7e5fd..7fec5af 100644 (file)
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-y += core.o
 obj-y += hisilicon/
 # SPDX-License-Identifier: GPL-2.0
 obj-y += core.o
 obj-y += hisilicon/

+obj-y += starfive/

 obj-$(CONFIG_ARCH_STI) += sti/
 obj-$(CONFIG_ARCH_TEGRA) += tegra/
 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
 obj-$(CONFIG_ARCH_STI) += sti/
 obj-$(CONFIG_ARCH_TEGRA) += tegra/
 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o


@@ -30,7 +31,6 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o

-obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o

 obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o

diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
new file mode 100644 (file)
index 0000000..abbf0c5
--- /dev/null
+++ b/drivers/reset/starfive/Kconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config RESET_STARFIVE_JH7100
+       bool "StarFive JH7100 Reset Driver"
+       depends on ARCH_STARFIVE || COMPILE_TEST
+       default ARCH_STARFIVE
+       help
+         This enables the reset controller driver for the StarFive JH7100 SoC.

diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
new file mode 100644 (file)
index 0000000..670d049
--- /dev/null
+++ b/drivers/reset/starfive/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_RESET_STARFIVE_JH7100)            += reset-starfive-jh7100.o

diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
similarity index 100%
rename from drivers/reset/reset-starfive-jh7100.c
rename to drivers/reset/starfive/reset-starfive-jh7100.c