tegra: Add support for PWM

The pulse width/frequency modulation peripheral supports generating
a repeating pulse. It is useful for controlling LCD brightness.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/armv7/tegra20/Makefile
index 09a0314..77cb4d1 100644 (file)
--- a/arch/arm/cpu/armv7/tegra20/Makefile
+++ b/arch/arm/cpu/armv7/tegra20/Makefile
@@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk
 LIB    =  $(obj)lib$(SOC).o
 
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
 LIB    =  $(obj)lib$(SOC).o
 
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o

+COBJS-$(CONFIG_PWM_TEGRA) += pwm.o

 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)

diff --git a/arch/arm/cpu/armv7/tegra20/pwm.c b/arch/arm/cpu/armv7/tegra20/pwm.c
new file mode 100644 (file)
index 0000000..b655c5c
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra20/pwm.c
@@ -0,0 +1,101 @@
+/*
+ * Tegra2 pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pwm.h>
+
+struct pwm_info {
+       struct pwm_ctlr *pwm;           /* Registers for our pwm controller */
+       int pwm_node;                   /* PWM device tree node */
+} local;
+
+void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider)
+{
+       u32 reg;
+
+       assert(channel < PWM_NUM_CHANNELS);
+
+       /* TODO: Can we use clock_adjust_periph_pll_div() here? */
+       clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, rate);
+
+       reg = PWM_ENABLE_MASK;
+       reg |= pulse_width << PWM_WIDTH_SHIFT;
+       reg |= freq_divider << PWM_DIVIDER_SHIFT;
+       writel(reg, &local.pwm[channel].control);
+       debug("%s: channel=%d, rate=%d\n", __func__, channel, rate);
+}
+
+int pwm_request(const void *blob, int node, const char *prop_name)
+{
+       int pwm_node;
+       u32 data[3];
+
+       if (fdtdec_get_int_array(blob, node, prop_name, data,
+                       ARRAY_SIZE(data))) {
+               debug("%s: Cannot decode PWM property '%s'\n", __func__,
+                     prop_name);
+               return -1;
+       }
+
+       pwm_node = fdt_node_offset_by_phandle(blob, data[0]);
+       if (pwm_node != local.pwm_node) {
+               debug("%s: PWM property '%s' phandle %d not recognised"
+                     "- expecting %d\n", __func__, prop_name, data[0],
+                     local.pwm_node);
+               return -1;
+       }
+       if (data[1] >= PWM_NUM_CHANNELS) {
+               debug("%s: PWM property '%s': invalid channel %u\n", __func__,
+                     prop_name, data[1]);
+               return -1;
+       }
+
+       /*
+        * TODO: We could maintain a list of requests, but it might not be
+        * worth it for U-Boot.
+        */
+       return data[1];
+}
+
+int pwm_init(const void *blob)
+{
+       local.pwm_node = fdtdec_next_compatible(blob, 0,
+                                               COMPAT_NVIDIA_TEGRA20_PWM);
+       if (local.pwm_node < 0) {
+               debug("%s: Cannot find device tree node\n", __func__);
+               return -1;
+       }
+
+       local.pwm = (struct pwm_ctlr *)fdtdec_get_addr(blob, local.pwm_node,
+                                                      "reg");
+       if (local.pwm == (struct pwm_ctlr *)FDT_ADDR_T_NONE) {
+               debug("%s: Cannot find pwm reg address\n", __func__);
+               return -1;
+       }
+       debug("Tegra PWM at %p, node %d\n", local.pwm, local.pwm_node);
+
+       return 0;
+}

diff --git a/arch/arm/include/asm/arch-tegra20/pwm.h b/arch/arm/include/asm/arch-tegra20/pwm.h
new file mode 100644 (file)
index 0000000..9e03837
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/pwm.h
@@ -0,0 +1,75 @@
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TEGRA_PWM_H
+#define __ASM_ARCH_TEGRA_PWM_H
+
+/* This is a single PWM channel */
+struct pwm_ctlr {
+       uint control;           /* Control register */
+       uint reserved[3];       /* Space space */
+};
+
+#define PWM_NUM_CHANNELS       4
+
+/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */
+#define PWM_ENABLE_SHIFT       31
+#define PWM_ENABLE_MASK        (0x1 << PWM_ENABLE_SHIFT)
+
+#define PWM_WIDTH_SHIFT        16
+#define PWM_WIDTH_MASK         (0x7FFF << PWM_WIDTH_SHIFT)
+
+#define PWM_DIVIDER_SHIFT      0
+#define PWM_DIVIDER_MASK       (0x1FFF << PWM_DIVIDER_SHIFT)
+
+/**
+ * Program the PWM with the given parameters.
+ *
+ * @param channel      PWM channel to update
+ * @param rate         Clock rate to use for PWM
+ * @param pulse_width  high pulse width: 0=always low, 1=1/256 pulse high,
+ *                     n = n/256 pulse high
+ * @param freq_divider frequency divider value (1 to use rate as is)
+ */
+void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider);
+
+/**
+ * Request a pwm channel as referenced by a device tree node.
+ *
+ * This channel can then be passed to pwm_enable().
+ *
+ * @param blob         Device tree blob
+ * @param node         Node containing reference to pwm
+ * @param prop_name    Property name of pwm reference
+ * @return channel number, if ok, else -1
+ */
+int pwm_request(const void *blob, int node, const char *prop_name);
+
+/**
+ * Set up the pwm controller, by looking it up in the fdt.
+ *
+ * @return 0 if ok, -1 if the device tree node was not found or invalid.
+ */
+int pwm_init(const void *blob);
+
+#endif /* __ASM_ARCH_TEGRA_PWM_H */

diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 2c7cd0d..f23c87d 100644 (file)
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -30,6 +30,7 @@
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/pmu.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/pmu.h>

+#include <asm/arch/pwm.h>

 #include <asm/arch/tegra.h>
 #include <asm/arch/usb.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch/usb.h>
 #include <asm/arch-tegra/board.h>


@@ -119,6 +120,10 @@ int board_init(void)
        pin_mux_spi();
        spi_init();
 #endif
        pin_mux_spi();
        spi_init();
 #endif

+#ifdef CONFIG_PWM_TEGRA
+       if (pwm_init(gd->fdt_blob))
+               debug("%s: Failed to init pwm\n", __func__);
+#endif

        /* boot param addr */
        gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
 
        /* boot param addr */
        gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
 

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 0b14075..cdc87eb 100644 (file)
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -66,6 +66,7 @@ enum fdt_compat_id {
        COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
        COMPAT_NVIDIA_TEGRA20_KBC,      /* Tegra20 Keyboard */
        COMPAT_NVIDIA_TEGRA20_NAND,     /* Tegra2 NAND controller */
        COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
        COMPAT_NVIDIA_TEGRA20_KBC,      /* Tegra20 Keyboard */
        COMPAT_NVIDIA_TEGRA20_NAND,     /* Tegra2 NAND controller */

+       COMPAT_NVIDIA_TEGRA20_PWM,      /* Tegra 2 PWM controller */

 
        COMPAT_COUNT,
 };
 
        COMPAT_COUNT,
 };

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 4c23f45..947f7c0 100644 (file)
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -43,6 +43,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
        COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
        COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"),
        COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
        COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
        COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"),
        COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),

+       COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),

 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)