sim: bfin: more astat tests

These are the randomly generated tests that directed some of the recent
astat related fixes.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog
index 23ca758..a23fe1d 100644 (file)
--- a/sim/testsuite/sim/bfin/ChangeLog
+++ b/sim/testsuite/sim/bfin/ChangeLog
@@ -1,3 +1,7 @@
+2012-04-09  Robin Getz  <robin.getz@analog.com>
+
+       * random_0036.S, random_0037.S: New astat tests.
+

 2012-04-09  Mike Frysinger  <vapier@gentoo.org>
 
        * se_all64bitg1opcodes.S: Delete xfail line.
 2012-04-09  Mike Frysinger  <vapier@gentoo.org>
 
        * se_all64bitg1opcodes.S: Delete xfail line.

diff --git a/sim/testsuite/sim/bfin/random_0036.S b/sim/testsuite/sim/bfin/random_0036.S
new file mode 100644 (file)
index 0000000..7e75da9
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0036.S
@@ -0,0 +1,309 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+       start
+
+       dmm32 ASTAT, (0x3ce04490 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY);
+       dmm32 A0.w, 0x7d8d8272;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xe0004138;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0x7d8e7fff;
+       imm32 R2, 0xffff8001;
+       A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
+       checkreg A0.w, 0xfd8c0273;
+       checkreg A0.x, 0x00000000;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x3ce04490 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY);
+
+       dmm32 ASTAT, (0x70b0c800 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
+       dmm32 A0.w, 0x53931540;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xf07795da;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R2, 0x8931da0a;
+       imm32 R4, 0xffff41eb;
+       imm32 R5, 0x7fff41eb;
+       A1 += R5.L * R4.H (M), R2 = (A0 -= R5.L * R4.H) (FU);
+       checkreg R2, 0x11a8572b;
+       checkreg A0.w, 0x11a8572b;
+       checkreg A0.x, 0x00000000;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x70b0c800 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AC0_COPY);
+
+       dmm32 ASTAT, (0x58100410 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY | _AC0_COPY);
+       dmm32 A0.w, 0xaeba0d61;
+       dmm32 A0.x, 0x00000041;
+       dmm32 A1.w, 0xbb313d2f;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R4, 0x1ea2588d;
+       imm32 R7, 0xffffffff;
+       A1 += R4.L * R7.H (M), A0 += R4.L * R7.L (FU);
+       checkreg A0.w, 0x0746b4d4;
+       checkreg A0.x, 0x00000042;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x58100410 | _VS | _V | _AV1S | _AV1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
+
+       dmm32 ASTAT, (0x58704200 | _VS | _AV1S | _AV0S);
+       dmm32 A0.w, 0xb7ab4854;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xe0002429;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0xb7ac8000;
+       imm32 R2, 0x80008001;
+       A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
+       checkreg A0.w, 0xf7ab4854;
+       checkreg A0.x, 0x00000000;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x58704200 | _VS | _AV1S | _AV1 | _AV0S);
+
+       dmm32 ASTAT, (0x38d0c800 | _VS | _AV1S | _AV0S);
+       dmm32 A0.w, 0xfffe0001;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xffff4001;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0xffffffff;
+       imm32 R2, 0xffffffff;
+       A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
+       checkreg A0.w, 0xfffc0002;
+       checkreg A0.x, 0x00000001;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x38d0c800 | _VS | _AV1S | _AV1 | _AV0S);
+
+       dmm32 ASTAT, (0x24e0ca80 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY);
+       dmm32 A0.w, 0x0000000a;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xff5439dc;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0x3ea961c5;
+       imm32 R6, 0xffff0510;
+       A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU);
+       checkreg A0.w, 0x00000000;
+       checkreg A0.x, 0x00000000;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x24e0ca80 | _VS | _V | _AV1S | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _V_COPY);
+
+       dmm32 ASTAT, (0x7800cc80 | _VS | _AC1 | _AC0 | _CC | _AC0_COPY);
+       dmm32 A0.w, 0xfffe0001;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xffff4001;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0xffffffff;
+       imm32 R2, 0x0000ffff;
+       A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x7800cc80 | _VS | _AV1S | _AV1 | _AC1 | _AC0 | _CC | _AC0_COPY);
+
+       dmm32 ASTAT, (0x50200800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY);
+       dmm32 A0.w, 0x6970968f;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xe0004b47;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0x69717fff;
+       imm32 R2, 0xffff8001;
+       A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
+       checkreg A0.w, 0xe96f1690;
+       checkreg A0.x, 0x00000000;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x50200800 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AC0_COPY);
+
+       dmm32 ASTAT, (0x34704080 | _VS | _AV1S | _AV1 | _AV0S | _AQ | _CC | _AC0_COPY);
+       dmm32 A0.w, 0x0839a708;
+       dmm32 A0.x, 0xffffff80;
+       dmm32 A1.w, 0xffffffff;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0x0c8c109a;
+       imm32 R2, 0x109a0c8c;
+       imm32 R5, 0x006dd6ac;
+       A1 -= R5.L * R0.L (M), R2.L = (A0 += R5.H * R0.L) (FU);
+       checkreg R2, 0x109affff;
+       checkreg A0.w, 0x0840b89a;
+       checkreg A0.x, 0xffffff80;
+       checkreg ASTAT, (0x34704080 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY);
+
+       dmm32 ASTAT, (0x78108090 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY);
+       dmm32 A0.w, 0x21edde12;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xe0006f08;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0x21ee7fff;
+       imm32 R2, 0xffff8001;
+       A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
+       checkreg A0.w, 0xa1ec5e13;
+       checkreg A0.x, 0x00000000;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x78108090 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY);
+
+       dmm32 ASTAT, (0x50b08a10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
+       dmm32 A0.w, 0x00000007;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xf8b109fc;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0x27827703;
+       imm32 R6, 0xffff03ca;
+       A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU);
+       checkreg A0.w, 0x00000000;
+       checkreg A0.x, 0x00000000;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x50b08a10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
+
+       dmm32 ASTAT, (0x34e0c800 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY);
+       dmm32 A0.w, 0xffffffff;
+       dmm32 A0.x, 0xffffffff;
+       dmm32 A1.w, 0xefc2be42;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0x53574850;
+       imm32 R6, 0xffff1400;
+       A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU);
+       checkreg A0.w, 0xaca95356;
+       checkreg A0.x, 0xffffffff;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x34e0c800 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _V_COPY);
+
+       dmm32 ASTAT, (0x24608c80 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY);
+       dmm32 A0.w, 0x0f03f0fc;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xe000787d;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0x0f04ffff;
+       imm32 R2, 0xffff8001;
+       A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
+       checkreg A0.w, 0x0f01f0fd;
+       checkreg A0.x, 0x00000001;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x24608c80 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY);
+
+       dmm32 ASTAT, (0x58404690 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
+       dmm32 A0.w, 0x1e65e19a;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xe00070cc;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0x1e66ffff;
+       imm32 R2, 0xffff8001;
+       A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
+       checkreg A0.w, 0x1e63e19b;
+       checkreg A0.x, 0x00000001;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x58404690 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
+
+       dmm32 ASTAT, (0x08004a10 | _VS | _AV1S | _AV1 | _AC0 | _CC | _AC0_COPY);
+       dmm32 A1.w, 0xffffffff;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0x293a8000;
+       imm32 R3, 0xd0e6382b;
+       A1 += R3.L * R0.H (M, FU);
+       checkreg ASTAT, (0x08004a10 | _VS | _AV1S | _AV1 | _AC0 | _CC | _AC0_COPY);
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg R0, 0x293a8000;
+       checkreg R3, 0xd0e6382b;
+
+       dmm32 ASTAT, (0x28e00e00 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY);
+       dmm32 A0.w, 0xfffe0001;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xffff4001;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0xffffffff;
+       imm32 R2, 0x0000ffff;
+       A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x28e00e00 | _VS | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY);
+
+       dmm32 ASTAT, (0x14004690 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
+       dmm32 A1.w, 0xffffffff;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0x369a8000;
+       imm32 R3, 0xf023457e;
+       A1 += R3.L * R0.H (M, FU);
+       checkreg ASTAT, (0x14004690 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg R0, 0x369a8000;
+       checkreg R3, 0xf023457e;
+
+       dmm32 ASTAT, (0x5c600680 | _VS | _AV1S | _AQ | _CC);
+       dmm32 A0.w, 0xfffe0001;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xffff4001;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0xffffffff;
+       imm32 R2, 0xffffffff;
+       A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
+       checkreg A0.w, 0xfffc0002;
+       checkreg A0.x, 0x00000001;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x5c600680 | _VS | _AV1S | _AV1 | _AQ | _CC);
+
+       dmm32 ASTAT, (0x7cd00800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY);
+       dmm32 A0.w, 0xfffe0001;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xffff4001;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0xffffffff;
+       imm32 R2, 0x0000ffff;
+       A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x7cd00800 | _VS | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AC0_COPY);
+
+       dmm32 ASTAT, (0x78e0cc10 | _VS | _AV1S | _AV0S | _AC1);
+       dmm32 A0.w, 0xfffe0001;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xffff4001;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0xffffffff;
+       imm32 R2, 0xffffffff;
+       A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU);
+       checkreg A0.w, 0xfffc0002;
+       checkreg A0.x, 0x00000001;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x78e0cc10 | _VS | _AV1S | _AV1 | _AV0S | _AC1);
+
+       dmm32 ASTAT, (0x1cd04c80 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY);
+       dmm32 A0.w, 0x00000015;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xfeeaa91d;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0x50246875;
+       imm32 R6, 0xffff0aab;
+       A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU);
+       checkreg A0.w, 0x00000000;
+       checkreg A0.x, 0x00000000;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x1cd04c80 | _VS | _V | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _V_COPY | _AC0_COPY);
+
+       dmm32 ASTAT, (0x18304890 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
+       dmm32 A0.w, 0xfffffffe;
+       dmm32 A0.x, 0xffffffff;
+       dmm32 A1.w, 0xffffca85;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R0, 0xffffffff;
+       imm32 R3, 0xffffdc58;
+       imm32 R7, 0xffff950a;
+       A1 -= R7.L * R0.H (M), R3.L = (A0 -= R7.L * R0.H) (FU);
+       checkreg R3, 0xffffffff;
+       checkreg A0.w, 0x6af69508;
+       checkreg A0.x, 0xffffffff;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x18304890 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
+
+       pass

diff --git a/sim/testsuite/sim/bfin/random_0037.S b/sim/testsuite/sim/bfin/random_0037.S
new file mode 100644 (file)
index 0000000..05eae8a
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0037.S
@@ -0,0 +1,84 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+       start
+
+       dmm32 ASTAT, (0x1880c200 | _VS | _AV1S | _AV0S | _AC1);
+       dmm32 A0.w, 0x2b9a5661;
+       dmm32 A0.x, 0x00000032;
+       dmm32 A1.w, 0x1a0c4c8c;
+       dmm32 A1.x, 0xffffff80;
+       imm32 R0, 0x694a9cb0;
+       imm32 R6, 0x651cc0dd;
+       A1 += R0.L * R0.H (M), R6.L = (A0 += R0.L * R0.H) (TFU);
+       checkreg R6, 0x651cffff;
+       checkreg A0.w, 0x6c0bd141;
+       checkreg A0.x, 0x00000032;
+       checkreg A1.w, 0x00000000;
+       checkreg A1.x, 0xffffff80;
+       checkreg ASTAT, (0x1880c200 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _V_COPY);
+
+       dmm32 ASTAT, (0x14104490 | _VS | _AV1S | _AZ);
+       dmm32 A0.w, 0x6ec017a0;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xff6f5846;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R3, 0x256a8306;
+       imm32 R6, 0x6a8ca1e4;
+       imm32 R7, 0x2e579ce0;
+       R6.H = (A1 -= R3.L * R7.L) (M), A0 = R3.L * R7.L (TFU);
+       checkreg R6, 0x7fffa1e4;
+       checkreg A0.w, 0x504a4d40;
+       checkreg A0.x, 0x00000000;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x14104490 | _VS | _V | _AV1S | _AV1 | _V_COPY | _AZ);
+
+       dmm32 ASTAT, (0x20008080 | _VS | _V | _AV1S | _AV0 | _AC1 | _AC0 | _AQ);
+       dmm32 A0.w, 0x58b9bdf1;
+       dmm32 A0.x, 0xffffffe2;
+       dmm32 A1.w, 0x42c9fae8;
+       dmm32 A1.x, 0xffffff80;
+       imm32 R1, 0x68df1898;
+       imm32 R2, 0x3ae1b1f0;
+       imm32 R5, 0x61c3f5ef;
+       A1 += R2.L * R5.L (M), R1.L = (A0 -= R2.L * R5.L) (TFU);
+       checkreg R1, 0x68dfffff;
+       checkreg A0.w, 0xadc8eee1;
+       checkreg A0.x, 0xffffffe1;
+       checkreg A1.w, 0x00000000;
+       checkreg A1.x, 0xffffff80;
+       checkreg ASTAT, (0x20008080 | _VS | _V | _AV1S | _AV1 | _AC1 | _AC0 | _AQ | _V_COPY);
+
+       dmm32 ASTAT, (0x1c70ca90 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AC0_COPY);
+       dmm32 A0.w, 0x082c2157;
+       dmm32 A0.x, 0xffffff9f;
+       dmm32 A1.w, 0x275e1474;
+       dmm32 A1.x, 0xffffff80;
+       imm32 R1, 0x7d3179fd;
+       imm32 R2, 0x5b41566f;
+       R2.H = (A1 -= R1.L * R1.H) (M), R2.L = (A0 = R1.L * R1.L) (TFU);
+       checkreg R2, 0x80003a21;
+       checkreg A0.w, 0x3a212409;
+       checkreg A0.x, 0x00000000;
+       checkreg A1.w, 0x00000000;
+       checkreg A1.x, 0xffffff80;
+       checkreg ASTAT, (0x1c70ca90 | _VS | _V | _AV1S | _AV1 | _AV0S | _CC | _V_COPY | _AC0_COPY);
+
+       dmm32 ASTAT, (0x7460cc10 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY);
+       dmm32 A0.w, 0x7fffffff;
+       dmm32 A0.x, 0x00000000;
+       dmm32 A1.w, 0xf20b4000;
+       dmm32 A1.x, 0x0000007f;
+       imm32 R1, 0x2ca2d045;
+       imm32 R6, 0x6e516a3c;
+       R1.H = (A1 -= R1.L * R6.H) (M), A0 = R1.L * R6.H (TFU);
+       checkreg R1, 0x7fffd045;
+       checkreg A0.w, 0x59bf8bd5;
+       checkreg A0.x, 0x00000000;
+       checkreg A1.w, 0xffffffff;
+       checkreg A1.x, 0x0000007f;
+       checkreg ASTAT, (0x7460cc10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AQ | _CC | _V_COPY);
+
+       pass