* decode.c, decode.h, sem.c, sem-switch.c, model.c: Regenerate.

	* cpux.c, decodex.c, decodex.h, readx.c, semx.c, modelx.c: Regenerate.

diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
index c9ee966..e043eb7 100644 (file)
--- a/sim/m32r/ChangeLog
+++ b/sim/m32r/ChangeLog
@@ -1,3 +1,23 @@
+Wed Feb 11 18:52:40 1998  Doug Evans  <devans@seba.cygnus.com>
+
+       * decode.c, decode.h, sem.c, sem-switch.c, model.c: Regenerate.
+start-sanitize-m32rx
+       * cpux.c, decodex.c, decodex.h, readx.c, semx.c, modelx.c: Regenerate.
+end-sanitize-m32rx
+
+Mon Feb  9 19:41:54 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+       * decode.c, sem.c: Regenerate.
+start-sanitize-m32rx
+       * cpux.h, decodex.c, readx.c, semx.c: Regenerate.
+       * m32rx.c (m32rx_h_accums_set): New function.
+       (m32rx_model_mark_[gs]et_h_gr): New function.
+       * mloopx.in: Rewrite.
+       * Makefile.in (mloopx.o): Build with -parallel.
+       * sim-main.h (_sim_cpu): Delete member `par_exec'.
+       * tconfig.in (WITH_SEM_SWITCH_FULL): Define as 0 for m32rx.
+end-sanitize-m32rx
+

 Thu Feb  5 12:44:31 1998  Doug Evans  <devans@seba.cygnus.com>
 
        * Makefile.in (m32r.o): Depend on cpu.h
 Thu Feb  5 12:44:31 1998  Doug Evans  <devans@seba.cygnus.com>
 
        * Makefile.in (m32r.o): Depend on cpu.h

diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
index c647d46..49e887d 100644 (file)
--- a/sim/m32r/cpux.h
+++ b/sim/m32r/cpux.h
@@ -280,50 +280,59 @@ struct argbuf {
     struct { /* e.g. nop */
       int empty;
     } fmt_41_nop;
     struct { /* e.g. nop */
       int empty;
     } fmt_41_nop;

-    struct { /* e.g. rac $accs */
+    struct { /* e.g. rac $accd */
+      UINT f_accd;
+    } fmt_42_rac_d;
+    struct { /* e.g. rac $accd,$accs */
+      UINT f_accd;

       UINT f_accs;
       UINT f_accs;

-    } fmt_42_rac_a;
+    } fmt_43_rac_ds;
+    struct { /* e.g. rac $accd,$accs,#$imm1 */
+      UINT f_accd;
+      UINT f_accs;
+      USI f_imm1;
+    } fmt_44_rac_dsi;

     struct { /* e.g. rte */
       int empty;
     struct { /* e.g. rte */
       int empty;

-    } fmt_43_rte;
+    } fmt_45_rte;

     struct { /* e.g. seth $dr,#$hi16 */
       UINT f_r1;
       UHI f_hi16;
     struct { /* e.g. seth $dr,#$hi16 */
       UINT f_r1;
       UHI f_hi16;

-    } fmt_44_seth;
+    } fmt_46_seth;

     struct { /* e.g. slli $dr,#$uimm5 */
       UINT f_r1;
       USI f_uimm5;
     struct { /* e.g. slli $dr,#$uimm5 */
       UINT f_r1;
       USI f_uimm5;

-    } fmt_45_slli;
+    } fmt_47_slli;

     struct { /* e.g. st $src1,@($slo16,$src2) */
       UINT f_r1;
       UINT f_r2;
       HI f_simm16;
     struct { /* e.g. st $src1,@($slo16,$src2) */
       UINT f_r1;
       UINT f_r2;
       HI f_simm16;

-    } fmt_46_st_d;
+    } fmt_48_st_d;

     struct { /* e.g. trap #$uimm4 */
       USI f_uimm4;
     struct { /* e.g. trap #$uimm4 */
       USI f_uimm4;

-    } fmt_47_trap;
+    } fmt_49_trap;

     struct { /* e.g. satb $dr,$src2 */
       UINT f_r1;
       UINT f_r2;
     struct { /* e.g. satb $dr,$src2 */
       UINT f_r1;
       UINT f_r2;

-    } fmt_48_satb;
+    } fmt_50_satb;

     struct { /* e.g. sat $dr,$src2 */
       UINT f_r1;
       UINT f_r2;
     struct { /* e.g. sat $dr,$src2 */
       UINT f_r1;
       UINT f_r2;

-    } fmt_49_sat;
+    } fmt_51_sat;

     struct { /* e.g. sadd */
       int empty;
     struct { /* e.g. sadd */
       int empty;

-    } fmt_50_sadd;
+    } fmt_52_sadd;

     struct { /* e.g. macwu1 $src1,$src2 */
       UINT f_r1;
       UINT f_r2;
     struct { /* e.g. macwu1 $src1,$src2 */
       UINT f_r1;
       UINT f_r2;

-    } fmt_51_macwu1;
+    } fmt_53_macwu1;

     struct { /* e.g. msblo $src1,$src2 */
       UINT f_r1;
       UINT f_r2;
     struct { /* e.g. msblo $src1,$src2 */
       UINT f_r1;
       UINT f_r2;

-    } fmt_52_msblo;
+    } fmt_54_msblo;

     struct { /* e.g. sc */
       int empty;
     struct { /* e.g. sc */
       int empty;

-    } fmt_53_sc;
+    } fmt_55_sc;

   } fields;
 #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
   unsigned long h_gr_get;
   } fields;
 #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
   unsigned long h_gr_get;


@@ -962,37 +971,81 @@ struct scache {
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 

-#define EXTRACT_FMT_42_RAC_A_VARS \
+#define EXTRACT_FMT_42_RAC_D_VARS \

   /* Instruction fields.  */ \
   UINT f_op1; \
   /* Instruction fields.  */ \
   UINT f_op1; \

-  UINT f_r1; \
+  UINT f_accd; \
+  UINT f_bits67; \

   UINT f_op2; \
   UINT f_accs; \
   UINT f_op2; \
   UINT f_accs; \

-  UINT f_op3; \
+  UINT f_bit14; \
+  UINT f_imm1; \

   unsigned int length;
   unsigned int length;

-#define EXTRACT_FMT_42_RAC_A_CODE \
+#define EXTRACT_FMT_42_RAC_D_CODE \

   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \

-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
+  f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \

   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \

-  f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
+  f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
+  f_imm1 = EXTRACT_UNSIGNED (insn, 16, 15, 1); \

 
 

-#define EXTRACT_FMT_43_RTE_VARS \
+#define EXTRACT_FMT_43_RAC_DS_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_accd; \
+  UINT f_bits67; \
+  UINT f_op2; \
+  UINT f_accs; \
+  UINT f_bit14; \
+  UINT f_imm1; \
+  unsigned int length;
+#define EXTRACT_FMT_43_RAC_DS_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
+  f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
+  f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
+  f_imm1 = EXTRACT_UNSIGNED (insn, 16, 15, 1); \
+
+#define EXTRACT_FMT_44_RAC_DSI_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_accd; \
+  UINT f_bits67; \
+  UINT f_op2; \
+  UINT f_accs; \
+  UINT f_bit14; \
+  UINT f_imm1; \
+  unsigned int length;
+#define EXTRACT_FMT_44_RAC_DSI_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
+  f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
+  f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
+  f_imm1 = EXTRACT_UNSIGNED (insn, 16, 15, 1); \
+
+#define EXTRACT_FMT_45_RTE_VARS \

   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;

-#define EXTRACT_FMT_43_RTE_CODE \
+#define EXTRACT_FMT_45_RTE_CODE \

   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 

-#define EXTRACT_FMT_44_SETH_VARS \
+#define EXTRACT_FMT_46_SETH_VARS \

   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \


@@ -1000,7 +1053,7 @@ struct scache {
   UINT f_r2; \
   UINT f_hi16; \
   unsigned int length;
   UINT f_r2; \
   UINT f_hi16; \
   unsigned int length;

-#define EXTRACT_FMT_44_SETH_CODE \
+#define EXTRACT_FMT_46_SETH_CODE \

   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \


@@ -1008,21 +1061,21 @@ struct scache {
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 

-#define EXTRACT_FMT_45_SLLI_VARS \
+#define EXTRACT_FMT_47_SLLI_VARS \

   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_shift_op2; \
   UINT f_uimm5; \
   unsigned int length;
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_shift_op2; \
   UINT f_uimm5; \
   unsigned int length;

-#define EXTRACT_FMT_45_SLLI_CODE \
+#define EXTRACT_FMT_47_SLLI_CODE \

   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
   f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
 
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
   f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
 

-#define EXTRACT_FMT_46_ST_D_VARS \
+#define EXTRACT_FMT_48_ST_D_VARS \

   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \


@@ -1030,7 +1083,7 @@ struct scache {
   UINT f_r2; \
   int f_simm16; \
   unsigned int length;
   UINT f_r2; \
   int f_simm16; \
   unsigned int length;

-#define EXTRACT_FMT_46_ST_D_CODE \
+#define EXTRACT_FMT_48_ST_D_CODE \

   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \


@@ -1038,21 +1091,21 @@ struct scache {
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 

-#define EXTRACT_FMT_47_TRAP_VARS \
+#define EXTRACT_FMT_49_TRAP_VARS \

   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_uimm4; \
   unsigned int length;
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_uimm4; \
   unsigned int length;

-#define EXTRACT_FMT_47_TRAP_CODE \
+#define EXTRACT_FMT_49_TRAP_CODE \

   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 

-#define EXTRACT_FMT_48_SATB_VARS \
+#define EXTRACT_FMT_50_SATB_VARS \

   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \


@@ -1060,7 +1113,7 @@ struct scache {
   UINT f_r2; \
   UINT f_uimm16; \
   unsigned int length;
   UINT f_r2; \
   UINT f_uimm16; \
   unsigned int length;

-#define EXTRACT_FMT_48_SATB_CODE \
+#define EXTRACT_FMT_50_SATB_CODE \

   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \


@@ -1068,7 +1121,7 @@ struct scache {
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 

-#define EXTRACT_FMT_49_SAT_VARS \
+#define EXTRACT_FMT_51_SAT_VARS \

   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \


@@ -1076,7 +1129,7 @@ struct scache {
   UINT f_r2; \
   UINT f_uimm16; \
   unsigned int length;
   UINT f_r2; \
   UINT f_uimm16; \
   unsigned int length;

-#define EXTRACT_FMT_49_SAT_CODE \
+#define EXTRACT_FMT_51_SAT_CODE \

   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \


@@ -1084,56 +1137,56 @@ struct scache {
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 

-#define EXTRACT_FMT_50_SADD_VARS \
+#define EXTRACT_FMT_52_SADD_VARS \

   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;

-#define EXTRACT_FMT_50_SADD_CODE \
+#define EXTRACT_FMT_52_SADD_CODE \

   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 

-#define EXTRACT_FMT_51_MACWU1_VARS \
+#define EXTRACT_FMT_53_MACWU1_VARS \

   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;

-#define EXTRACT_FMT_51_MACWU1_CODE \
+#define EXTRACT_FMT_53_MACWU1_CODE \

   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 

-#define EXTRACT_FMT_52_MSBLO_VARS \
+#define EXTRACT_FMT_54_MSBLO_VARS \

   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;

-#define EXTRACT_FMT_52_MSBLO_CODE \
+#define EXTRACT_FMT_54_MSBLO_CODE \

   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 

-#define EXTRACT_FMT_53_SC_VARS \
+#define EXTRACT_FMT_55_SC_VARS \

   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;

-#define EXTRACT_FMT_53_SC_CODE \
+#define EXTRACT_FMT_55_SC_CODE \

   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \


@@ -1142,7 +1195,7 @@ struct scache {
 
 /* Fetched input values of an instruction.  */
 
 
 /* Fetched input values of an instruction.  */
 

-struct parallel_exec {
+struct parexec {

   union {
     struct { /* e.g. add $dr,$sr */
       SI dr;
   union {
     struct { /* e.g. add $dr,$sr */
       SI dr;


@@ -1308,54 +1361,61 @@ struct parallel_exec {
     struct { /* e.g. nop */
       int empty;
     } fmt_41_nop;
     struct { /* e.g. nop */
       int empty;
     } fmt_41_nop;

-    struct { /* e.g. rac $accs */
+    struct { /* e.g. rac $accd */
+      DI accum;
+    } fmt_42_rac_d;
+    struct { /* e.g. rac $accd,$accs */
+      DI accs;
+    } fmt_43_rac_ds;
+    struct { /* e.g. rac $accd,$accs,#$imm1 */

       DI accs;
       DI accs;

-    } fmt_42_rac_a;
+      USI imm1;
+    } fmt_44_rac_dsi;

     struct { /* e.g. rte */
       UBI h_bcond_0;
       UBI h_bie_0;
       SI h_bpc_0;
       UBI h_bsm_0;
     struct { /* e.g. rte */
       UBI h_bcond_0;
       UBI h_bie_0;
       SI h_bpc_0;
       UBI h_bsm_0;

-    } fmt_43_rte;
+    } fmt_45_rte;

     struct { /* e.g. seth $dr,#$hi16 */
       UHI hi16;
     struct { /* e.g. seth $dr,#$hi16 */
       UHI hi16;

-    } fmt_44_seth;
+    } fmt_46_seth;

     struct { /* e.g. slli $dr,#$uimm5 */
       SI dr;
       USI uimm5;
     struct { /* e.g. slli $dr,#$uimm5 */
       SI dr;
       USI uimm5;

-    } fmt_45_slli;
+    } fmt_47_slli;

     struct { /* e.g. st $src1,@($slo16,$src2) */
       HI slo16;
       SI src1;
       SI src2;
     struct { /* e.g. st $src1,@($slo16,$src2) */
       HI slo16;
       SI src1;
       SI src2;

-    } fmt_46_st_d;
+    } fmt_48_st_d;

     struct { /* e.g. trap #$uimm4 */
       USI uimm4;
     struct { /* e.g. trap #$uimm4 */
       USI uimm4;

-    } fmt_47_trap;
+    } fmt_49_trap;

     struct { /* e.g. satb $dr,$src2 */
       SI src2;
     struct { /* e.g. satb $dr,$src2 */
       SI src2;

-    } fmt_48_satb;
+    } fmt_50_satb;

     struct { /* e.g. sat $dr,$src2 */
       UBI condbit;
       SI src2;
     struct { /* e.g. sat $dr,$src2 */
       UBI condbit;
       SI src2;

-    } fmt_49_sat;
+    } fmt_51_sat;

     struct { /* e.g. sadd */
       DI h_accums_0;
       DI h_accums_1;
     struct { /* e.g. sadd */
       DI h_accums_0;
       DI h_accums_1;

-    } fmt_50_sadd;
+    } fmt_52_sadd;

     struct { /* e.g. macwu1 $src1,$src2 */
       DI h_accums_1;
       SI src1;
       SI src2;
     struct { /* e.g. macwu1 $src1,$src2 */
       DI h_accums_1;
       SI src1;
       SI src2;

-    } fmt_51_macwu1;
+    } fmt_53_macwu1;

     struct { /* e.g. msblo $src1,$src2 */
       DI accum;
       SI src1;
       SI src2;
     struct { /* e.g. msblo $src1,$src2 */
       DI accum;
       SI src1;
       SI src2;

-    } fmt_52_msblo;
+    } fmt_54_msblo;

     struct { /* e.g. sc */
       UBI condbit;
     struct { /* e.g. sc */
       UBI condbit;

-    } fmt_53_sc;
+    } fmt_55_sc;

   } operands;
 };
 
   } operands;
 };
 

diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c
index a779786..a474d0a 100644 (file)
--- a/sim/m32r/decode.c
+++ b/sim/m32r/decode.c
@@ -40,6 +40,14 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define EX(fn) 0
 #endif
 
 #define EX(fn) 0
 #endif
 

+#ifdef HAVE_PARALLEL_EXEC
+#ifdef __GNUC__
+#define READ(n) 0
+#else
+#define READ(n) XCONCAT3 (READ,_,n)
+#endif
+#endif
+

 #if WITH_SEM_SWITCH_FULL
 #define FULL(fn) 0
 #else
 #if WITH_SEM_SWITCH_FULL
 #define FULL(fn) 0
 #else


@@ -62,112 +70,115 @@ with this program; if not, write to the Free Software Foundation, Inc.,
    prepend m32r_, so simplify things by handling it here.  */
 #define decode_illegal m32r_decode_illegal
 
    prepend m32r_, so simplify things by handling it here.  */
 #define decode_illegal m32r_decode_illegal
 

-static DECODE decode_add = { M32R_INSN_ADD, & m32r_cgen_insn_table_entries[M32R_INSN_ADD], EX (fmt_0_add), FULL (add), FAST (add) };
-static DECODE decode_add3 = { M32R_INSN_ADD3, & m32r_cgen_insn_table_entries[M32R_INSN_ADD3], EX (fmt_1_add3), FULL (add3), FAST (add3) };
-static DECODE decode_and = { M32R_INSN_AND, & m32r_cgen_insn_table_entries[M32R_INSN_AND], EX (fmt_0_add), FULL (and), FAST (and) };
-static DECODE decode_and3 = { M32R_INSN_AND3, & m32r_cgen_insn_table_entries[M32R_INSN_AND3], EX (fmt_2_and3), FULL (and3), FAST (and3) };
-static DECODE decode_or = { M32R_INSN_OR, & m32r_cgen_insn_table_entries[M32R_INSN_OR], EX (fmt_0_add), FULL (or), FAST (or) };
-static DECODE decode_or3 = { M32R_INSN_OR3, & m32r_cgen_insn_table_entries[M32R_INSN_OR3], EX (fmt_3_or3), FULL (or3), FAST (or3) };
-static DECODE decode_xor = { M32R_INSN_XOR, & m32r_cgen_insn_table_entries[M32R_INSN_XOR], EX (fmt_0_add), FULL (xor), FAST (xor) };
-static DECODE decode_xor3 = { M32R_INSN_XOR3, & m32r_cgen_insn_table_entries[M32R_INSN_XOR3], EX (fmt_2_and3), FULL (xor3), FAST (xor3) };
-static DECODE decode_addi = { M32R_INSN_ADDI, & m32r_cgen_insn_table_entries[M32R_INSN_ADDI], EX (fmt_4_addi), FULL (addi), FAST (addi) };
-static DECODE decode_addv = { M32R_INSN_ADDV, & m32r_cgen_insn_table_entries[M32R_INSN_ADDV], EX (fmt_0_add), FULL (addv), FAST (addv) };
-static DECODE decode_addv3 = { M32R_INSN_ADDV3, & m32r_cgen_insn_table_entries[M32R_INSN_ADDV3], EX (fmt_5_addv3), FULL (addv3), FAST (addv3) };
-static DECODE decode_addx = { M32R_INSN_ADDX, & m32r_cgen_insn_table_entries[M32R_INSN_ADDX], EX (fmt_6_addx), FULL (addx), FAST (addx) };
-static DECODE decode_bc8 = { M32R_INSN_BC8, & m32r_cgen_insn_table_entries[M32R_INSN_BC8], EX (fmt_7_bc8), FULL (bc8), FAST (bc8) };
-static DECODE decode_bc24 = { M32R_INSN_BC24, & m32r_cgen_insn_table_entries[M32R_INSN_BC24], EX (fmt_8_bc24), FULL (bc24), FAST (bc24) };
-static DECODE decode_beq = { M32R_INSN_BEQ, & m32r_cgen_insn_table_entries[M32R_INSN_BEQ], EX (fmt_9_beq), FULL (beq), FAST (beq) };
-static DECODE decode_beqz = { M32R_INSN_BEQZ, & m32r_cgen_insn_table_entries[M32R_INSN_BEQZ], EX (fmt_10_beqz), FULL (beqz), FAST (beqz) };
-static DECODE decode_bgez = { M32R_INSN_BGEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BGEZ], EX (fmt_10_beqz), FULL (bgez), FAST (bgez) };
-static DECODE decode_bgtz = { M32R_INSN_BGTZ, & m32r_cgen_insn_table_entries[M32R_INSN_BGTZ], EX (fmt_10_beqz), FULL (bgtz), FAST (bgtz) };
-static DECODE decode_blez = { M32R_INSN_BLEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BLEZ], EX (fmt_10_beqz), FULL (blez), FAST (blez) };
-static DECODE decode_bltz = { M32R_INSN_BLTZ, & m32r_cgen_insn_table_entries[M32R_INSN_BLTZ], EX (fmt_10_beqz), FULL (bltz), FAST (bltz) };
-static DECODE decode_bnez = { M32R_INSN_BNEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BNEZ], EX (fmt_10_beqz), FULL (bnez), FAST (bnez) };
-static DECODE decode_bl8 = { M32R_INSN_BL8, & m32r_cgen_insn_table_entries[M32R_INSN_BL8], EX (fmt_11_bl8), FULL (bl8), FAST (bl8) };
-static DECODE decode_bl24 = { M32R_INSN_BL24, & m32r_cgen_insn_table_entries[M32R_INSN_BL24], EX (fmt_12_bl24), FULL (bl24), FAST (bl24) };
-static DECODE decode_bnc8 = { M32R_INSN_BNC8, & m32r_cgen_insn_table_entries[M32R_INSN_BNC8], EX (fmt_7_bc8), FULL (bnc8), FAST (bnc8) };
-static DECODE decode_bnc24 = { M32R_INSN_BNC24, & m32r_cgen_insn_table_entries[M32R_INSN_BNC24], EX (fmt_8_bc24), FULL (bnc24), FAST (bnc24) };
-static DECODE decode_bne = { M32R_INSN_BNE, & m32r_cgen_insn_table_entries[M32R_INSN_BNE], EX (fmt_9_beq), FULL (bne), FAST (bne) };
-static DECODE decode_bra8 = { M32R_INSN_BRA8, & m32r_cgen_insn_table_entries[M32R_INSN_BRA8], EX (fmt_13_bra8), FULL (bra8), FAST (bra8) };
-static DECODE decode_bra24 = { M32R_INSN_BRA24, & m32r_cgen_insn_table_entries[M32R_INSN_BRA24], EX (fmt_14_bra24), FULL (bra24), FAST (bra24) };
-static DECODE decode_cmp = { M32R_INSN_CMP, & m32r_cgen_insn_table_entries[M32R_INSN_CMP], EX (fmt_15_cmp), FULL (cmp), FAST (cmp) };
-static DECODE decode_cmpi = { M32R_INSN_CMPI, & m32r_cgen_insn_table_entries[M32R_INSN_CMPI], EX (fmt_16_cmpi), FULL (cmpi), FAST (cmpi) };
-static DECODE decode_cmpu = { M32R_INSN_CMPU, & m32r_cgen_insn_table_entries[M32R_INSN_CMPU], EX (fmt_15_cmp), FULL (cmpu), FAST (cmpu) };
-static DECODE decode_cmpui = { M32R_INSN_CMPUI, & m32r_cgen_insn_table_entries[M32R_INSN_CMPUI], EX (fmt_17_cmpui), FULL (cmpui), FAST (cmpui) };
-static DECODE decode_div = { M32R_INSN_DIV, & m32r_cgen_insn_table_entries[M32R_INSN_DIV], EX (fmt_18_div), FULL (div), FAST (div) };
-static DECODE decode_divu = { M32R_INSN_DIVU, & m32r_cgen_insn_table_entries[M32R_INSN_DIVU], EX (fmt_18_div), FULL (divu), FAST (divu) };
-static DECODE decode_rem = { M32R_INSN_REM, & m32r_cgen_insn_table_entries[M32R_INSN_REM], EX (fmt_18_div), FULL (rem), FAST (rem) };
-static DECODE decode_remu = { M32R_INSN_REMU, & m32r_cgen_insn_table_entries[M32R_INSN_REMU], EX (fmt_18_div), FULL (remu), FAST (remu) };
-static DECODE decode_jl = { M32R_INSN_JL, & m32r_cgen_insn_table_entries[M32R_INSN_JL], EX (fmt_19_jl), FULL (jl), FAST (jl) };
-static DECODE decode_jmp = { M32R_INSN_JMP, & m32r_cgen_insn_table_entries[M32R_INSN_JMP], EX (fmt_20_jmp), FULL (jmp), FAST (jmp) };
-static DECODE decode_ld = { M32R_INSN_LD, & m32r_cgen_insn_table_entries[M32R_INSN_LD], EX (fmt_21_ld), FULL (ld), FAST (ld) };
-static DECODE decode_ld_d = { M32R_INSN_LD_D, & m32r_cgen_insn_table_entries[M32R_INSN_LD_D], EX (fmt_22_ld_d), FULL (ld_d), FAST (ld_d) };
-static DECODE decode_ldb = { M32R_INSN_LDB, & m32r_cgen_insn_table_entries[M32R_INSN_LDB], EX (fmt_23_ldb), FULL (ldb), FAST (ldb) };
-static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDB_D], EX (fmt_24_ldb_d), FULL (ldb_d), FAST (ldb_d) };
-static DECODE decode_ldh = { M32R_INSN_LDH, & m32r_cgen_insn_table_entries[M32R_INSN_LDH], EX (fmt_25_ldh), FULL (ldh), FAST (ldh) };
-static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDH_D], EX (fmt_26_ldh_d), FULL (ldh_d), FAST (ldh_d) };
-static DECODE decode_ldub = { M32R_INSN_LDUB, & m32r_cgen_insn_table_entries[M32R_INSN_LDUB], EX (fmt_23_ldb), FULL (ldub), FAST (ldub) };
-static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDUB_D], EX (fmt_24_ldb_d), FULL (ldub_d), FAST (ldub_d) };
-static DECODE decode_lduh = { M32R_INSN_LDUH, & m32r_cgen_insn_table_entries[M32R_INSN_LDUH], EX (fmt_25_ldh), FULL (lduh), FAST (lduh) };
-static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDUH_D], EX (fmt_26_ldh_d), FULL (lduh_d), FAST (lduh_d) };
-static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & m32r_cgen_insn_table_entries[M32R_INSN_LD_PLUS], EX (fmt_21_ld), FULL (ld_plus), FAST (ld_plus) };
-static DECODE decode_ld24 = { M32R_INSN_LD24, & m32r_cgen_insn_table_entries[M32R_INSN_LD24], EX (fmt_27_ld24), FULL (ld24), FAST (ld24) };
-static DECODE decode_ldi8 = { M32R_INSN_LDI8, & m32r_cgen_insn_table_entries[M32R_INSN_LDI8], EX (fmt_28_ldi8), FULL (ldi8), FAST (ldi8) };
-static DECODE decode_ldi16 = { M32R_INSN_LDI16, & m32r_cgen_insn_table_entries[M32R_INSN_LDI16], EX (fmt_29_ldi16), FULL (ldi16), FAST (ldi16) };
-static DECODE decode_lock = { M32R_INSN_LOCK, & m32r_cgen_insn_table_entries[M32R_INSN_LOCK], EX (fmt_0_add), FULL (lock), FAST (lock) };
-static DECODE decode_machi = { M32R_INSN_MACHI, & m32r_cgen_insn_table_entries[M32R_INSN_MACHI], EX (fmt_30_machi), FULL (machi), FAST (machi) };
-static DECODE decode_maclo = { M32R_INSN_MACLO, & m32r_cgen_insn_table_entries[M32R_INSN_MACLO], EX (fmt_30_machi), FULL (maclo), FAST (maclo) };
-static DECODE decode_macwhi = { M32R_INSN_MACWHI, & m32r_cgen_insn_table_entries[M32R_INSN_MACWHI], EX (fmt_30_machi), FULL (macwhi), FAST (macwhi) };
-static DECODE decode_macwlo = { M32R_INSN_MACWLO, & m32r_cgen_insn_table_entries[M32R_INSN_MACWLO], EX (fmt_30_machi), FULL (macwlo), FAST (macwlo) };
-static DECODE decode_mul = { M32R_INSN_MUL, & m32r_cgen_insn_table_entries[M32R_INSN_MUL], EX (fmt_0_add), FULL (mul), FAST (mul) };
-static DECODE decode_mulhi = { M32R_INSN_MULHI, & m32r_cgen_insn_table_entries[M32R_INSN_MULHI], EX (fmt_15_cmp), FULL (mulhi), FAST (mulhi) };
-static DECODE decode_mullo = { M32R_INSN_MULLO, & m32r_cgen_insn_table_entries[M32R_INSN_MULLO], EX (fmt_15_cmp), FULL (mullo), FAST (mullo) };
-static DECODE decode_mulwhi = { M32R_INSN_MULWHI, & m32r_cgen_insn_table_entries[M32R_INSN_MULWHI], EX (fmt_15_cmp), FULL (mulwhi), FAST (mulwhi) };
-static DECODE decode_mulwlo = { M32R_INSN_MULWLO, & m32r_cgen_insn_table_entries[M32R_INSN_MULWLO], EX (fmt_15_cmp), FULL (mulwlo), FAST (mulwlo) };
-static DECODE decode_mv = { M32R_INSN_MV, & m32r_cgen_insn_table_entries[M32R_INSN_MV], EX (fmt_31_mv), FULL (mv), FAST (mv) };
-static DECODE decode_mvfachi = { M32R_INSN_MVFACHI, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACHI], EX (fmt_32_mvfachi), FULL (mvfachi), FAST (mvfachi) };
-static DECODE decode_mvfaclo = { M32R_INSN_MVFACLO, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACLO], EX (fmt_32_mvfachi), FULL (mvfaclo), FAST (mvfaclo) };
-static DECODE decode_mvfacmi = { M32R_INSN_MVFACMI, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACMI], EX (fmt_32_mvfachi), FULL (mvfacmi), FAST (mvfacmi) };
-static DECODE decode_mvfc = { M32R_INSN_MVFC, & m32r_cgen_insn_table_entries[M32R_INSN_MVFC], EX (fmt_33_mvfc), FULL (mvfc), FAST (mvfc) };
-static DECODE decode_mvtachi = { M32R_INSN_MVTACHI, & m32r_cgen_insn_table_entries[M32R_INSN_MVTACHI], EX (fmt_34_mvtachi), FULL (mvtachi), FAST (mvtachi) };
-static DECODE decode_mvtaclo = { M32R_INSN_MVTACLO, & m32r_cgen_insn_table_entries[M32R_INSN_MVTACLO], EX (fmt_34_mvtachi), FULL (mvtaclo), FAST (mvtaclo) };
-static DECODE decode_mvtc = { M32R_INSN_MVTC, & m32r_cgen_insn_table_entries[M32R_INSN_MVTC], EX (fmt_35_mvtc), FULL (mvtc), FAST (mvtc) };
-static DECODE decode_neg = { M32R_INSN_NEG, & m32r_cgen_insn_table_entries[M32R_INSN_NEG], EX (fmt_31_mv), FULL (neg), FAST (neg) };
-static DECODE decode_nop = { M32R_INSN_NOP, & m32r_cgen_insn_table_entries[M32R_INSN_NOP], EX (fmt_36_nop), FULL (nop), FAST (nop) };
-static DECODE decode_not = { M32R_INSN_NOT, & m32r_cgen_insn_table_entries[M32R_INSN_NOT], EX (fmt_31_mv), FULL (not), FAST (not) };
-static DECODE decode_rac = { M32R_INSN_RAC, & m32r_cgen_insn_table_entries[M32R_INSN_RAC], EX (fmt_37_rac), FULL (rac), FAST (rac) };
-static DECODE decode_rach = { M32R_INSN_RACH, & m32r_cgen_insn_table_entries[M32R_INSN_RACH], EX (fmt_37_rac), FULL (rach), FAST (rach) };
-static DECODE decode_rte = { M32R_INSN_RTE, & m32r_cgen_insn_table_entries[M32R_INSN_RTE], EX (fmt_38_rte), FULL (rte), FAST (rte) };
-static DECODE decode_seth = { M32R_INSN_SETH, & m32r_cgen_insn_table_entries[M32R_INSN_SETH], EX (fmt_39_seth), FULL (seth), FAST (seth) };
-static DECODE decode_sll = { M32R_INSN_SLL, & m32r_cgen_insn_table_entries[M32R_INSN_SLL], EX (fmt_0_add), FULL (sll), FAST (sll) };
-static DECODE decode_sll3 = { M32R_INSN_SLL3, & m32r_cgen_insn_table_entries[M32R_INSN_SLL3], EX (fmt_5_addv3), FULL (sll3), FAST (sll3) };
-static DECODE decode_slli = { M32R_INSN_SLLI, & m32r_cgen_insn_table_entries[M32R_INSN_SLLI], EX (fmt_40_slli), FULL (slli), FAST (slli) };
-static DECODE decode_sra = { M32R_INSN_SRA, & m32r_cgen_insn_table_entries[M32R_INSN_SRA], EX (fmt_0_add), FULL (sra), FAST (sra) };
-static DECODE decode_sra3 = { M32R_INSN_SRA3, & m32r_cgen_insn_table_entries[M32R_INSN_SRA3], EX (fmt_5_addv3), FULL (sra3), FAST (sra3) };
-static DECODE decode_srai = { M32R_INSN_SRAI, & m32r_cgen_insn_table_entries[M32R_INSN_SRAI], EX (fmt_40_slli), FULL (srai), FAST (srai) };
-static DECODE decode_srl = { M32R_INSN_SRL, & m32r_cgen_insn_table_entries[M32R_INSN_SRL], EX (fmt_0_add), FULL (srl), FAST (srl) };
-static DECODE decode_srl3 = { M32R_INSN_SRL3, & m32r_cgen_insn_table_entries[M32R_INSN_SRL3], EX (fmt_5_addv3), FULL (srl3), FAST (srl3) };
-static DECODE decode_srli = { M32R_INSN_SRLI, & m32r_cgen_insn_table_entries[M32R_INSN_SRLI], EX (fmt_40_slli), FULL (srli), FAST (srli) };
-static DECODE decode_st = { M32R_INSN_ST, & m32r_cgen_insn_table_entries[M32R_INSN_ST], EX (fmt_15_cmp), FULL (st), FAST (st) };
-static DECODE decode_st_d = { M32R_INSN_ST_D, & m32r_cgen_insn_table_entries[M32R_INSN_ST_D], EX (fmt_41_st_d), FULL (st_d), FAST (st_d) };
-static DECODE decode_stb = { M32R_INSN_STB, & m32r_cgen_insn_table_entries[M32R_INSN_STB], EX (fmt_15_cmp), FULL (stb), FAST (stb) };
-static DECODE decode_stb_d = { M32R_INSN_STB_D, & m32r_cgen_insn_table_entries[M32R_INSN_STB_D], EX (fmt_41_st_d), FULL (stb_d), FAST (stb_d) };
-static DECODE decode_sth = { M32R_INSN_STH, & m32r_cgen_insn_table_entries[M32R_INSN_STH], EX (fmt_15_cmp), FULL (sth), FAST (sth) };
-static DECODE decode_sth_d = { M32R_INSN_STH_D, & m32r_cgen_insn_table_entries[M32R_INSN_STH_D], EX (fmt_41_st_d), FULL (sth_d), FAST (sth_d) };
-static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & m32r_cgen_insn_table_entries[M32R_INSN_ST_PLUS], EX (fmt_15_cmp), FULL (st_plus), FAST (st_plus) };
-static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & m32r_cgen_insn_table_entries[M32R_INSN_ST_MINUS], EX (fmt_15_cmp), FULL (st_minus), FAST (st_minus) };
-static DECODE decode_sub = { M32R_INSN_SUB, & m32r_cgen_insn_table_entries[M32R_INSN_SUB], EX (fmt_0_add), FULL (sub), FAST (sub) };
-static DECODE decode_subv = { M32R_INSN_SUBV, & m32r_cgen_insn_table_entries[M32R_INSN_SUBV], EX (fmt_0_add), FULL (subv), FAST (subv) };
-static DECODE decode_subx = { M32R_INSN_SUBX, & m32r_cgen_insn_table_entries[M32R_INSN_SUBX], EX (fmt_6_addx), FULL (subx), FAST (subx) };
-static DECODE decode_trap = { M32R_INSN_TRAP, & m32r_cgen_insn_table_entries[M32R_INSN_TRAP], EX (fmt_42_trap), FULL (trap), FAST (trap) };
-static DECODE decode_unlock = { M32R_INSN_UNLOCK, & m32r_cgen_insn_table_entries[M32R_INSN_UNLOCK], EX (fmt_15_cmp), FULL (unlock), FAST (unlock) };
+#define ITAB(n) m32r_cgen_insn_table_entries[n]
+
+static DECODE decode_add = { M32R_INSN_ADD, & ITAB (M32R_INSN_ADD), EX (fmt_0_add), FULL (add), FAST (add) };
+static DECODE decode_add3 = { M32R_INSN_ADD3, & ITAB (M32R_INSN_ADD3), EX (fmt_1_add3), FULL (add3), FAST (add3) };
+static DECODE decode_and = { M32R_INSN_AND, & ITAB (M32R_INSN_AND), EX (fmt_0_add), FULL (and), FAST (and) };
+static DECODE decode_and3 = { M32R_INSN_AND3, & ITAB (M32R_INSN_AND3), EX (fmt_2_and3), FULL (and3), FAST (and3) };
+static DECODE decode_or = { M32R_INSN_OR, & ITAB (M32R_INSN_OR), EX (fmt_0_add), FULL (or), FAST (or) };
+static DECODE decode_or3 = { M32R_INSN_OR3, & ITAB (M32R_INSN_OR3), EX (fmt_3_or3), FULL (or3), FAST (or3) };
+static DECODE decode_xor = { M32R_INSN_XOR, & ITAB (M32R_INSN_XOR), EX (fmt_0_add), FULL (xor), FAST (xor) };
+static DECODE decode_xor3 = { M32R_INSN_XOR3, & ITAB (M32R_INSN_XOR3), EX (fmt_2_and3), FULL (xor3), FAST (xor3) };
+static DECODE decode_addi = { M32R_INSN_ADDI, & ITAB (M32R_INSN_ADDI), EX (fmt_4_addi), FULL (addi), FAST (addi) };
+static DECODE decode_addv = { M32R_INSN_ADDV, & ITAB (M32R_INSN_ADDV), EX (fmt_0_add), FULL (addv), FAST (addv) };
+static DECODE decode_addv3 = { M32R_INSN_ADDV3, & ITAB (M32R_INSN_ADDV3), EX (fmt_5_addv3), FULL (addv3), FAST (addv3) };
+static DECODE decode_addx = { M32R_INSN_ADDX, & ITAB (M32R_INSN_ADDX), EX (fmt_6_addx), FULL (addx), FAST (addx) };
+static DECODE decode_bc8 = { M32R_INSN_BC8, & ITAB (M32R_INSN_BC8), EX (fmt_7_bc8), FULL (bc8), FAST (bc8) };
+static DECODE decode_bc24 = { M32R_INSN_BC24, & ITAB (M32R_INSN_BC24), EX (fmt_8_bc24), FULL (bc24), FAST (bc24) };
+static DECODE decode_beq = { M32R_INSN_BEQ, & ITAB (M32R_INSN_BEQ), EX (fmt_9_beq), FULL (beq), FAST (beq) };
+static DECODE decode_beqz = { M32R_INSN_BEQZ, & ITAB (M32R_INSN_BEQZ), EX (fmt_10_beqz), FULL (beqz), FAST (beqz) };
+static DECODE decode_bgez = { M32R_INSN_BGEZ, & ITAB (M32R_INSN_BGEZ), EX (fmt_10_beqz), FULL (bgez), FAST (bgez) };
+static DECODE decode_bgtz = { M32R_INSN_BGTZ, & ITAB (M32R_INSN_BGTZ), EX (fmt_10_beqz), FULL (bgtz), FAST (bgtz) };
+static DECODE decode_blez = { M32R_INSN_BLEZ, & ITAB (M32R_INSN_BLEZ), EX (fmt_10_beqz), FULL (blez), FAST (blez) };
+static DECODE decode_bltz = { M32R_INSN_BLTZ, & ITAB (M32R_INSN_BLTZ), EX (fmt_10_beqz), FULL (bltz), FAST (bltz) };
+static DECODE decode_bnez = { M32R_INSN_BNEZ, & ITAB (M32R_INSN_BNEZ), EX (fmt_10_beqz), FULL (bnez), FAST (bnez) };
+static DECODE decode_bl8 = { M32R_INSN_BL8, & ITAB (M32R_INSN_BL8), EX (fmt_11_bl8), FULL (bl8), FAST (bl8) };
+static DECODE decode_bl24 = { M32R_INSN_BL24, & ITAB (M32R_INSN_BL24), EX (fmt_12_bl24), FULL (bl24), FAST (bl24) };
+static DECODE decode_bnc8 = { M32R_INSN_BNC8, & ITAB (M32R_INSN_BNC8), EX (fmt_7_bc8), FULL (bnc8), FAST (bnc8) };
+static DECODE decode_bnc24 = { M32R_INSN_BNC24, & ITAB (M32R_INSN_BNC24), EX (fmt_8_bc24), FULL (bnc24), FAST (bnc24) };
+static DECODE decode_bne = { M32R_INSN_BNE, & ITAB (M32R_INSN_BNE), EX (fmt_9_beq), FULL (bne), FAST (bne) };
+static DECODE decode_bra8 = { M32R_INSN_BRA8, & ITAB (M32R_INSN_BRA8), EX (fmt_13_bra8), FULL (bra8), FAST (bra8) };
+static DECODE decode_bra24 = { M32R_INSN_BRA24, & ITAB (M32R_INSN_BRA24), EX (fmt_14_bra24), FULL (bra24), FAST (bra24) };
+static DECODE decode_cmp = { M32R_INSN_CMP, & ITAB (M32R_INSN_CMP), EX (fmt_15_cmp), FULL (cmp), FAST (cmp) };
+static DECODE decode_cmpi = { M32R_INSN_CMPI, & ITAB (M32R_INSN_CMPI), EX (fmt_16_cmpi), FULL (cmpi), FAST (cmpi) };
+static DECODE decode_cmpu = { M32R_INSN_CMPU, & ITAB (M32R_INSN_CMPU), EX (fmt_15_cmp), FULL (cmpu), FAST (cmpu) };
+static DECODE decode_cmpui = { M32R_INSN_CMPUI, & ITAB (M32R_INSN_CMPUI), EX (fmt_17_cmpui), FULL (cmpui), FAST (cmpui) };
+static DECODE decode_div = { M32R_INSN_DIV, & ITAB (M32R_INSN_DIV), EX (fmt_18_div), FULL (div), FAST (div) };
+static DECODE decode_divu = { M32R_INSN_DIVU, & ITAB (M32R_INSN_DIVU), EX (fmt_18_div), FULL (divu), FAST (divu) };
+static DECODE decode_rem = { M32R_INSN_REM, & ITAB (M32R_INSN_REM), EX (fmt_18_div), FULL (rem), FAST (rem) };
+static DECODE decode_remu = { M32R_INSN_REMU, & ITAB (M32R_INSN_REMU), EX (fmt_18_div), FULL (remu), FAST (remu) };
+static DECODE decode_divh = { M32R_INSN_DIVH, & ITAB (M32R_INSN_DIVH), EX (fmt_18_div), FULL (divh), FAST (divh) };
+static DECODE decode_jl = { M32R_INSN_JL, & ITAB (M32R_INSN_JL), EX (fmt_19_jl), FULL (jl), FAST (jl) };
+static DECODE decode_jmp = { M32R_INSN_JMP, & ITAB (M32R_INSN_JMP), EX (fmt_20_jmp), FULL (jmp), FAST (jmp) };
+static DECODE decode_ld = { M32R_INSN_LD, & ITAB (M32R_INSN_LD), EX (fmt_21_ld), FULL (ld), FAST (ld) };
+static DECODE decode_ld_d = { M32R_INSN_LD_D, & ITAB (M32R_INSN_LD_D), EX (fmt_22_ld_d), FULL (ld_d), FAST (ld_d) };
+static DECODE decode_ldb = { M32R_INSN_LDB, & ITAB (M32R_INSN_LDB), EX (fmt_23_ldb), FULL (ldb), FAST (ldb) };
+static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & ITAB (M32R_INSN_LDB_D), EX (fmt_24_ldb_d), FULL (ldb_d), FAST (ldb_d) };
+static DECODE decode_ldh = { M32R_INSN_LDH, & ITAB (M32R_INSN_LDH), EX (fmt_25_ldh), FULL (ldh), FAST (ldh) };
+static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & ITAB (M32R_INSN_LDH_D), EX (fmt_26_ldh_d), FULL (ldh_d), FAST (ldh_d) };
+static DECODE decode_ldub = { M32R_INSN_LDUB, & ITAB (M32R_INSN_LDUB), EX (fmt_23_ldb), FULL (ldub), FAST (ldub) };
+static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & ITAB (M32R_INSN_LDUB_D), EX (fmt_24_ldb_d), FULL (ldub_d), FAST (ldub_d) };
+static DECODE decode_lduh = { M32R_INSN_LDUH, & ITAB (M32R_INSN_LDUH), EX (fmt_25_ldh), FULL (lduh), FAST (lduh) };
+static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & ITAB (M32R_INSN_LDUH_D), EX (fmt_26_ldh_d), FULL (lduh_d), FAST (lduh_d) };
+static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & ITAB (M32R_INSN_LD_PLUS), EX (fmt_21_ld), FULL (ld_plus), FAST (ld_plus) };
+static DECODE decode_ld24 = { M32R_INSN_LD24, & ITAB (M32R_INSN_LD24), EX (fmt_27_ld24), FULL (ld24), FAST (ld24) };
+static DECODE decode_ldi8 = { M32R_INSN_LDI8, & ITAB (M32R_INSN_LDI8), EX (fmt_28_ldi8), FULL (ldi8), FAST (ldi8) };
+static DECODE decode_ldi16 = { M32R_INSN_LDI16, & ITAB (M32R_INSN_LDI16), EX (fmt_29_ldi16), FULL (ldi16), FAST (ldi16) };
+static DECODE decode_lock = { M32R_INSN_LOCK, & ITAB (M32R_INSN_LOCK), EX (fmt_0_add), FULL (lock), FAST (lock) };
+static DECODE decode_machi = { M32R_INSN_MACHI, & ITAB (M32R_INSN_MACHI), EX (fmt_30_machi), FULL (machi), FAST (machi) };
+static DECODE decode_maclo = { M32R_INSN_MACLO, & ITAB (M32R_INSN_MACLO), EX (fmt_30_machi), FULL (maclo), FAST (maclo) };
+static DECODE decode_macwhi = { M32R_INSN_MACWHI, & ITAB (M32R_INSN_MACWHI), EX (fmt_30_machi), FULL (macwhi), FAST (macwhi) };
+static DECODE decode_macwlo = { M32R_INSN_MACWLO, & ITAB (M32R_INSN_MACWLO), EX (fmt_30_machi), FULL (macwlo), FAST (macwlo) };
+static DECODE decode_mul = { M32R_INSN_MUL, & ITAB (M32R_INSN_MUL), EX (fmt_0_add), FULL (mul), FAST (mul) };
+static DECODE decode_mulhi = { M32R_INSN_MULHI, & ITAB (M32R_INSN_MULHI), EX (fmt_15_cmp), FULL (mulhi), FAST (mulhi) };
+static DECODE decode_mullo = { M32R_INSN_MULLO, & ITAB (M32R_INSN_MULLO), EX (fmt_15_cmp), FULL (mullo), FAST (mullo) };
+static DECODE decode_mulwhi = { M32R_INSN_MULWHI, & ITAB (M32R_INSN_MULWHI), EX (fmt_15_cmp), FULL (mulwhi), FAST (mulwhi) };
+static DECODE decode_mulwlo = { M32R_INSN_MULWLO, & ITAB (M32R_INSN_MULWLO), EX (fmt_15_cmp), FULL (mulwlo), FAST (mulwlo) };
+static DECODE decode_mv = { M32R_INSN_MV, & ITAB (M32R_INSN_MV), EX (fmt_31_mv), FULL (mv), FAST (mv) };
+static DECODE decode_mvfachi = { M32R_INSN_MVFACHI, & ITAB (M32R_INSN_MVFACHI), EX (fmt_32_mvfachi), FULL (mvfachi), FAST (mvfachi) };
+static DECODE decode_mvfaclo = { M32R_INSN_MVFACLO, & ITAB (M32R_INSN_MVFACLO), EX (fmt_32_mvfachi), FULL (mvfaclo), FAST (mvfaclo) };
+static DECODE decode_mvfacmi = { M32R_INSN_MVFACMI, & ITAB (M32R_INSN_MVFACMI), EX (fmt_32_mvfachi), FULL (mvfacmi), FAST (mvfacmi) };
+static DECODE decode_mvfc = { M32R_INSN_MVFC, & ITAB (M32R_INSN_MVFC), EX (fmt_33_mvfc), FULL (mvfc), FAST (mvfc) };
+static DECODE decode_mvtachi = { M32R_INSN_MVTACHI, & ITAB (M32R_INSN_MVTACHI), EX (fmt_34_mvtachi), FULL (mvtachi), FAST (mvtachi) };
+static DECODE decode_mvtaclo = { M32R_INSN_MVTACLO, & ITAB (M32R_INSN_MVTACLO), EX (fmt_34_mvtachi), FULL (mvtaclo), FAST (mvtaclo) };
+static DECODE decode_mvtc = { M32R_INSN_MVTC, & ITAB (M32R_INSN_MVTC), EX (fmt_35_mvtc), FULL (mvtc), FAST (mvtc) };
+static DECODE decode_neg = { M32R_INSN_NEG, & ITAB (M32R_INSN_NEG), EX (fmt_31_mv), FULL (neg), FAST (neg) };
+static DECODE decode_nop = { M32R_INSN_NOP, & ITAB (M32R_INSN_NOP), EX (fmt_36_nop), FULL (nop), FAST (nop) };
+static DECODE decode_not = { M32R_INSN_NOT, & ITAB (M32R_INSN_NOT), EX (fmt_31_mv), FULL (not), FAST (not) };
+static DECODE decode_rac = { M32R_INSN_RAC, & ITAB (M32R_INSN_RAC), EX (fmt_37_rac), FULL (rac), FAST (rac) };
+static DECODE decode_rach = { M32R_INSN_RACH, & ITAB (M32R_INSN_RACH), EX (fmt_37_rac), FULL (rach), FAST (rach) };
+static DECODE decode_rte = { M32R_INSN_RTE, & ITAB (M32R_INSN_RTE), EX (fmt_38_rte), FULL (rte), FAST (rte) };
+static DECODE decode_seth = { M32R_INSN_SETH, & ITAB (M32R_INSN_SETH), EX (fmt_39_seth), FULL (seth), FAST (seth) };
+static DECODE decode_sll = { M32R_INSN_SLL, & ITAB (M32R_INSN_SLL), EX (fmt_0_add), FULL (sll), FAST (sll) };
+static DECODE decode_sll3 = { M32R_INSN_SLL3, & ITAB (M32R_INSN_SLL3), EX (fmt_5_addv3), FULL (sll3), FAST (sll3) };
+static DECODE decode_slli = { M32R_INSN_SLLI, & ITAB (M32R_INSN_SLLI), EX (fmt_40_slli), FULL (slli), FAST (slli) };
+static DECODE decode_sra = { M32R_INSN_SRA, & ITAB (M32R_INSN_SRA), EX (fmt_0_add), FULL (sra), FAST (sra) };
+static DECODE decode_sra3 = { M32R_INSN_SRA3, & ITAB (M32R_INSN_SRA3), EX (fmt_5_addv3), FULL (sra3), FAST (sra3) };
+static DECODE decode_srai = { M32R_INSN_SRAI, & ITAB (M32R_INSN_SRAI), EX (fmt_40_slli), FULL (srai), FAST (srai) };
+static DECODE decode_srl = { M32R_INSN_SRL, & ITAB (M32R_INSN_SRL), EX (fmt_0_add), FULL (srl), FAST (srl) };
+static DECODE decode_srl3 = { M32R_INSN_SRL3, & ITAB (M32R_INSN_SRL3), EX (fmt_5_addv3), FULL (srl3), FAST (srl3) };
+static DECODE decode_srli = { M32R_INSN_SRLI, & ITAB (M32R_INSN_SRLI), EX (fmt_40_slli), FULL (srli), FAST (srli) };
+static DECODE decode_st = { M32R_INSN_ST, & ITAB (M32R_INSN_ST), EX (fmt_15_cmp), FULL (st), FAST (st) };
+static DECODE decode_st_d = { M32R_INSN_ST_D, & ITAB (M32R_INSN_ST_D), EX (fmt_41_st_d), FULL (st_d), FAST (st_d) };
+static DECODE decode_stb = { M32R_INSN_STB, & ITAB (M32R_INSN_STB), EX (fmt_15_cmp), FULL (stb), FAST (stb) };
+static DECODE decode_stb_d = { M32R_INSN_STB_D, & ITAB (M32R_INSN_STB_D), EX (fmt_41_st_d), FULL (stb_d), FAST (stb_d) };
+static DECODE decode_sth = { M32R_INSN_STH, & ITAB (M32R_INSN_STH), EX (fmt_15_cmp), FULL (sth), FAST (sth) };
+static DECODE decode_sth_d = { M32R_INSN_STH_D, & ITAB (M32R_INSN_STH_D), EX (fmt_41_st_d), FULL (sth_d), FAST (sth_d) };
+static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & ITAB (M32R_INSN_ST_PLUS), EX (fmt_15_cmp), FULL (st_plus), FAST (st_plus) };
+static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & ITAB (M32R_INSN_ST_MINUS), EX (fmt_15_cmp), FULL (st_minus), FAST (st_minus) };
+static DECODE decode_sub = { M32R_INSN_SUB, & ITAB (M32R_INSN_SUB), EX (fmt_0_add), FULL (sub), FAST (sub) };
+static DECODE decode_subv = { M32R_INSN_SUBV, & ITAB (M32R_INSN_SUBV), EX (fmt_0_add), FULL (subv), FAST (subv) };
+static DECODE decode_subx = { M32R_INSN_SUBX, & ITAB (M32R_INSN_SUBX), EX (fmt_6_addx), FULL (subx), FAST (subx) };
+static DECODE decode_trap = { M32R_INSN_TRAP, & ITAB (M32R_INSN_TRAP), EX (fmt_42_trap), FULL (trap), FAST (trap) };
+static DECODE decode_unlock = { M32R_INSN_UNLOCK, & ITAB (M32R_INSN_UNLOCK), EX (fmt_15_cmp), FULL (unlock), FAST (unlock) };
+

 DECODE m32r_decode_illegal = {
 DECODE m32r_decode_illegal = {

-  M32R_INSN_ILLEGAL, & m32r_cgen_insn_table_entries[0],
-  EX (illegal), FULL (illegal),
-  FAST (illegal)
+  M32R_INSN_ILLEGAL, & ITAB (M32R_INSN_ILLEGAL),
+  EX (illegal), FULL (illegal), FAST (illegal)

 };
 
 };
 

-/* The order must match that of `labels' in sem-switch.c.  */
+/* The order must match that of `labels' in sem-switch.c/read.c.  */

 
 DECODE *m32r_decode_vars[] = {
   & m32r_decode_illegal,
 
 DECODE *m32r_decode_vars[] = {
   & m32r_decode_illegal,


@@ -207,6 +218,7 @@ DECODE *m32r_decode_vars[] = {
   & decode_divu,
   & decode_rem,
   & decode_remu,
   & decode_divu,
   & decode_rem,
   & decode_remu,

+  & decode_divh,

   & decode_jl,
   & decode_jmp,
   & decode_ld,
   & decode_jl,
   & decode_jmp,
   & decode_ld,


@@ -327,7 +339,7 @@ m32r_decode (current_cpu, pc, insn)
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 

-      && default_0, && default_0, && default_0, && default_0, 
+      && case_0_144, && default_0, && default_0, && default_0, 

       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 


@@ -394,7 +406,7 @@ m32r_decode (current_cpu, pc, insn)
       &decode_cmpi, &decode_cmpui, &decode_illegal, &decode_illegal, 
       &decode_addv3, &decode_illegal, &decode_add3, &decode_illegal, 
       &decode_and3, &decode_xor3, &decode_or3, &decode_illegal, 
       &decode_cmpi, &decode_cmpui, &decode_illegal, &decode_illegal, 
       &decode_addv3, &decode_illegal, &decode_add3, &decode_illegal, 
       &decode_and3, &decode_xor3, &decode_or3, &decode_illegal, 

-      &decode_div, &decode_divu, &decode_rem, &decode_remu, 
+      0, &decode_divu, &decode_rem, &decode_remu, 

       &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
       &decode_srl3, &decode_illegal, &decode_sra3, &decode_illegal, 
       &decode_sll3, &decode_illegal, &decode_illegal, &decode_ldi16, 
       &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
       &decode_srl3, &decode_illegal, &decode_sra3, &decode_illegal, 
       &decode_sll3, &decode_illegal, &decode_illegal, &decode_ldi16, 


@@ -496,6 +508,67 @@ m32r_decode (current_cpu, pc, insn)
           unsigned int val = (((insn >> 8) & (15 << 0)));
           return insns[val];
         }
           unsigned int val = (((insn >> 8) & (15 << 0)));
           return insns[val];
         }

+      CASE (0, 144) :
+        {
+#ifdef __GNUC__
+          static void *labels_0_144[16] = {
+            && case_0_144_0, && default_0_144, && default_0_144, && default_0_144, 
+            && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
+            && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
+            && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
+          };
+#endif
+          static DECODE *insns[16] = {
+            0, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+          };
+          unsigned int val;
+          /* Must fetch more bits.  */
+          insn = GETIMEMUHI (current_cpu, CPU (h_pc) + 2);
+          val = (((insn >> 12) & (15 << 0)));
+          DECODE_SWITCH (0_144, val)
+            {
+            CASE (0_144, 0) :
+              {
+#ifdef __GNUC__
+                static void *labels_0_144_0[16] = {
+                  && case_0_144_0_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
+                  && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
+                  && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
+                  && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
+                };
+#endif
+                static DECODE *insns[16] = {
+                  0, &decode_illegal, &decode_illegal, &decode_illegal, 
+                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                };
+                unsigned int val;
+                val = (((insn >> 8) & (15 << 0)));
+                DECODE_SWITCH (0_144_0, val)
+                  {
+                  CASE (0_144_0, 0) :
+                    {
+                      static DECODE *insns[16] = {
+                        &decode_div, &decode_divh, &decode_illegal, &decode_illegal, 
+                        &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                        &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                        &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                      };
+                      unsigned int val = (((insn >> 4) & (15 << 0)));
+                      return insns[val];
+                    }
+                  DEFAULT (0_144_0) : return insns[val];
+                  }
+                ENDSWITCH (0_144_0)
+              }
+            DEFAULT (0_144) : return insns[val];
+            }
+          ENDSWITCH (0_144)
+        }

       CASE (0, 240) : /* fall through */
       CASE (0, 241) : /* fall through */
       CASE (0, 242) : /* fall through */
       CASE (0, 240) : /* fall through */
       CASE (0, 241) : /* fall through */
       CASE (0, 242) : /* fall through */

diff --git a/sim/m32r/decode.h b/sim/m32r/decode.h
new file mode 100644 (file)
index 0000000..3511e31
--- /dev/null
+++ b/sim/m32r/decode.h
@@ -0,0 +1,285 @@
+/* Decode header for m32r.
+
+This file is machine generated with CGEN.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef M32R_DECODE_H
+#define M32R_DECODE_H
+
+#define EX(fn) XCONCAT3 (m32r,_ex_,fn)
+#define SEM(fn) XCONCAT3 (m32r,_sem_,fn)
+#define SEMC(fn) XCONCAT3 (m32r,_semc_,fn)
+
+extern EXTRACT_FN EX (illegal);
+extern SEMANTIC_FN SEM (illegal);
+extern SEMANTIC_CACHE_FN SEMC (illegal);
+
+extern EXTRACT_FN EX (fmt_0_add);
+extern EXTRACT_FN EX (fmt_1_add3);
+extern EXTRACT_FN EX (fmt_2_and3);
+extern EXTRACT_FN EX (fmt_3_or3);
+extern EXTRACT_FN EX (fmt_4_addi);
+extern EXTRACT_FN EX (fmt_5_addv3);
+extern EXTRACT_FN EX (fmt_6_addx);
+extern EXTRACT_FN EX (fmt_7_bc8);
+extern EXTRACT_FN EX (fmt_8_bc24);
+extern EXTRACT_FN EX (fmt_9_beq);
+extern EXTRACT_FN EX (fmt_10_beqz);
+extern EXTRACT_FN EX (fmt_11_bl8);
+extern EXTRACT_FN EX (fmt_12_bl24);
+extern EXTRACT_FN EX (fmt_13_bra8);
+extern EXTRACT_FN EX (fmt_14_bra24);
+extern EXTRACT_FN EX (fmt_15_cmp);
+extern EXTRACT_FN EX (fmt_16_cmpi);
+extern EXTRACT_FN EX (fmt_17_cmpui);
+extern EXTRACT_FN EX (fmt_18_div);
+extern EXTRACT_FN EX (fmt_19_jl);
+extern EXTRACT_FN EX (fmt_20_jmp);
+extern EXTRACT_FN EX (fmt_21_ld);
+extern EXTRACT_FN EX (fmt_22_ld_d);
+extern EXTRACT_FN EX (fmt_23_ldb);
+extern EXTRACT_FN EX (fmt_24_ldb_d);
+extern EXTRACT_FN EX (fmt_25_ldh);
+extern EXTRACT_FN EX (fmt_26_ldh_d);
+extern EXTRACT_FN EX (fmt_27_ld24);
+extern EXTRACT_FN EX (fmt_28_ldi8);
+extern EXTRACT_FN EX (fmt_29_ldi16);
+extern EXTRACT_FN EX (fmt_30_machi);
+extern EXTRACT_FN EX (fmt_31_mv);
+extern EXTRACT_FN EX (fmt_32_mvfachi);
+extern EXTRACT_FN EX (fmt_33_mvfc);
+extern EXTRACT_FN EX (fmt_34_mvtachi);
+extern EXTRACT_FN EX (fmt_35_mvtc);
+extern EXTRACT_FN EX (fmt_36_nop);
+extern EXTRACT_FN EX (fmt_37_rac);
+extern EXTRACT_FN EX (fmt_38_rte);
+extern EXTRACT_FN EX (fmt_39_seth);
+extern EXTRACT_FN EX (fmt_40_slli);
+extern EXTRACT_FN EX (fmt_41_st_d);
+extern EXTRACT_FN EX (fmt_42_trap);
+
+extern SEMANTIC_FN SEM (add);
+extern SEMANTIC_CACHE_FN SEMC (add);
+extern SEMANTIC_FN SEM (add3);
+extern SEMANTIC_CACHE_FN SEMC (add3);
+extern SEMANTIC_FN SEM (and);
+extern SEMANTIC_CACHE_FN SEMC (and);
+extern SEMANTIC_FN SEM (and3);
+extern SEMANTIC_CACHE_FN SEMC (and3);
+extern SEMANTIC_FN SEM (or);
+extern SEMANTIC_CACHE_FN SEMC (or);
+extern SEMANTIC_FN SEM (or3);
+extern SEMANTIC_CACHE_FN SEMC (or3);
+extern SEMANTIC_FN SEM (xor);
+extern SEMANTIC_CACHE_FN SEMC (xor);
+extern SEMANTIC_FN SEM (xor3);
+extern SEMANTIC_CACHE_FN SEMC (xor3);
+extern SEMANTIC_FN SEM (addi);
+extern SEMANTIC_CACHE_FN SEMC (addi);
+extern SEMANTIC_FN SEM (addv);
+extern SEMANTIC_CACHE_FN SEMC (addv);
+extern SEMANTIC_FN SEM (addv3);
+extern SEMANTIC_CACHE_FN SEMC (addv3);
+extern SEMANTIC_FN SEM (addx);
+extern SEMANTIC_CACHE_FN SEMC (addx);
+extern SEMANTIC_FN SEM (bc8);
+extern SEMANTIC_CACHE_FN SEMC (bc8);
+extern SEMANTIC_FN SEM (bc24);
+extern SEMANTIC_CACHE_FN SEMC (bc24);
+extern SEMANTIC_FN SEM (beq);
+extern SEMANTIC_CACHE_FN SEMC (beq);
+extern SEMANTIC_FN SEM (beqz);
+extern SEMANTIC_CACHE_FN SEMC (beqz);
+extern SEMANTIC_FN SEM (bgez);
+extern SEMANTIC_CACHE_FN SEMC (bgez);
+extern SEMANTIC_FN SEM (bgtz);
+extern SEMANTIC_CACHE_FN SEMC (bgtz);
+extern SEMANTIC_FN SEM (blez);
+extern SEMANTIC_CACHE_FN SEMC (blez);
+extern SEMANTIC_FN SEM (bltz);
+extern SEMANTIC_CACHE_FN SEMC (bltz);
+extern SEMANTIC_FN SEM (bnez);
+extern SEMANTIC_CACHE_FN SEMC (bnez);
+extern SEMANTIC_FN SEM (bl8);
+extern SEMANTIC_CACHE_FN SEMC (bl8);
+extern SEMANTIC_FN SEM (bl24);
+extern SEMANTIC_CACHE_FN SEMC (bl24);
+extern SEMANTIC_FN SEM (bnc8);
+extern SEMANTIC_CACHE_FN SEMC (bnc8);
+extern SEMANTIC_FN SEM (bnc24);
+extern SEMANTIC_CACHE_FN SEMC (bnc24);
+extern SEMANTIC_FN SEM (bne);
+extern SEMANTIC_CACHE_FN SEMC (bne);
+extern SEMANTIC_FN SEM (bra8);
+extern SEMANTIC_CACHE_FN SEMC (bra8);
+extern SEMANTIC_FN SEM (bra24);
+extern SEMANTIC_CACHE_FN SEMC (bra24);
+extern SEMANTIC_FN SEM (cmp);
+extern SEMANTIC_CACHE_FN SEMC (cmp);
+extern SEMANTIC_FN SEM (cmpi);
+extern SEMANTIC_CACHE_FN SEMC (cmpi);
+extern SEMANTIC_FN SEM (cmpu);
+extern SEMANTIC_CACHE_FN SEMC (cmpu);
+extern SEMANTIC_FN SEM (cmpui);
+extern SEMANTIC_CACHE_FN SEMC (cmpui);
+extern SEMANTIC_FN SEM (div);
+extern SEMANTIC_CACHE_FN SEMC (div);
+extern SEMANTIC_FN SEM (divu);
+extern SEMANTIC_CACHE_FN SEMC (divu);
+extern SEMANTIC_FN SEM (rem);
+extern SEMANTIC_CACHE_FN SEMC (rem);
+extern SEMANTIC_FN SEM (remu);
+extern SEMANTIC_CACHE_FN SEMC (remu);
+extern SEMANTIC_FN SEM (divh);
+extern SEMANTIC_CACHE_FN SEMC (divh);
+extern SEMANTIC_FN SEM (jl);
+extern SEMANTIC_CACHE_FN SEMC (jl);
+extern SEMANTIC_FN SEM (jmp);
+extern SEMANTIC_CACHE_FN SEMC (jmp);
+extern SEMANTIC_FN SEM (ld);
+extern SEMANTIC_CACHE_FN SEMC (ld);
+extern SEMANTIC_FN SEM (ld_d);
+extern SEMANTIC_CACHE_FN SEMC (ld_d);
+extern SEMANTIC_FN SEM (ldb);
+extern SEMANTIC_CACHE_FN SEMC (ldb);
+extern SEMANTIC_FN SEM (ldb_d);
+extern SEMANTIC_CACHE_FN SEMC (ldb_d);
+extern SEMANTIC_FN SEM (ldh);
+extern SEMANTIC_CACHE_FN SEMC (ldh);
+extern SEMANTIC_FN SEM (ldh_d);
+extern SEMANTIC_CACHE_FN SEMC (ldh_d);
+extern SEMANTIC_FN SEM (ldub);
+extern SEMANTIC_CACHE_FN SEMC (ldub);
+extern SEMANTIC_FN SEM (ldub_d);
+extern SEMANTIC_CACHE_FN SEMC (ldub_d);
+extern SEMANTIC_FN SEM (lduh);
+extern SEMANTIC_CACHE_FN SEMC (lduh);
+extern SEMANTIC_FN SEM (lduh_d);
+extern SEMANTIC_CACHE_FN SEMC (lduh_d);
+extern SEMANTIC_FN SEM (ld_plus);
+extern SEMANTIC_CACHE_FN SEMC (ld_plus);
+extern SEMANTIC_FN SEM (ld24);
+extern SEMANTIC_CACHE_FN SEMC (ld24);
+extern SEMANTIC_FN SEM (ldi8);
+extern SEMANTIC_CACHE_FN SEMC (ldi8);
+extern SEMANTIC_FN SEM (ldi16);
+extern SEMANTIC_CACHE_FN SEMC (ldi16);
+extern SEMANTIC_FN SEM (lock);
+extern SEMANTIC_CACHE_FN SEMC (lock);
+extern SEMANTIC_FN SEM (machi);
+extern SEMANTIC_CACHE_FN SEMC (machi);
+extern SEMANTIC_FN SEM (maclo);
+extern SEMANTIC_CACHE_FN SEMC (maclo);
+extern SEMANTIC_FN SEM (macwhi);
+extern SEMANTIC_CACHE_FN SEMC (macwhi);
+extern SEMANTIC_FN SEM (macwlo);
+extern SEMANTIC_CACHE_FN SEMC (macwlo);
+extern SEMANTIC_FN SEM (mul);
+extern SEMANTIC_CACHE_FN SEMC (mul);
+extern SEMANTIC_FN SEM (mulhi);
+extern SEMANTIC_CACHE_FN SEMC (mulhi);
+extern SEMANTIC_FN SEM (mullo);
+extern SEMANTIC_CACHE_FN SEMC (mullo);
+extern SEMANTIC_FN SEM (mulwhi);
+extern SEMANTIC_CACHE_FN SEMC (mulwhi);
+extern SEMANTIC_FN SEM (mulwlo);
+extern SEMANTIC_CACHE_FN SEMC (mulwlo);
+extern SEMANTIC_FN SEM (mv);
+extern SEMANTIC_CACHE_FN SEMC (mv);
+extern SEMANTIC_FN SEM (mvfachi);
+extern SEMANTIC_CACHE_FN SEMC (mvfachi);
+extern SEMANTIC_FN SEM (mvfaclo);
+extern SEMANTIC_CACHE_FN SEMC (mvfaclo);
+extern SEMANTIC_FN SEM (mvfacmi);
+extern SEMANTIC_CACHE_FN SEMC (mvfacmi);
+extern SEMANTIC_FN SEM (mvfc);
+extern SEMANTIC_CACHE_FN SEMC (mvfc);
+extern SEMANTIC_FN SEM (mvtachi);
+extern SEMANTIC_CACHE_FN SEMC (mvtachi);
+extern SEMANTIC_FN SEM (mvtaclo);
+extern SEMANTIC_CACHE_FN SEMC (mvtaclo);
+extern SEMANTIC_FN SEM (mvtc);
+extern SEMANTIC_CACHE_FN SEMC (mvtc);
+extern SEMANTIC_FN SEM (neg);
+extern SEMANTIC_CACHE_FN SEMC (neg);
+extern SEMANTIC_FN SEM (nop);
+extern SEMANTIC_CACHE_FN SEMC (nop);
+extern SEMANTIC_FN SEM (not);
+extern SEMANTIC_CACHE_FN SEMC (not);
+extern SEMANTIC_FN SEM (rac);
+extern SEMANTIC_CACHE_FN SEMC (rac);
+extern SEMANTIC_FN SEM (rach);
+extern SEMANTIC_CACHE_FN SEMC (rach);
+extern SEMANTIC_FN SEM (rte);
+extern SEMANTIC_CACHE_FN SEMC (rte);
+extern SEMANTIC_FN SEM (seth);
+extern SEMANTIC_CACHE_FN SEMC (seth);
+extern SEMANTIC_FN SEM (sll);
+extern SEMANTIC_CACHE_FN SEMC (sll);
+extern SEMANTIC_FN SEM (sll3);
+extern SEMANTIC_CACHE_FN SEMC (sll3);
+extern SEMANTIC_FN SEM (slli);
+extern SEMANTIC_CACHE_FN SEMC (slli);
+extern SEMANTIC_FN SEM (sra);
+extern SEMANTIC_CACHE_FN SEMC (sra);
+extern SEMANTIC_FN SEM (sra3);
+extern SEMANTIC_CACHE_FN SEMC (sra3);
+extern SEMANTIC_FN SEM (srai);
+extern SEMANTIC_CACHE_FN SEMC (srai);
+extern SEMANTIC_FN SEM (srl);
+extern SEMANTIC_CACHE_FN SEMC (srl);
+extern SEMANTIC_FN SEM (srl3);
+extern SEMANTIC_CACHE_FN SEMC (srl3);
+extern SEMANTIC_FN SEM (srli);
+extern SEMANTIC_CACHE_FN SEMC (srli);
+extern SEMANTIC_FN SEM (st);
+extern SEMANTIC_CACHE_FN SEMC (st);
+extern SEMANTIC_FN SEM (st_d);
+extern SEMANTIC_CACHE_FN SEMC (st_d);
+extern SEMANTIC_FN SEM (stb);
+extern SEMANTIC_CACHE_FN SEMC (stb);
+extern SEMANTIC_FN SEM (stb_d);
+extern SEMANTIC_CACHE_FN SEMC (stb_d);
+extern SEMANTIC_FN SEM (sth);
+extern SEMANTIC_CACHE_FN SEMC (sth);
+extern SEMANTIC_FN SEM (sth_d);
+extern SEMANTIC_CACHE_FN SEMC (sth_d);
+extern SEMANTIC_FN SEM (st_plus);
+extern SEMANTIC_CACHE_FN SEMC (st_plus);
+extern SEMANTIC_FN SEM (st_minus);
+extern SEMANTIC_CACHE_FN SEMC (st_minus);
+extern SEMANTIC_FN SEM (sub);
+extern SEMANTIC_CACHE_FN SEMC (sub);
+extern SEMANTIC_FN SEM (subv);
+extern SEMANTIC_CACHE_FN SEMC (subv);
+extern SEMANTIC_FN SEM (subx);
+extern SEMANTIC_CACHE_FN SEMC (subx);
+extern SEMANTIC_FN SEM (trap);
+extern SEMANTIC_CACHE_FN SEMC (trap);
+extern SEMANTIC_FN SEM (unlock);
+extern SEMANTIC_CACHE_FN SEMC (unlock);
+
+#undef EX
+#undef SEM
+#undef SEMC
+
+#endif /* M32R_DECODE_H */

diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c
index 31c32af..3ed3018 100644 (file)
--- a/sim/m32r/decodex.c
+++ b/sim/m32r/decodex.c
@@ -40,6 +40,14 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define EX(fn) 0
 #endif
 
 #define EX(fn) 0
 #endif
 

+#ifdef HAVE_PARALLEL_EXEC
+#ifdef __GNUC__
+#define READ(n) 0
+#else
+#define READ(n) XCONCAT3 (READ,_,n)
+#endif
+#endif
+

 #if WITH_SEM_SWITCH_FULL
 #define FULL(fn) 0
 #else
 #if WITH_SEM_SWITCH_FULL
 #define FULL(fn) 0
 #else


@@ -62,127 +70,134 @@ with this program; if not, write to the Free Software Foundation, Inc.,
    prepend m32rx_, so simplify things by handling it here.  */
 #define decode_illegal m32rx_decode_illegal
 
    prepend m32rx_, so simplify things by handling it here.  */
 #define decode_illegal m32rx_decode_illegal
 

-static DECODE decode_add = { M32R_INSN_ADD, & m32r_cgen_insn_table_entries[M32R_INSN_ADD], EX (fmt_0_add), FULL (add), FAST (add) };
-static DECODE decode_add3 = { M32R_INSN_ADD3, & m32r_cgen_insn_table_entries[M32R_INSN_ADD3], EX (fmt_1_add3), FULL (add3), FAST (add3) };
-static DECODE decode_and = { M32R_INSN_AND, & m32r_cgen_insn_table_entries[M32R_INSN_AND], EX (fmt_0_add), FULL (and), FAST (and) };
-static DECODE decode_and3 = { M32R_INSN_AND3, & m32r_cgen_insn_table_entries[M32R_INSN_AND3], EX (fmt_2_and3), FULL (and3), FAST (and3) };
-static DECODE decode_or = { M32R_INSN_OR, & m32r_cgen_insn_table_entries[M32R_INSN_OR], EX (fmt_0_add), FULL (or), FAST (or) };
-static DECODE decode_or3 = { M32R_INSN_OR3, & m32r_cgen_insn_table_entries[M32R_INSN_OR3], EX (fmt_3_or3), FULL (or3), FAST (or3) };
-static DECODE decode_xor = { M32R_INSN_XOR, & m32r_cgen_insn_table_entries[M32R_INSN_XOR], EX (fmt_0_add), FULL (xor), FAST (xor) };
-static DECODE decode_xor3 = { M32R_INSN_XOR3, & m32r_cgen_insn_table_entries[M32R_INSN_XOR3], EX (fmt_2_and3), FULL (xor3), FAST (xor3) };
-static DECODE decode_addi = { M32R_INSN_ADDI, & m32r_cgen_insn_table_entries[M32R_INSN_ADDI], EX (fmt_4_addi), FULL (addi), FAST (addi) };
-static DECODE decode_addv = { M32R_INSN_ADDV, & m32r_cgen_insn_table_entries[M32R_INSN_ADDV], EX (fmt_0_add), FULL (addv), FAST (addv) };
-static DECODE decode_addv3 = { M32R_INSN_ADDV3, & m32r_cgen_insn_table_entries[M32R_INSN_ADDV3], EX (fmt_5_addv3), FULL (addv3), FAST (addv3) };
-static DECODE decode_addx = { M32R_INSN_ADDX, & m32r_cgen_insn_table_entries[M32R_INSN_ADDX], EX (fmt_6_addx), FULL (addx), FAST (addx) };
-static DECODE decode_bc8 = { M32R_INSN_BC8, & m32r_cgen_insn_table_entries[M32R_INSN_BC8], EX (fmt_7_bc8), FULL (bc8), FAST (bc8) };
-static DECODE decode_bc24 = { M32R_INSN_BC24, & m32r_cgen_insn_table_entries[M32R_INSN_BC24], EX (fmt_8_bc24), FULL (bc24), FAST (bc24) };
-static DECODE decode_beq = { M32R_INSN_BEQ, & m32r_cgen_insn_table_entries[M32R_INSN_BEQ], EX (fmt_9_beq), FULL (beq), FAST (beq) };
-static DECODE decode_beqz = { M32R_INSN_BEQZ, & m32r_cgen_insn_table_entries[M32R_INSN_BEQZ], EX (fmt_10_beqz), FULL (beqz), FAST (beqz) };
-static DECODE decode_bgez = { M32R_INSN_BGEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BGEZ], EX (fmt_10_beqz), FULL (bgez), FAST (bgez) };
-static DECODE decode_bgtz = { M32R_INSN_BGTZ, & m32r_cgen_insn_table_entries[M32R_INSN_BGTZ], EX (fmt_10_beqz), FULL (bgtz), FAST (bgtz) };
-static DECODE decode_blez = { M32R_INSN_BLEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BLEZ], EX (fmt_10_beqz), FULL (blez), FAST (blez) };
-static DECODE decode_bltz = { M32R_INSN_BLTZ, & m32r_cgen_insn_table_entries[M32R_INSN_BLTZ], EX (fmt_10_beqz), FULL (bltz), FAST (bltz) };
-static DECODE decode_bnez = { M32R_INSN_BNEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BNEZ], EX (fmt_10_beqz), FULL (bnez), FAST (bnez) };
-static DECODE decode_bl8 = { M32R_INSN_BL8, & m32r_cgen_insn_table_entries[M32R_INSN_BL8], EX (fmt_11_bl8), FULL (bl8), FAST (bl8) };
-static DECODE decode_bl24 = { M32R_INSN_BL24, & m32r_cgen_insn_table_entries[M32R_INSN_BL24], EX (fmt_12_bl24), FULL (bl24), FAST (bl24) };
-static DECODE decode_bcl8 = { M32R_INSN_BCL8, & m32r_cgen_insn_table_entries[M32R_INSN_BCL8], EX (fmt_13_bcl8), FULL (bcl8), FAST (bcl8) };
-static DECODE decode_bcl24 = { M32R_INSN_BCL24, & m32r_cgen_insn_table_entries[M32R_INSN_BCL24], EX (fmt_14_bcl24), FULL (bcl24), FAST (bcl24) };
-static DECODE decode_bnc8 = { M32R_INSN_BNC8, & m32r_cgen_insn_table_entries[M32R_INSN_BNC8], EX (fmt_7_bc8), FULL (bnc8), FAST (bnc8) };
-static DECODE decode_bnc24 = { M32R_INSN_BNC24, & m32r_cgen_insn_table_entries[M32R_INSN_BNC24], EX (fmt_8_bc24), FULL (bnc24), FAST (bnc24) };
-static DECODE decode_bne = { M32R_INSN_BNE, & m32r_cgen_insn_table_entries[M32R_INSN_BNE], EX (fmt_9_beq), FULL (bne), FAST (bne) };
-static DECODE decode_bra8 = { M32R_INSN_BRA8, & m32r_cgen_insn_table_entries[M32R_INSN_BRA8], EX (fmt_15_bra8), FULL (bra8), FAST (bra8) };
-static DECODE decode_bra24 = { M32R_INSN_BRA24, & m32r_cgen_insn_table_entries[M32R_INSN_BRA24], EX (fmt_16_bra24), FULL (bra24), FAST (bra24) };
-static DECODE decode_bncl8 = { M32R_INSN_BNCL8, & m32r_cgen_insn_table_entries[M32R_INSN_BNCL8], EX (fmt_13_bcl8), FULL (bncl8), FAST (bncl8) };
-static DECODE decode_bncl24 = { M32R_INSN_BNCL24, & m32r_cgen_insn_table_entries[M32R_INSN_BNCL24], EX (fmt_14_bcl24), FULL (bncl24), FAST (bncl24) };
-static DECODE decode_cmp = { M32R_INSN_CMP, & m32r_cgen_insn_table_entries[M32R_INSN_CMP], EX (fmt_17_cmp), FULL (cmp), FAST (cmp) };
-static DECODE decode_cmpi = { M32R_INSN_CMPI, & m32r_cgen_insn_table_entries[M32R_INSN_CMPI], EX (fmt_18_cmpi), FULL (cmpi), FAST (cmpi) };
-static DECODE decode_cmpu = { M32R_INSN_CMPU, & m32r_cgen_insn_table_entries[M32R_INSN_CMPU], EX (fmt_17_cmp), FULL (cmpu), FAST (cmpu) };
-static DECODE decode_cmpui = { M32R_INSN_CMPUI, & m32r_cgen_insn_table_entries[M32R_INSN_CMPUI], EX (fmt_19_cmpui), FULL (cmpui), FAST (cmpui) };
-static DECODE decode_cmpeq = { M32R_INSN_CMPEQ, & m32r_cgen_insn_table_entries[M32R_INSN_CMPEQ], EX (fmt_17_cmp), FULL (cmpeq), FAST (cmpeq) };
-static DECODE decode_cmpz = { M32R_INSN_CMPZ, & m32r_cgen_insn_table_entries[M32R_INSN_CMPZ], EX (fmt_20_cmpz), FULL (cmpz), FAST (cmpz) };
-static DECODE decode_div = { M32R_INSN_DIV, & m32r_cgen_insn_table_entries[M32R_INSN_DIV], EX (fmt_21_div), FULL (div), FAST (div) };
-static DECODE decode_divu = { M32R_INSN_DIVU, & m32r_cgen_insn_table_entries[M32R_INSN_DIVU], EX (fmt_21_div), FULL (divu), FAST (divu) };
-static DECODE decode_rem = { M32R_INSN_REM, & m32r_cgen_insn_table_entries[M32R_INSN_REM], EX (fmt_21_div), FULL (rem), FAST (rem) };
-static DECODE decode_remu = { M32R_INSN_REMU, & m32r_cgen_insn_table_entries[M32R_INSN_REMU], EX (fmt_21_div), FULL (remu), FAST (remu) };
-static DECODE decode_jc = { M32R_INSN_JC, & m32r_cgen_insn_table_entries[M32R_INSN_JC], EX (fmt_22_jc), FULL (jc), FAST (jc) };
-static DECODE decode_jnc = { M32R_INSN_JNC, & m32r_cgen_insn_table_entries[M32R_INSN_JNC], EX (fmt_22_jc), FULL (jnc), FAST (jnc) };
-static DECODE decode_jl = { M32R_INSN_JL, & m32r_cgen_insn_table_entries[M32R_INSN_JL], EX (fmt_23_jl), FULL (jl), FAST (jl) };
-static DECODE decode_jmp = { M32R_INSN_JMP, & m32r_cgen_insn_table_entries[M32R_INSN_JMP], EX (fmt_24_jmp), FULL (jmp), FAST (jmp) };
-static DECODE decode_ld = { M32R_INSN_LD, & m32r_cgen_insn_table_entries[M32R_INSN_LD], EX (fmt_25_ld), FULL (ld), FAST (ld) };
-static DECODE decode_ld_d = { M32R_INSN_LD_D, & m32r_cgen_insn_table_entries[M32R_INSN_LD_D], EX (fmt_26_ld_d), FULL (ld_d), FAST (ld_d) };
-static DECODE decode_ldb = { M32R_INSN_LDB, & m32r_cgen_insn_table_entries[M32R_INSN_LDB], EX (fmt_27_ldb), FULL (ldb), FAST (ldb) };
-static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDB_D], EX (fmt_28_ldb_d), FULL (ldb_d), FAST (ldb_d) };
-static DECODE decode_ldh = { M32R_INSN_LDH, & m32r_cgen_insn_table_entries[M32R_INSN_LDH], EX (fmt_29_ldh), FULL (ldh), FAST (ldh) };
-static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDH_D], EX (fmt_30_ldh_d), FULL (ldh_d), FAST (ldh_d) };
-static DECODE decode_ldub = { M32R_INSN_LDUB, & m32r_cgen_insn_table_entries[M32R_INSN_LDUB], EX (fmt_27_ldb), FULL (ldub), FAST (ldub) };
-static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDUB_D], EX (fmt_28_ldb_d), FULL (ldub_d), FAST (ldub_d) };
-static DECODE decode_lduh = { M32R_INSN_LDUH, & m32r_cgen_insn_table_entries[M32R_INSN_LDUH], EX (fmt_29_ldh), FULL (lduh), FAST (lduh) };
-static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDUH_D], EX (fmt_30_ldh_d), FULL (lduh_d), FAST (lduh_d) };
-static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & m32r_cgen_insn_table_entries[M32R_INSN_LD_PLUS], EX (fmt_25_ld), FULL (ld_plus), FAST (ld_plus) };
-static DECODE decode_ld24 = { M32R_INSN_LD24, & m32r_cgen_insn_table_entries[M32R_INSN_LD24], EX (fmt_31_ld24), FULL (ld24), FAST (ld24) };
-static DECODE decode_ldi8 = { M32R_INSN_LDI8, & m32r_cgen_insn_table_entries[M32R_INSN_LDI8], EX (fmt_32_ldi8), FULL (ldi8), FAST (ldi8) };
-static DECODE decode_ldi16 = { M32R_INSN_LDI16, & m32r_cgen_insn_table_entries[M32R_INSN_LDI16], EX (fmt_33_ldi16), FULL (ldi16), FAST (ldi16) };
-static DECODE decode_lock = { M32R_INSN_LOCK, & m32r_cgen_insn_table_entries[M32R_INSN_LOCK], EX (fmt_0_add), FULL (lock), FAST (lock) };
-static DECODE decode_machi_a = { M32R_INSN_MACHI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MACHI_A], EX (fmt_34_machi_a), FULL (machi_a), FAST (machi_a) };
-static DECODE decode_maclo_a = { M32R_INSN_MACLO_A, & m32r_cgen_insn_table_entries[M32R_INSN_MACLO_A], EX (fmt_34_machi_a), FULL (maclo_a), FAST (maclo_a) };
-static DECODE decode_mul = { M32R_INSN_MUL, & m32r_cgen_insn_table_entries[M32R_INSN_MUL], EX (fmt_0_add), FULL (mul), FAST (mul) };
-static DECODE decode_mulhi_a = { M32R_INSN_MULHI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MULHI_A], EX (fmt_35_mulhi_a), FULL (mulhi_a), FAST (mulhi_a) };
-static DECODE decode_mullo_a = { M32R_INSN_MULLO_A, & m32r_cgen_insn_table_entries[M32R_INSN_MULLO_A], EX (fmt_35_mulhi_a), FULL (mullo_a), FAST (mullo_a) };
-static DECODE decode_mv = { M32R_INSN_MV, & m32r_cgen_insn_table_entries[M32R_INSN_MV], EX (fmt_36_mv), FULL (mv), FAST (mv) };
-static DECODE decode_mvfachi_a = { M32R_INSN_MVFACHI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACHI_A], EX (fmt_37_mvfachi_a), FULL (mvfachi_a), FAST (mvfachi_a) };
-static DECODE decode_mvfaclo_a = { M32R_INSN_MVFACLO_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACLO_A], EX (fmt_37_mvfachi_a), FULL (mvfaclo_a), FAST (mvfaclo_a) };
-static DECODE decode_mvfacmi_a = { M32R_INSN_MVFACMI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACMI_A], EX (fmt_37_mvfachi_a), FULL (mvfacmi_a), FAST (mvfacmi_a) };
-static DECODE decode_mvfc = { M32R_INSN_MVFC, & m32r_cgen_insn_table_entries[M32R_INSN_MVFC], EX (fmt_38_mvfc), FULL (mvfc), FAST (mvfc) };
-static DECODE decode_mvtachi_a = { M32R_INSN_MVTACHI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVTACHI_A], EX (fmt_39_mvtachi_a), FULL (mvtachi_a), FAST (mvtachi_a) };
-static DECODE decode_mvtaclo_a = { M32R_INSN_MVTACLO_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVTACLO_A], EX (fmt_39_mvtachi_a), FULL (mvtaclo_a), FAST (mvtaclo_a) };
-static DECODE decode_mvtc = { M32R_INSN_MVTC, & m32r_cgen_insn_table_entries[M32R_INSN_MVTC], EX (fmt_40_mvtc), FULL (mvtc), FAST (mvtc) };
-static DECODE decode_neg = { M32R_INSN_NEG, & m32r_cgen_insn_table_entries[M32R_INSN_NEG], EX (fmt_36_mv), FULL (neg), FAST (neg) };
-static DECODE decode_nop = { M32R_INSN_NOP, & m32r_cgen_insn_table_entries[M32R_INSN_NOP], EX (fmt_41_nop), FULL (nop), FAST (nop) };
-static DECODE decode_not = { M32R_INSN_NOT, & m32r_cgen_insn_table_entries[M32R_INSN_NOT], EX (fmt_36_mv), FULL (not), FAST (not) };
-static DECODE decode_rac_a = { M32R_INSN_RAC_A, & m32r_cgen_insn_table_entries[M32R_INSN_RAC_A], EX (fmt_42_rac_a), FULL (rac_a), FAST (rac_a) };
-static DECODE decode_rach_a = { M32R_INSN_RACH_A, & m32r_cgen_insn_table_entries[M32R_INSN_RACH_A], EX (fmt_42_rac_a), FULL (rach_a), FAST (rach_a) };
-static DECODE decode_rte = { M32R_INSN_RTE, & m32r_cgen_insn_table_entries[M32R_INSN_RTE], EX (fmt_43_rte), FULL (rte), FAST (rte) };
-static DECODE decode_seth = { M32R_INSN_SETH, & m32r_cgen_insn_table_entries[M32R_INSN_SETH], EX (fmt_44_seth), FULL (seth), FAST (seth) };
-static DECODE decode_sll = { M32R_INSN_SLL, & m32r_cgen_insn_table_entries[M32R_INSN_SLL], EX (fmt_0_add), FULL (sll), FAST (sll) };
-static DECODE decode_sll3 = { M32R_INSN_SLL3, & m32r_cgen_insn_table_entries[M32R_INSN_SLL3], EX (fmt_5_addv3), FULL (sll3), FAST (sll3) };
-static DECODE decode_slli = { M32R_INSN_SLLI, & m32r_cgen_insn_table_entries[M32R_INSN_SLLI], EX (fmt_45_slli), FULL (slli), FAST (slli) };
-static DECODE decode_sra = { M32R_INSN_SRA, & m32r_cgen_insn_table_entries[M32R_INSN_SRA], EX (fmt_0_add), FULL (sra), FAST (sra) };
-static DECODE decode_sra3 = { M32R_INSN_SRA3, & m32r_cgen_insn_table_entries[M32R_INSN_SRA3], EX (fmt_5_addv3), FULL (sra3), FAST (sra3) };
-static DECODE decode_srai = { M32R_INSN_SRAI, & m32r_cgen_insn_table_entries[M32R_INSN_SRAI], EX (fmt_45_slli), FULL (srai), FAST (srai) };
-static DECODE decode_srl = { M32R_INSN_SRL, & m32r_cgen_insn_table_entries[M32R_INSN_SRL], EX (fmt_0_add), FULL (srl), FAST (srl) };
-static DECODE decode_srl3 = { M32R_INSN_SRL3, & m32r_cgen_insn_table_entries[M32R_INSN_SRL3], EX (fmt_5_addv3), FULL (srl3), FAST (srl3) };
-static DECODE decode_srli = { M32R_INSN_SRLI, & m32r_cgen_insn_table_entries[M32R_INSN_SRLI], EX (fmt_45_slli), FULL (srli), FAST (srli) };
-static DECODE decode_st = { M32R_INSN_ST, & m32r_cgen_insn_table_entries[M32R_INSN_ST], EX (fmt_17_cmp), FULL (st), FAST (st) };
-static DECODE decode_st_d = { M32R_INSN_ST_D, & m32r_cgen_insn_table_entries[M32R_INSN_ST_D], EX (fmt_46_st_d), FULL (st_d), FAST (st_d) };
-static DECODE decode_stb = { M32R_INSN_STB, & m32r_cgen_insn_table_entries[M32R_INSN_STB], EX (fmt_17_cmp), FULL (stb), FAST (stb) };
-static DECODE decode_stb_d = { M32R_INSN_STB_D, & m32r_cgen_insn_table_entries[M32R_INSN_STB_D], EX (fmt_46_st_d), FULL (stb_d), FAST (stb_d) };
-static DECODE decode_sth = { M32R_INSN_STH, & m32r_cgen_insn_table_entries[M32R_INSN_STH], EX (fmt_17_cmp), FULL (sth), FAST (sth) };
-static DECODE decode_sth_d = { M32R_INSN_STH_D, & m32r_cgen_insn_table_entries[M32R_INSN_STH_D], EX (fmt_46_st_d), FULL (sth_d), FAST (sth_d) };
-static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & m32r_cgen_insn_table_entries[M32R_INSN_ST_PLUS], EX (fmt_17_cmp), FULL (st_plus), FAST (st_plus) };
-static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & m32r_cgen_insn_table_entries[M32R_INSN_ST_MINUS], EX (fmt_17_cmp), FULL (st_minus), FAST (st_minus) };
-static DECODE decode_sub = { M32R_INSN_SUB, & m32r_cgen_insn_table_entries[M32R_INSN_SUB], EX (fmt_0_add), FULL (sub), FAST (sub) };
-static DECODE decode_subv = { M32R_INSN_SUBV, & m32r_cgen_insn_table_entries[M32R_INSN_SUBV], EX (fmt_0_add), FULL (subv), FAST (subv) };
-static DECODE decode_subx = { M32R_INSN_SUBX, & m32r_cgen_insn_table_entries[M32R_INSN_SUBX], EX (fmt_6_addx), FULL (subx), FAST (subx) };
-static DECODE decode_trap = { M32R_INSN_TRAP, & m32r_cgen_insn_table_entries[M32R_INSN_TRAP], EX (fmt_47_trap), FULL (trap), FAST (trap) };
-static DECODE decode_unlock = { M32R_INSN_UNLOCK, & m32r_cgen_insn_table_entries[M32R_INSN_UNLOCK], EX (fmt_17_cmp), FULL (unlock), FAST (unlock) };
-static DECODE decode_satb = { M32R_INSN_SATB, & m32r_cgen_insn_table_entries[M32R_INSN_SATB], EX (fmt_48_satb), FULL (satb), FAST (satb) };
-static DECODE decode_sath = { M32R_INSN_SATH, & m32r_cgen_insn_table_entries[M32R_INSN_SATH], EX (fmt_48_satb), FULL (sath), FAST (sath) };
-static DECODE decode_sat = { M32R_INSN_SAT, & m32r_cgen_insn_table_entries[M32R_INSN_SAT], EX (fmt_49_sat), FULL (sat), FAST (sat) };
-static DECODE decode_pcmpbz = { M32R_INSN_PCMPBZ, & m32r_cgen_insn_table_entries[M32R_INSN_PCMPBZ], EX (fmt_20_cmpz), FULL (pcmpbz), FAST (pcmpbz) };
-static DECODE decode_sadd = { M32R_INSN_SADD, & m32r_cgen_insn_table_entries[M32R_INSN_SADD], EX (fmt_50_sadd), FULL (sadd), FAST (sadd) };
-static DECODE decode_macwu1 = { M32R_INSN_MACWU1, & m32r_cgen_insn_table_entries[M32R_INSN_MACWU1], EX (fmt_51_macwu1), FULL (macwu1), FAST (macwu1) };
-static DECODE decode_msblo = { M32R_INSN_MSBLO, & m32r_cgen_insn_table_entries[M32R_INSN_MSBLO], EX (fmt_52_msblo), FULL (msblo), FAST (msblo) };
-static DECODE decode_mulwu1 = { M32R_INSN_MULWU1, & m32r_cgen_insn_table_entries[M32R_INSN_MULWU1], EX (fmt_17_cmp), FULL (mulwu1), FAST (mulwu1) };
-static DECODE decode_machl1 = { M32R_INSN_MACHL1, & m32r_cgen_insn_table_entries[M32R_INSN_MACHL1], EX (fmt_51_macwu1), FULL (machl1), FAST (machl1) };
-static DECODE decode_sc = { M32R_INSN_SC, & m32r_cgen_insn_table_entries[M32R_INSN_SC], EX (fmt_53_sc), FULL (sc), FAST (sc) };
-static DECODE decode_snc = { M32R_INSN_SNC, & m32r_cgen_insn_table_entries[M32R_INSN_SNC], EX (fmt_53_sc), FULL (snc), FAST (snc) };
+#define ITAB(n) m32r_cgen_insn_table_entries[n]
+
+static DECODE decode_add = { M32R_INSN_ADD, & ITAB (M32R_INSN_ADD), EX (fmt_0_add), READ (FMT_0_ADD), FULL (add), FAST (add) };
+static DECODE decode_add3 = { M32R_INSN_ADD3, & ITAB (M32R_INSN_ADD3), EX (fmt_1_add3), READ (FMT_1_ADD3), FULL (add3), FAST (add3) };
+static DECODE decode_and = { M32R_INSN_AND, & ITAB (M32R_INSN_AND), EX (fmt_0_add), READ (FMT_0_ADD), FULL (and), FAST (and) };
+static DECODE decode_and3 = { M32R_INSN_AND3, & ITAB (M32R_INSN_AND3), EX (fmt_2_and3), READ (FMT_2_AND3), FULL (and3), FAST (and3) };
+static DECODE decode_or = { M32R_INSN_OR, & ITAB (M32R_INSN_OR), EX (fmt_0_add), READ (FMT_0_ADD), FULL (or), FAST (or) };
+static DECODE decode_or3 = { M32R_INSN_OR3, & ITAB (M32R_INSN_OR3), EX (fmt_3_or3), READ (FMT_3_OR3), FULL (or3), FAST (or3) };
+static DECODE decode_xor = { M32R_INSN_XOR, & ITAB (M32R_INSN_XOR), EX (fmt_0_add), READ (FMT_0_ADD), FULL (xor), FAST (xor) };
+static DECODE decode_xor3 = { M32R_INSN_XOR3, & ITAB (M32R_INSN_XOR3), EX (fmt_2_and3), READ (FMT_2_AND3), FULL (xor3), FAST (xor3) };
+static DECODE decode_addi = { M32R_INSN_ADDI, & ITAB (M32R_INSN_ADDI), EX (fmt_4_addi), READ (FMT_4_ADDI), FULL (addi), FAST (addi) };
+static DECODE decode_addv = { M32R_INSN_ADDV, & ITAB (M32R_INSN_ADDV), EX (fmt_0_add), READ (FMT_0_ADD), FULL (addv), FAST (addv) };
+static DECODE decode_addv3 = { M32R_INSN_ADDV3, & ITAB (M32R_INSN_ADDV3), EX (fmt_5_addv3), READ (FMT_5_ADDV3), FULL (addv3), FAST (addv3) };
+static DECODE decode_addx = { M32R_INSN_ADDX, & ITAB (M32R_INSN_ADDX), EX (fmt_6_addx), READ (FMT_6_ADDX), FULL (addx), FAST (addx) };
+static DECODE decode_bc8 = { M32R_INSN_BC8, & ITAB (M32R_INSN_BC8), EX (fmt_7_bc8), READ (FMT_7_BC8), FULL (bc8), FAST (bc8) };
+static DECODE decode_bc24 = { M32R_INSN_BC24, & ITAB (M32R_INSN_BC24), EX (fmt_8_bc24), READ (FMT_8_BC24), FULL (bc24), FAST (bc24) };
+static DECODE decode_beq = { M32R_INSN_BEQ, & ITAB (M32R_INSN_BEQ), EX (fmt_9_beq), READ (FMT_9_BEQ), FULL (beq), FAST (beq) };
+static DECODE decode_beqz = { M32R_INSN_BEQZ, & ITAB (M32R_INSN_BEQZ), EX (fmt_10_beqz), READ (FMT_10_BEQZ), FULL (beqz), FAST (beqz) };
+static DECODE decode_bgez = { M32R_INSN_BGEZ, & ITAB (M32R_INSN_BGEZ), EX (fmt_10_beqz), READ (FMT_10_BEQZ), FULL (bgez), FAST (bgez) };
+static DECODE decode_bgtz = { M32R_INSN_BGTZ, & ITAB (M32R_INSN_BGTZ), EX (fmt_10_beqz), READ (FMT_10_BEQZ), FULL (bgtz), FAST (bgtz) };
+static DECODE decode_blez = { M32R_INSN_BLEZ, & ITAB (M32R_INSN_BLEZ), EX (fmt_10_beqz), READ (FMT_10_BEQZ), FULL (blez), FAST (blez) };
+static DECODE decode_bltz = { M32R_INSN_BLTZ, & ITAB (M32R_INSN_BLTZ), EX (fmt_10_beqz), READ (FMT_10_BEQZ), FULL (bltz), FAST (bltz) };
+static DECODE decode_bnez = { M32R_INSN_BNEZ, & ITAB (M32R_INSN_BNEZ), EX (fmt_10_beqz), READ (FMT_10_BEQZ), FULL (bnez), FAST (bnez) };
+static DECODE decode_bl8 = { M32R_INSN_BL8, & ITAB (M32R_INSN_BL8), EX (fmt_11_bl8), READ (FMT_11_BL8), FULL (bl8), FAST (bl8) };
+static DECODE decode_bl24 = { M32R_INSN_BL24, & ITAB (M32R_INSN_BL24), EX (fmt_12_bl24), READ (FMT_12_BL24), FULL (bl24), FAST (bl24) };
+static DECODE decode_bcl8 = { M32R_INSN_BCL8, & ITAB (M32R_INSN_BCL8), EX (fmt_13_bcl8), READ (FMT_13_BCL8), FULL (bcl8), FAST (bcl8) };
+static DECODE decode_bcl24 = { M32R_INSN_BCL24, & ITAB (M32R_INSN_BCL24), EX (fmt_14_bcl24), READ (FMT_14_BCL24), FULL (bcl24), FAST (bcl24) };
+static DECODE decode_bnc8 = { M32R_INSN_BNC8, & ITAB (M32R_INSN_BNC8), EX (fmt_7_bc8), READ (FMT_7_BC8), FULL (bnc8), FAST (bnc8) };
+static DECODE decode_bnc24 = { M32R_INSN_BNC24, & ITAB (M32R_INSN_BNC24), EX (fmt_8_bc24), READ (FMT_8_BC24), FULL (bnc24), FAST (bnc24) };
+static DECODE decode_bne = { M32R_INSN_BNE, & ITAB (M32R_INSN_BNE), EX (fmt_9_beq), READ (FMT_9_BEQ), FULL (bne), FAST (bne) };
+static DECODE decode_bra8 = { M32R_INSN_BRA8, & ITAB (M32R_INSN_BRA8), EX (fmt_15_bra8), READ (FMT_15_BRA8), FULL (bra8), FAST (bra8) };
+static DECODE decode_bra24 = { M32R_INSN_BRA24, & ITAB (M32R_INSN_BRA24), EX (fmt_16_bra24), READ (FMT_16_BRA24), FULL (bra24), FAST (bra24) };
+static DECODE decode_bncl8 = { M32R_INSN_BNCL8, & ITAB (M32R_INSN_BNCL8), EX (fmt_13_bcl8), READ (FMT_13_BCL8), FULL (bncl8), FAST (bncl8) };
+static DECODE decode_bncl24 = { M32R_INSN_BNCL24, & ITAB (M32R_INSN_BNCL24), EX (fmt_14_bcl24), READ (FMT_14_BCL24), FULL (bncl24), FAST (bncl24) };
+static DECODE decode_cmp = { M32R_INSN_CMP, & ITAB (M32R_INSN_CMP), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (cmp), FAST (cmp) };
+static DECODE decode_cmpi = { M32R_INSN_CMPI, & ITAB (M32R_INSN_CMPI), EX (fmt_18_cmpi), READ (FMT_18_CMPI), FULL (cmpi), FAST (cmpi) };
+static DECODE decode_cmpu = { M32R_INSN_CMPU, & ITAB (M32R_INSN_CMPU), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (cmpu), FAST (cmpu) };
+static DECODE decode_cmpui = { M32R_INSN_CMPUI, & ITAB (M32R_INSN_CMPUI), EX (fmt_19_cmpui), READ (FMT_19_CMPUI), FULL (cmpui), FAST (cmpui) };
+static DECODE decode_cmpeq = { M32R_INSN_CMPEQ, & ITAB (M32R_INSN_CMPEQ), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (cmpeq), FAST (cmpeq) };
+static DECODE decode_cmpz = { M32R_INSN_CMPZ, & ITAB (M32R_INSN_CMPZ), EX (fmt_20_cmpz), READ (FMT_20_CMPZ), FULL (cmpz), FAST (cmpz) };
+static DECODE decode_div = { M32R_INSN_DIV, & ITAB (M32R_INSN_DIV), EX (fmt_21_div), READ (FMT_21_DIV), FULL (div), FAST (div) };
+static DECODE decode_divu = { M32R_INSN_DIVU, & ITAB (M32R_INSN_DIVU), EX (fmt_21_div), READ (FMT_21_DIV), FULL (divu), FAST (divu) };
+static DECODE decode_rem = { M32R_INSN_REM, & ITAB (M32R_INSN_REM), EX (fmt_21_div), READ (FMT_21_DIV), FULL (rem), FAST (rem) };
+static DECODE decode_remu = { M32R_INSN_REMU, & ITAB (M32R_INSN_REMU), EX (fmt_21_div), READ (FMT_21_DIV), FULL (remu), FAST (remu) };
+static DECODE decode_divh = { M32R_INSN_DIVH, & ITAB (M32R_INSN_DIVH), EX (fmt_21_div), READ (FMT_21_DIV), FULL (divh), FAST (divh) };
+static DECODE decode_jc = { M32R_INSN_JC, & ITAB (M32R_INSN_JC), EX (fmt_22_jc), READ (FMT_22_JC), FULL (jc), FAST (jc) };
+static DECODE decode_jnc = { M32R_INSN_JNC, & ITAB (M32R_INSN_JNC), EX (fmt_22_jc), READ (FMT_22_JC), FULL (jnc), FAST (jnc) };
+static DECODE decode_jl = { M32R_INSN_JL, & ITAB (M32R_INSN_JL), EX (fmt_23_jl), READ (FMT_23_JL), FULL (jl), FAST (jl) };
+static DECODE decode_jmp = { M32R_INSN_JMP, & ITAB (M32R_INSN_JMP), EX (fmt_24_jmp), READ (FMT_24_JMP), FULL (jmp), FAST (jmp) };
+static DECODE decode_ld = { M32R_INSN_LD, & ITAB (M32R_INSN_LD), EX (fmt_25_ld), READ (FMT_25_LD), FULL (ld), FAST (ld) };
+static DECODE decode_ld_d = { M32R_INSN_LD_D, & ITAB (M32R_INSN_LD_D), EX (fmt_26_ld_d), READ (FMT_26_LD_D), FULL (ld_d), FAST (ld_d) };
+static DECODE decode_ldb = { M32R_INSN_LDB, & ITAB (M32R_INSN_LDB), EX (fmt_27_ldb), READ (FMT_27_LDB), FULL (ldb), FAST (ldb) };
+static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & ITAB (M32R_INSN_LDB_D), EX (fmt_28_ldb_d), READ (FMT_28_LDB_D), FULL (ldb_d), FAST (ldb_d) };
+static DECODE decode_ldh = { M32R_INSN_LDH, & ITAB (M32R_INSN_LDH), EX (fmt_29_ldh), READ (FMT_29_LDH), FULL (ldh), FAST (ldh) };
+static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & ITAB (M32R_INSN_LDH_D), EX (fmt_30_ldh_d), READ (FMT_30_LDH_D), FULL (ldh_d), FAST (ldh_d) };
+static DECODE decode_ldub = { M32R_INSN_LDUB, & ITAB (M32R_INSN_LDUB), EX (fmt_27_ldb), READ (FMT_27_LDB), FULL (ldub), FAST (ldub) };
+static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & ITAB (M32R_INSN_LDUB_D), EX (fmt_28_ldb_d), READ (FMT_28_LDB_D), FULL (ldub_d), FAST (ldub_d) };
+static DECODE decode_lduh = { M32R_INSN_LDUH, & ITAB (M32R_INSN_LDUH), EX (fmt_29_ldh), READ (FMT_29_LDH), FULL (lduh), FAST (lduh) };
+static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & ITAB (M32R_INSN_LDUH_D), EX (fmt_30_ldh_d), READ (FMT_30_LDH_D), FULL (lduh_d), FAST (lduh_d) };
+static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & ITAB (M32R_INSN_LD_PLUS), EX (fmt_25_ld), READ (FMT_25_LD), FULL (ld_plus), FAST (ld_plus) };
+static DECODE decode_ld24 = { M32R_INSN_LD24, & ITAB (M32R_INSN_LD24), EX (fmt_31_ld24), READ (FMT_31_LD24), FULL (ld24), FAST (ld24) };
+static DECODE decode_ldi8 = { M32R_INSN_LDI8, & ITAB (M32R_INSN_LDI8), EX (fmt_32_ldi8), READ (FMT_32_LDI8), FULL (ldi8), FAST (ldi8) };
+static DECODE decode_ldi16 = { M32R_INSN_LDI16, & ITAB (M32R_INSN_LDI16), EX (fmt_33_ldi16), READ (FMT_33_LDI16), FULL (ldi16), FAST (ldi16) };
+static DECODE decode_lock = { M32R_INSN_LOCK, & ITAB (M32R_INSN_LOCK), EX (fmt_0_add), READ (FMT_0_ADD), FULL (lock), FAST (lock) };
+static DECODE decode_machi_a = { M32R_INSN_MACHI_A, & ITAB (M32R_INSN_MACHI_A), EX (fmt_34_machi_a), READ (FMT_34_MACHI_A), FULL (machi_a), FAST (machi_a) };
+static DECODE decode_maclo_a = { M32R_INSN_MACLO_A, & ITAB (M32R_INSN_MACLO_A), EX (fmt_34_machi_a), READ (FMT_34_MACHI_A), FULL (maclo_a), FAST (maclo_a) };
+static DECODE decode_mul = { M32R_INSN_MUL, & ITAB (M32R_INSN_MUL), EX (fmt_0_add), READ (FMT_0_ADD), FULL (mul), FAST (mul) };
+static DECODE decode_mulhi_a = { M32R_INSN_MULHI_A, & ITAB (M32R_INSN_MULHI_A), EX (fmt_35_mulhi_a), READ (FMT_35_MULHI_A), FULL (mulhi_a), FAST (mulhi_a) };
+static DECODE decode_mullo_a = { M32R_INSN_MULLO_A, & ITAB (M32R_INSN_MULLO_A), EX (fmt_35_mulhi_a), READ (FMT_35_MULHI_A), FULL (mullo_a), FAST (mullo_a) };
+static DECODE decode_mv = { M32R_INSN_MV, & ITAB (M32R_INSN_MV), EX (fmt_36_mv), READ (FMT_36_MV), FULL (mv), FAST (mv) };
+static DECODE decode_mvfachi_a = { M32R_INSN_MVFACHI_A, & ITAB (M32R_INSN_MVFACHI_A), EX (fmt_37_mvfachi_a), READ (FMT_37_MVFACHI_A), FULL (mvfachi_a), FAST (mvfachi_a) };
+static DECODE decode_mvfaclo_a = { M32R_INSN_MVFACLO_A, & ITAB (M32R_INSN_MVFACLO_A), EX (fmt_37_mvfachi_a), READ (FMT_37_MVFACHI_A), FULL (mvfaclo_a), FAST (mvfaclo_a) };
+static DECODE decode_mvfacmi_a = { M32R_INSN_MVFACMI_A, & ITAB (M32R_INSN_MVFACMI_A), EX (fmt_37_mvfachi_a), READ (FMT_37_MVFACHI_A), FULL (mvfacmi_a), FAST (mvfacmi_a) };
+static DECODE decode_mvfc = { M32R_INSN_MVFC, & ITAB (M32R_INSN_MVFC), EX (fmt_38_mvfc), READ (FMT_38_MVFC), FULL (mvfc), FAST (mvfc) };
+static DECODE decode_mvtachi_a = { M32R_INSN_MVTACHI_A, & ITAB (M32R_INSN_MVTACHI_A), EX (fmt_39_mvtachi_a), READ (FMT_39_MVTACHI_A), FULL (mvtachi_a), FAST (mvtachi_a) };
+static DECODE decode_mvtaclo_a = { M32R_INSN_MVTACLO_A, & ITAB (M32R_INSN_MVTACLO_A), EX (fmt_39_mvtachi_a), READ (FMT_39_MVTACHI_A), FULL (mvtaclo_a), FAST (mvtaclo_a) };
+static DECODE decode_mvtc = { M32R_INSN_MVTC, & ITAB (M32R_INSN_MVTC), EX (fmt_40_mvtc), READ (FMT_40_MVTC), FULL (mvtc), FAST (mvtc) };
+static DECODE decode_neg = { M32R_INSN_NEG, & ITAB (M32R_INSN_NEG), EX (fmt_36_mv), READ (FMT_36_MV), FULL (neg), FAST (neg) };
+static DECODE decode_nop = { M32R_INSN_NOP, & ITAB (M32R_INSN_NOP), EX (fmt_41_nop), READ (FMT_41_NOP), FULL (nop), FAST (nop) };
+static DECODE decode_not = { M32R_INSN_NOT, & ITAB (M32R_INSN_NOT), EX (fmt_36_mv), READ (FMT_36_MV), FULL (not), FAST (not) };
+static DECODE decode_rac_d = { M32R_INSN_RAC_D, & ITAB (M32R_INSN_RAC_D), EX (fmt_42_rac_d), READ (FMT_42_RAC_D), FULL (rac_d), FAST (rac_d) };
+static DECODE decode_rac_ds = { M32R_INSN_RAC_DS, & ITAB (M32R_INSN_RAC_DS), EX (fmt_43_rac_ds), READ (FMT_43_RAC_DS), FULL (rac_ds), FAST (rac_ds) };
+static DECODE decode_rac_dsi = { M32R_INSN_RAC_DSI, & ITAB (M32R_INSN_RAC_DSI), EX (fmt_44_rac_dsi), READ (FMT_44_RAC_DSI), FULL (rac_dsi), FAST (rac_dsi) };
+static DECODE decode_rach_d = { M32R_INSN_RACH_D, & ITAB (M32R_INSN_RACH_D), EX (fmt_42_rac_d), READ (FMT_42_RAC_D), FULL (rach_d), FAST (rach_d) };
+static DECODE decode_rach_ds = { M32R_INSN_RACH_DS, & ITAB (M32R_INSN_RACH_DS), EX (fmt_43_rac_ds), READ (FMT_43_RAC_DS), FULL (rach_ds), FAST (rach_ds) };
+static DECODE decode_rach_dsi = { M32R_INSN_RACH_DSI, & ITAB (M32R_INSN_RACH_DSI), EX (fmt_44_rac_dsi), READ (FMT_44_RAC_DSI), FULL (rach_dsi), FAST (rach_dsi) };
+static DECODE decode_rte = { M32R_INSN_RTE, & ITAB (M32R_INSN_RTE), EX (fmt_45_rte), READ (FMT_45_RTE), FULL (rte), FAST (rte) };
+static DECODE decode_seth = { M32R_INSN_SETH, & ITAB (M32R_INSN_SETH), EX (fmt_46_seth), READ (FMT_46_SETH), FULL (seth), FAST (seth) };
+static DECODE decode_sll = { M32R_INSN_SLL, & ITAB (M32R_INSN_SLL), EX (fmt_0_add), READ (FMT_0_ADD), FULL (sll), FAST (sll) };
+static DECODE decode_sll3 = { M32R_INSN_SLL3, & ITAB (M32R_INSN_SLL3), EX (fmt_5_addv3), READ (FMT_5_ADDV3), FULL (sll3), FAST (sll3) };
+static DECODE decode_slli = { M32R_INSN_SLLI, & ITAB (M32R_INSN_SLLI), EX (fmt_47_slli), READ (FMT_47_SLLI), FULL (slli), FAST (slli) };
+static DECODE decode_sra = { M32R_INSN_SRA, & ITAB (M32R_INSN_SRA), EX (fmt_0_add), READ (FMT_0_ADD), FULL (sra), FAST (sra) };
+static DECODE decode_sra3 = { M32R_INSN_SRA3, & ITAB (M32R_INSN_SRA3), EX (fmt_5_addv3), READ (FMT_5_ADDV3), FULL (sra3), FAST (sra3) };
+static DECODE decode_srai = { M32R_INSN_SRAI, & ITAB (M32R_INSN_SRAI), EX (fmt_47_slli), READ (FMT_47_SLLI), FULL (srai), FAST (srai) };
+static DECODE decode_srl = { M32R_INSN_SRL, & ITAB (M32R_INSN_SRL), EX (fmt_0_add), READ (FMT_0_ADD), FULL (srl), FAST (srl) };
+static DECODE decode_srl3 = { M32R_INSN_SRL3, & ITAB (M32R_INSN_SRL3), EX (fmt_5_addv3), READ (FMT_5_ADDV3), FULL (srl3), FAST (srl3) };
+static DECODE decode_srli = { M32R_INSN_SRLI, & ITAB (M32R_INSN_SRLI), EX (fmt_47_slli), READ (FMT_47_SLLI), FULL (srli), FAST (srli) };
+static DECODE decode_st = { M32R_INSN_ST, & ITAB (M32R_INSN_ST), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (st), FAST (st) };
+static DECODE decode_st_d = { M32R_INSN_ST_D, & ITAB (M32R_INSN_ST_D), EX (fmt_48_st_d), READ (FMT_48_ST_D), FULL (st_d), FAST (st_d) };
+static DECODE decode_stb = { M32R_INSN_STB, & ITAB (M32R_INSN_STB), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (stb), FAST (stb) };
+static DECODE decode_stb_d = { M32R_INSN_STB_D, & ITAB (M32R_INSN_STB_D), EX (fmt_48_st_d), READ (FMT_48_ST_D), FULL (stb_d), FAST (stb_d) };
+static DECODE decode_sth = { M32R_INSN_STH, & ITAB (M32R_INSN_STH), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (sth), FAST (sth) };
+static DECODE decode_sth_d = { M32R_INSN_STH_D, & ITAB (M32R_INSN_STH_D), EX (fmt_48_st_d), READ (FMT_48_ST_D), FULL (sth_d), FAST (sth_d) };
+static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & ITAB (M32R_INSN_ST_PLUS), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (st_plus), FAST (st_plus) };
+static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & ITAB (M32R_INSN_ST_MINUS), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (st_minus), FAST (st_minus) };
+static DECODE decode_sub = { M32R_INSN_SUB, & ITAB (M32R_INSN_SUB), EX (fmt_0_add), READ (FMT_0_ADD), FULL (sub), FAST (sub) };
+static DECODE decode_subv = { M32R_INSN_SUBV, & ITAB (M32R_INSN_SUBV), EX (fmt_0_add), READ (FMT_0_ADD), FULL (subv), FAST (subv) };
+static DECODE decode_subx = { M32R_INSN_SUBX, & ITAB (M32R_INSN_SUBX), EX (fmt_6_addx), READ (FMT_6_ADDX), FULL (subx), FAST (subx) };
+static DECODE decode_trap = { M32R_INSN_TRAP, & ITAB (M32R_INSN_TRAP), EX (fmt_49_trap), READ (FMT_49_TRAP), FULL (trap), FAST (trap) };
+static DECODE decode_unlock = { M32R_INSN_UNLOCK, & ITAB (M32R_INSN_UNLOCK), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (unlock), FAST (unlock) };
+static DECODE decode_satb = { M32R_INSN_SATB, & ITAB (M32R_INSN_SATB), EX (fmt_50_satb), READ (FMT_50_SATB), FULL (satb), FAST (satb) };
+static DECODE decode_sath = { M32R_INSN_SATH, & ITAB (M32R_INSN_SATH), EX (fmt_50_satb), READ (FMT_50_SATB), FULL (sath), FAST (sath) };
+static DECODE decode_sat = { M32R_INSN_SAT, & ITAB (M32R_INSN_SAT), EX (fmt_51_sat), READ (FMT_51_SAT), FULL (sat), FAST (sat) };
+static DECODE decode_pcmpbz = { M32R_INSN_PCMPBZ, & ITAB (M32R_INSN_PCMPBZ), EX (fmt_20_cmpz), READ (FMT_20_CMPZ), FULL (pcmpbz), FAST (pcmpbz) };
+static DECODE decode_sadd = { M32R_INSN_SADD, & ITAB (M32R_INSN_SADD), EX (fmt_52_sadd), READ (FMT_52_SADD), FULL (sadd), FAST (sadd) };
+static DECODE decode_macwu1 = { M32R_INSN_MACWU1, & ITAB (M32R_INSN_MACWU1), EX (fmt_53_macwu1), READ (FMT_53_MACWU1), FULL (macwu1), FAST (macwu1) };
+static DECODE decode_msblo = { M32R_INSN_MSBLO, & ITAB (M32R_INSN_MSBLO), EX (fmt_54_msblo), READ (FMT_54_MSBLO), FULL (msblo), FAST (msblo) };
+static DECODE decode_mulwu1 = { M32R_INSN_MULWU1, & ITAB (M32R_INSN_MULWU1), EX (fmt_17_cmp), READ (FMT_17_CMP), FULL (mulwu1), FAST (mulwu1) };
+static DECODE decode_maclh1 = { M32R_INSN_MACLH1, & ITAB (M32R_INSN_MACLH1), EX (fmt_53_macwu1), READ (FMT_53_MACWU1), FULL (maclh1), FAST (maclh1) };
+static DECODE decode_sc = { M32R_INSN_SC, & ITAB (M32R_INSN_SC), EX (fmt_55_sc), READ (FMT_55_SC), FULL (sc), FAST (sc) };
+static DECODE decode_snc = { M32R_INSN_SNC, & ITAB (M32R_INSN_SNC), EX (fmt_55_sc), READ (FMT_55_SC), FULL (snc), FAST (snc) };
+

 DECODE m32rx_decode_illegal = {
 DECODE m32rx_decode_illegal = {

-  M32R_INSN_ILLEGAL, & m32r_cgen_insn_table_entries[0],
-  EX (illegal), FULL (illegal),
-  FAST (illegal)
+  M32R_INSN_ILLEGAL, & ITAB (M32R_INSN_ILLEGAL),
+  EX (illegal), FULL (illegal), FAST (illegal)

 };
 
 };
 

-/* The order must match that of `labels' in sem-switch.c.  */
+/* The order must match that of `labels' in sem-switch.c/read.c.  */

 
 DECODE *m32rx_decode_vars[] = {
   & m32rx_decode_illegal,
 
 DECODE *m32rx_decode_vars[] = {
   & m32rx_decode_illegal,


@@ -228,6 +243,7 @@ DECODE *m32rx_decode_vars[] = {
   & decode_divu,
   & decode_rem,
   & decode_remu,
   & decode_divu,
   & decode_rem,
   & decode_remu,

+  & decode_divh,

   & decode_jc,
   & decode_jnc,
   & decode_jl,
   & decode_jc,
   & decode_jnc,
   & decode_jl,


@@ -263,8 +279,12 @@ DECODE *m32rx_decode_vars[] = {
   & decode_neg,
   & decode_nop,
   & decode_not,
   & decode_neg,
   & decode_nop,
   & decode_not,

-  & decode_rac_a,
-  & decode_rach_a,
+  & decode_rac_d,
+  & decode_rac_ds,
+  & decode_rac_dsi,
+  & decode_rach_d,
+  & decode_rach_ds,
+  & decode_rach_dsi,

   & decode_rte,
   & decode_seth,
   & decode_sll,
   & decode_rte,
   & decode_seth,
   & decode_sll,


@@ -297,7 +317,7 @@ DECODE *m32rx_decode_vars[] = {
   & decode_macwu1,
   & decode_msblo,
   & decode_mulwu1,
   & decode_macwu1,
   & decode_msblo,
   & decode_mulwu1,

-  & decode_machl1,
+  & decode_maclh1,

   & decode_sc,
   & decode_snc,
   0
   & decode_sc,
   & decode_snc,
   0


@@ -343,7 +363,7 @@ m32rx_decode (current_cpu, pc, insn)
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && case_0_87, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && case_0_87, 

-      && default_0, && default_0, && default_0, && default_0, 
+      && case_0_88, && case_0_89, && default_0, && default_0, 

       && default_0, && default_0, && default_0, && case_0_95, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && case_0_95, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 


@@ -357,7 +377,7 @@ m32rx_decode (current_cpu, pc, insn)
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 

-      && default_0, && default_0, && default_0, && default_0, 
+      && case_0_144, && default_0, && default_0, && default_0, 

       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 
       && default_0, && default_0, && default_0, && default_0, 


@@ -410,8 +430,8 @@ m32rx_decode (current_cpu, pc, insn)
       &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
       &decode_srli, &decode_srli, &decode_srai, &decode_srai, 
       &decode_slli, &decode_slli, &decode_illegal, 0, 
       &decode_addi, &decode_addi, &decode_addi, &decode_addi, 
       &decode_srli, &decode_srli, &decode_srai, &decode_srai, 
       &decode_slli, &decode_slli, &decode_illegal, 0, 

-      &decode_rach_a, &decode_rac_a, &decode_mulwu1, &decode_macwu1, 
-      &decode_machl1, &decode_msblo, &decode_sadd, 0, 
+      0, 0, &decode_mulwu1, &decode_macwu1, 
+      &decode_maclh1, &decode_msblo, &decode_sadd, 0, 

       &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
       &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
       &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
       &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
       &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 
       &decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8, 


@@ -424,7 +444,7 @@ m32rx_decode (current_cpu, pc, insn)
       &decode_cmpi, &decode_cmpui, &decode_illegal, &decode_illegal, 
       &decode_addv3, &decode_illegal, &decode_add3, &decode_illegal, 
       &decode_and3, &decode_xor3, &decode_or3, &decode_illegal, 
       &decode_cmpi, &decode_cmpui, &decode_illegal, &decode_illegal, 
       &decode_addv3, &decode_illegal, &decode_add3, &decode_illegal, 
       &decode_and3, &decode_xor3, &decode_or3, &decode_illegal, 

-      &decode_div, &decode_divu, &decode_rem, &decode_remu, 
+      0, &decode_divu, &decode_rem, &decode_remu, 

       &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
       &decode_srl3, &decode_illegal, &decode_sra3, &decode_illegal, 
       &decode_sll3, &decode_illegal, &decode_illegal, &decode_ldi16, 
       &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
       &decode_srl3, &decode_illegal, &decode_sra3, &decode_illegal, 
       &decode_sll3, &decode_illegal, &decode_illegal, &decode_ldi16, 


@@ -487,6 +507,90 @@ m32rx_decode (current_cpu, pc, insn)
           unsigned int val = (((insn >> 0) & (3 << 0)));
           return insns[val];
         }
           unsigned int val = (((insn >> 0) & (3 << 0)));
           return insns[val];
         }

+      CASE (0, 88) :
+        {
+#ifdef __GNUC__
+          static void *labels_0_88[16] = {
+            && case_0_88_0, && case_0_88_1, && case_0_88_2, && case_0_88_3, 
+            && default_0_88, && default_0_88, && default_0_88, && default_0_88, 
+            && default_0_88, && default_0_88, && default_0_88, && default_0_88, 
+            && default_0_88, && default_0_88, && default_0_88, && default_0_88, 
+          };
+#endif
+          static DECODE *insns[16] = {
+            0, 0, 0, 0, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+          };
+          unsigned int val;
+          val = (((insn >> 6) & (3 << 2)) | ((insn >> 2) & (3 << 0)));
+          DECODE_SWITCH (0_88, val)
+            {
+            CASE (0_88, 0) :
+              {
+                static DECODE *insns[4] = {
+                  &decode_rach_d, &decode_rach_dsi, &decode_illegal, &decode_illegal, 
+                };
+                unsigned int val = (((insn >> 0) & (3 << 0)));
+                return insns[val];
+              }
+            CASE (0_88, 1) : /* fall through */
+            CASE (0_88, 2) : /* fall through */
+            CASE (0_88, 3) :
+              {
+                static DECODE *insns[4] = {
+                  &decode_rach_ds, &decode_rach_dsi, &decode_illegal, &decode_illegal, 
+                };
+                unsigned int val = (((insn >> 0) & (3 << 0)));
+                return insns[val];
+              }
+            DEFAULT (0_88) : return insns[val];
+            }
+          ENDSWITCH (0_88)
+        }
+      CASE (0, 89) :
+        {
+#ifdef __GNUC__
+          static void *labels_0_89[16] = {
+            && case_0_89_0, && case_0_89_1, && case_0_89_2, && case_0_89_3, 
+            && default_0_89, && default_0_89, && default_0_89, && default_0_89, 
+            && default_0_89, && default_0_89, && default_0_89, && default_0_89, 
+            && default_0_89, && default_0_89, && default_0_89, && default_0_89, 
+          };
+#endif
+          static DECODE *insns[16] = {
+            0, 0, 0, 0, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+          };
+          unsigned int val;
+          val = (((insn >> 6) & (3 << 2)) | ((insn >> 2) & (3 << 0)));
+          DECODE_SWITCH (0_89, val)
+            {
+            CASE (0_89, 0) :
+              {
+                static DECODE *insns[4] = {
+                  &decode_rac_d, &decode_rac_dsi, &decode_illegal, &decode_illegal, 
+                };
+                unsigned int val = (((insn >> 0) & (3 << 0)));
+                return insns[val];
+              }
+            CASE (0_89, 1) : /* fall through */
+            CASE (0_89, 2) : /* fall through */
+            CASE (0_89, 3) :
+              {
+                static DECODE *insns[4] = {
+                  &decode_rac_ds, &decode_rac_dsi, &decode_illegal, &decode_illegal, 
+                };
+                unsigned int val = (((insn >> 0) & (3 << 0)));
+                return insns[val];
+              }
+            DEFAULT (0_89) : return insns[val];
+            }
+          ENDSWITCH (0_89)
+        }

       CASE (0, 95) :
         {
           static DECODE *insns[4] = {
       CASE (0, 95) :
         {
           static DECODE *insns[4] = {


@@ -568,6 +672,67 @@ m32rx_decode (current_cpu, pc, insn)
             }
           ENDSWITCH (0_128)
         }
             }
           ENDSWITCH (0_128)
         }

+      CASE (0, 144) :
+        {
+#ifdef __GNUC__
+          static void *labels_0_144[16] = {
+            && case_0_144_0, && default_0_144, && default_0_144, && default_0_144, 
+            && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
+            && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
+            && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
+          };
+#endif
+          static DECODE *insns[16] = {
+            0, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+            &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+          };
+          unsigned int val;
+          /* Must fetch more bits.  */
+          insn = GETIMEMUHI (current_cpu, CPU (h_pc) + 2);
+          val = (((insn >> 12) & (15 << 0)));
+          DECODE_SWITCH (0_144, val)
+            {
+            CASE (0_144, 0) :
+              {
+#ifdef __GNUC__
+                static void *labels_0_144_0[16] = {
+                  && case_0_144_0_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
+                  && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
+                  && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
+                  && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
+                };
+#endif
+                static DECODE *insns[16] = {
+                  0, &decode_illegal, &decode_illegal, &decode_illegal, 
+                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                  &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                };
+                unsigned int val;
+                val = (((insn >> 8) & (15 << 0)));
+                DECODE_SWITCH (0_144_0, val)
+                  {
+                  CASE (0_144_0, 0) :
+                    {
+                      static DECODE *insns[16] = {
+                        &decode_div, &decode_divh, &decode_illegal, &decode_illegal, 
+                        &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                        &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                        &decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal, 
+                      };
+                      unsigned int val = (((insn >> 4) & (15 << 0)));
+                      return insns[val];
+                    }
+                  DEFAULT (0_144_0) : return insns[val];
+                  }
+                ENDSWITCH (0_144_0)
+              }
+            DEFAULT (0_144) : return insns[val];
+            }
+          ENDSWITCH (0_144)
+        }

       CASE (0, 240) : /* fall through */
       CASE (0, 241) : /* fall through */
       CASE (0, 242) : /* fall through */
       CASE (0, 240) : /* fall through */
       CASE (0, 241) : /* fall through */
       CASE (0, 242) : /* fall through */

diff --git a/sim/m32r/decodex.h b/sim/m32r/decodex.h
new file mode 100644 (file)
index 0000000..a8b4f41
--- /dev/null
+++ b/sim/m32r/decodex.h
@@ -0,0 +1,336 @@
+/* Decode header for m32rx.
+
+This file is machine generated with CGEN.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef M32RX_DECODE_H
+#define M32RX_DECODE_H
+
+#define EX(fn) XCONCAT3 (m32rx,_ex_,fn)
+#define SEM(fn) XCONCAT3 (m32rx,_sem_,fn)
+#define SEMC(fn) XCONCAT3 (m32rx,_semc_,fn)
+
+extern EXTRACT_FN EX (illegal);
+extern SEMANTIC_FN SEM (illegal);
+extern SEMANTIC_CACHE_FN SEMC (illegal);
+
+extern EXTRACT_FN EX (fmt_0_add);
+extern EXTRACT_FN EX (fmt_1_add3);
+extern EXTRACT_FN EX (fmt_2_and3);
+extern EXTRACT_FN EX (fmt_3_or3);
+extern EXTRACT_FN EX (fmt_4_addi);
+extern EXTRACT_FN EX (fmt_5_addv3);
+extern EXTRACT_FN EX (fmt_6_addx);
+extern EXTRACT_FN EX (fmt_7_bc8);
+extern EXTRACT_FN EX (fmt_8_bc24);
+extern EXTRACT_FN EX (fmt_9_beq);
+extern EXTRACT_FN EX (fmt_10_beqz);
+extern EXTRACT_FN EX (fmt_11_bl8);
+extern EXTRACT_FN EX (fmt_12_bl24);
+extern EXTRACT_FN EX (fmt_13_bcl8);
+extern EXTRACT_FN EX (fmt_14_bcl24);
+extern EXTRACT_FN EX (fmt_15_bra8);
+extern EXTRACT_FN EX (fmt_16_bra24);
+extern EXTRACT_FN EX (fmt_17_cmp);
+extern EXTRACT_FN EX (fmt_18_cmpi);
+extern EXTRACT_FN EX (fmt_19_cmpui);
+extern EXTRACT_FN EX (fmt_20_cmpz);
+extern EXTRACT_FN EX (fmt_21_div);
+extern EXTRACT_FN EX (fmt_22_jc);
+extern EXTRACT_FN EX (fmt_23_jl);
+extern EXTRACT_FN EX (fmt_24_jmp);
+extern EXTRACT_FN EX (fmt_25_ld);
+extern EXTRACT_FN EX (fmt_26_ld_d);
+extern EXTRACT_FN EX (fmt_27_ldb);
+extern EXTRACT_FN EX (fmt_28_ldb_d);
+extern EXTRACT_FN EX (fmt_29_ldh);
+extern EXTRACT_FN EX (fmt_30_ldh_d);
+extern EXTRACT_FN EX (fmt_31_ld24);
+extern EXTRACT_FN EX (fmt_32_ldi8);
+extern EXTRACT_FN EX (fmt_33_ldi16);
+extern EXTRACT_FN EX (fmt_34_machi_a);
+extern EXTRACT_FN EX (fmt_35_mulhi_a);
+extern EXTRACT_FN EX (fmt_36_mv);
+extern EXTRACT_FN EX (fmt_37_mvfachi_a);
+extern EXTRACT_FN EX (fmt_38_mvfc);
+extern EXTRACT_FN EX (fmt_39_mvtachi_a);
+extern EXTRACT_FN EX (fmt_40_mvtc);
+extern EXTRACT_FN EX (fmt_41_nop);
+extern EXTRACT_FN EX (fmt_42_rac_d);
+extern EXTRACT_FN EX (fmt_43_rac_ds);
+extern EXTRACT_FN EX (fmt_44_rac_dsi);
+extern EXTRACT_FN EX (fmt_45_rte);
+extern EXTRACT_FN EX (fmt_46_seth);
+extern EXTRACT_FN EX (fmt_47_slli);
+extern EXTRACT_FN EX (fmt_48_st_d);
+extern EXTRACT_FN EX (fmt_49_trap);
+extern EXTRACT_FN EX (fmt_50_satb);
+extern EXTRACT_FN EX (fmt_51_sat);
+extern EXTRACT_FN EX (fmt_52_sadd);
+extern EXTRACT_FN EX (fmt_53_macwu1);
+extern EXTRACT_FN EX (fmt_54_msblo);
+extern EXTRACT_FN EX (fmt_55_sc);
+
+extern SEMANTIC_FN SEM (add);
+extern SEMANTIC_CACHE_FN SEMC (add);
+extern SEMANTIC_FN SEM (add3);
+extern SEMANTIC_CACHE_FN SEMC (add3);
+extern SEMANTIC_FN SEM (and);
+extern SEMANTIC_CACHE_FN SEMC (and);
+extern SEMANTIC_FN SEM (and3);
+extern SEMANTIC_CACHE_FN SEMC (and3);
+extern SEMANTIC_FN SEM (or);
+extern SEMANTIC_CACHE_FN SEMC (or);
+extern SEMANTIC_FN SEM (or3);
+extern SEMANTIC_CACHE_FN SEMC (or3);
+extern SEMANTIC_FN SEM (xor);
+extern SEMANTIC_CACHE_FN SEMC (xor);
+extern SEMANTIC_FN SEM (xor3);
+extern SEMANTIC_CACHE_FN SEMC (xor3);
+extern SEMANTIC_FN SEM (addi);
+extern SEMANTIC_CACHE_FN SEMC (addi);
+extern SEMANTIC_FN SEM (addv);
+extern SEMANTIC_CACHE_FN SEMC (addv);
+extern SEMANTIC_FN SEM (addv3);
+extern SEMANTIC_CACHE_FN SEMC (addv3);
+extern SEMANTIC_FN SEM (addx);
+extern SEMANTIC_CACHE_FN SEMC (addx);
+extern SEMANTIC_FN SEM (bc8);
+extern SEMANTIC_CACHE_FN SEMC (bc8);
+extern SEMANTIC_FN SEM (bc24);
+extern SEMANTIC_CACHE_FN SEMC (bc24);
+extern SEMANTIC_FN SEM (beq);
+extern SEMANTIC_CACHE_FN SEMC (beq);
+extern SEMANTIC_FN SEM (beqz);
+extern SEMANTIC_CACHE_FN SEMC (beqz);
+extern SEMANTIC_FN SEM (bgez);
+extern SEMANTIC_CACHE_FN SEMC (bgez);
+extern SEMANTIC_FN SEM (bgtz);
+extern SEMANTIC_CACHE_FN SEMC (bgtz);
+extern SEMANTIC_FN SEM (blez);
+extern SEMANTIC_CACHE_FN SEMC (blez);
+extern SEMANTIC_FN SEM (bltz);
+extern SEMANTIC_CACHE_FN SEMC (bltz);
+extern SEMANTIC_FN SEM (bnez);
+extern SEMANTIC_CACHE_FN SEMC (bnez);
+extern SEMANTIC_FN SEM (bl8);
+extern SEMANTIC_CACHE_FN SEMC (bl8);
+extern SEMANTIC_FN SEM (bl24);
+extern SEMANTIC_CACHE_FN SEMC (bl24);
+extern SEMANTIC_FN SEM (bcl8);
+extern SEMANTIC_CACHE_FN SEMC (bcl8);
+extern SEMANTIC_FN SEM (bcl24);
+extern SEMANTIC_CACHE_FN SEMC (bcl24);
+extern SEMANTIC_FN SEM (bnc8);
+extern SEMANTIC_CACHE_FN SEMC (bnc8);
+extern SEMANTIC_FN SEM (bnc24);
+extern SEMANTIC_CACHE_FN SEMC (bnc24);
+extern SEMANTIC_FN SEM (bne);
+extern SEMANTIC_CACHE_FN SEMC (bne);
+extern SEMANTIC_FN SEM (bra8);
+extern SEMANTIC_CACHE_FN SEMC (bra8);
+extern SEMANTIC_FN SEM (bra24);
+extern SEMANTIC_CACHE_FN SEMC (bra24);
+extern SEMANTIC_FN SEM (bncl8);
+extern SEMANTIC_CACHE_FN SEMC (bncl8);
+extern SEMANTIC_FN SEM (bncl24);
+extern SEMANTIC_CACHE_FN SEMC (bncl24);
+extern SEMANTIC_FN SEM (cmp);
+extern SEMANTIC_CACHE_FN SEMC (cmp);
+extern SEMANTIC_FN SEM (cmpi);
+extern SEMANTIC_CACHE_FN SEMC (cmpi);
+extern SEMANTIC_FN SEM (cmpu);
+extern SEMANTIC_CACHE_FN SEMC (cmpu);
+extern SEMANTIC_FN SEM (cmpui);
+extern SEMANTIC_CACHE_FN SEMC (cmpui);
+extern SEMANTIC_FN SEM (cmpeq);
+extern SEMANTIC_CACHE_FN SEMC (cmpeq);
+extern SEMANTIC_FN SEM (cmpz);
+extern SEMANTIC_CACHE_FN SEMC (cmpz);
+extern SEMANTIC_FN SEM (div);
+extern SEMANTIC_CACHE_FN SEMC (div);
+extern SEMANTIC_FN SEM (divu);
+extern SEMANTIC_CACHE_FN SEMC (divu);
+extern SEMANTIC_FN SEM (rem);
+extern SEMANTIC_CACHE_FN SEMC (rem);
+extern SEMANTIC_FN SEM (remu);
+extern SEMANTIC_CACHE_FN SEMC (remu);
+extern SEMANTIC_FN SEM (divh);
+extern SEMANTIC_CACHE_FN SEMC (divh);
+extern SEMANTIC_FN SEM (jc);
+extern SEMANTIC_CACHE_FN SEMC (jc);
+extern SEMANTIC_FN SEM (jnc);
+extern SEMANTIC_CACHE_FN SEMC (jnc);
+extern SEMANTIC_FN SEM (jl);
+extern SEMANTIC_CACHE_FN SEMC (jl);
+extern SEMANTIC_FN SEM (jmp);
+extern SEMANTIC_CACHE_FN SEMC (jmp);
+extern SEMANTIC_FN SEM (ld);
+extern SEMANTIC_CACHE_FN SEMC (ld);
+extern SEMANTIC_FN SEM (ld_d);
+extern SEMANTIC_CACHE_FN SEMC (ld_d);
+extern SEMANTIC_FN SEM (ldb);
+extern SEMANTIC_CACHE_FN SEMC (ldb);
+extern SEMANTIC_FN SEM (ldb_d);
+extern SEMANTIC_CACHE_FN SEMC (ldb_d);
+extern SEMANTIC_FN SEM (ldh);
+extern SEMANTIC_CACHE_FN SEMC (ldh);
+extern SEMANTIC_FN SEM (ldh_d);
+extern SEMANTIC_CACHE_FN SEMC (ldh_d);
+extern SEMANTIC_FN SEM (ldub);
+extern SEMANTIC_CACHE_FN SEMC (ldub);
+extern SEMANTIC_FN SEM (ldub_d);
+extern SEMANTIC_CACHE_FN SEMC (ldub_d);
+extern SEMANTIC_FN SEM (lduh);
+extern SEMANTIC_CACHE_FN SEMC (lduh);
+extern SEMANTIC_FN SEM (lduh_d);
+extern SEMANTIC_CACHE_FN SEMC (lduh_d);
+extern SEMANTIC_FN SEM (ld_plus);
+extern SEMANTIC_CACHE_FN SEMC (ld_plus);
+extern SEMANTIC_FN SEM (ld24);
+extern SEMANTIC_CACHE_FN SEMC (ld24);
+extern SEMANTIC_FN SEM (ldi8);
+extern SEMANTIC_CACHE_FN SEMC (ldi8);
+extern SEMANTIC_FN SEM (ldi16);
+extern SEMANTIC_CACHE_FN SEMC (ldi16);
+extern SEMANTIC_FN SEM (lock);
+extern SEMANTIC_CACHE_FN SEMC (lock);
+extern SEMANTIC_FN SEM (machi_a);
+extern SEMANTIC_CACHE_FN SEMC (machi_a);
+extern SEMANTIC_FN SEM (maclo_a);
+extern SEMANTIC_CACHE_FN SEMC (maclo_a);
+extern SEMANTIC_FN SEM (mul);
+extern SEMANTIC_CACHE_FN SEMC (mul);
+extern SEMANTIC_FN SEM (mulhi_a);
+extern SEMANTIC_CACHE_FN SEMC (mulhi_a);
+extern SEMANTIC_FN SEM (mullo_a);
+extern SEMANTIC_CACHE_FN SEMC (mullo_a);
+extern SEMANTIC_FN SEM (mv);
+extern SEMANTIC_CACHE_FN SEMC (mv);
+extern SEMANTIC_FN SEM (mvfachi_a);
+extern SEMANTIC_CACHE_FN SEMC (mvfachi_a);
+extern SEMANTIC_FN SEM (mvfaclo_a);
+extern SEMANTIC_CACHE_FN SEMC (mvfaclo_a);
+extern SEMANTIC_FN SEM (mvfacmi_a);
+extern SEMANTIC_CACHE_FN SEMC (mvfacmi_a);
+extern SEMANTIC_FN SEM (mvfc);
+extern SEMANTIC_CACHE_FN SEMC (mvfc);
+extern SEMANTIC_FN SEM (mvtachi_a);
+extern SEMANTIC_CACHE_FN SEMC (mvtachi_a);
+extern SEMANTIC_FN SEM (mvtaclo_a);
+extern SEMANTIC_CACHE_FN SEMC (mvtaclo_a);
+extern SEMANTIC_FN SEM (mvtc);
+extern SEMANTIC_CACHE_FN SEMC (mvtc);
+extern SEMANTIC_FN SEM (neg);
+extern SEMANTIC_CACHE_FN SEMC (neg);
+extern SEMANTIC_FN SEM (nop);
+extern SEMANTIC_CACHE_FN SEMC (nop);
+extern SEMANTIC_FN SEM (not);
+extern SEMANTIC_CACHE_FN SEMC (not);
+extern SEMANTIC_FN SEM (rac_d);
+extern SEMANTIC_CACHE_FN SEMC (rac_d);
+extern SEMANTIC_FN SEM (rac_ds);
+extern SEMANTIC_CACHE_FN SEMC (rac_ds);
+extern SEMANTIC_FN SEM (rac_dsi);
+extern SEMANTIC_CACHE_FN SEMC (rac_dsi);
+extern SEMANTIC_FN SEM (rach_d);
+extern SEMANTIC_CACHE_FN SEMC (rach_d);
+extern SEMANTIC_FN SEM (rach_ds);
+extern SEMANTIC_CACHE_FN SEMC (rach_ds);
+extern SEMANTIC_FN SEM (rach_dsi);
+extern SEMANTIC_CACHE_FN SEMC (rach_dsi);
+extern SEMANTIC_FN SEM (rte);
+extern SEMANTIC_CACHE_FN SEMC (rte);
+extern SEMANTIC_FN SEM (seth);
+extern SEMANTIC_CACHE_FN SEMC (seth);
+extern SEMANTIC_FN SEM (sll);
+extern SEMANTIC_CACHE_FN SEMC (sll);
+extern SEMANTIC_FN SEM (sll3);
+extern SEMANTIC_CACHE_FN SEMC (sll3);
+extern SEMANTIC_FN SEM (slli);
+extern SEMANTIC_CACHE_FN SEMC (slli);
+extern SEMANTIC_FN SEM (sra);
+extern SEMANTIC_CACHE_FN SEMC (sra);
+extern SEMANTIC_FN SEM (sra3);
+extern SEMANTIC_CACHE_FN SEMC (sra3);
+extern SEMANTIC_FN SEM (srai);
+extern SEMANTIC_CACHE_FN SEMC (srai);
+extern SEMANTIC_FN SEM (srl);
+extern SEMANTIC_CACHE_FN SEMC (srl);
+extern SEMANTIC_FN SEM (srl3);
+extern SEMANTIC_CACHE_FN SEMC (srl3);
+extern SEMANTIC_FN SEM (srli);
+extern SEMANTIC_CACHE_FN SEMC (srli);
+extern SEMANTIC_FN SEM (st);
+extern SEMANTIC_CACHE_FN SEMC (st);
+extern SEMANTIC_FN SEM (st_d);
+extern SEMANTIC_CACHE_FN SEMC (st_d);
+extern SEMANTIC_FN SEM (stb);
+extern SEMANTIC_CACHE_FN SEMC (stb);
+extern SEMANTIC_FN SEM (stb_d);
+extern SEMANTIC_CACHE_FN SEMC (stb_d);
+extern SEMANTIC_FN SEM (sth);
+extern SEMANTIC_CACHE_FN SEMC (sth);
+extern SEMANTIC_FN SEM (sth_d);
+extern SEMANTIC_CACHE_FN SEMC (sth_d);
+extern SEMANTIC_FN SEM (st_plus);
+extern SEMANTIC_CACHE_FN SEMC (st_plus);
+extern SEMANTIC_FN SEM (st_minus);
+extern SEMANTIC_CACHE_FN SEMC (st_minus);
+extern SEMANTIC_FN SEM (sub);
+extern SEMANTIC_CACHE_FN SEMC (sub);
+extern SEMANTIC_FN SEM (subv);
+extern SEMANTIC_CACHE_FN SEMC (subv);
+extern SEMANTIC_FN SEM (subx);
+extern SEMANTIC_CACHE_FN SEMC (subx);
+extern SEMANTIC_FN SEM (trap);
+extern SEMANTIC_CACHE_FN SEMC (trap);
+extern SEMANTIC_FN SEM (unlock);
+extern SEMANTIC_CACHE_FN SEMC (unlock);
+extern SEMANTIC_FN SEM (satb);
+extern SEMANTIC_CACHE_FN SEMC (satb);
+extern SEMANTIC_FN SEM (sath);
+extern SEMANTIC_CACHE_FN SEMC (sath);
+extern SEMANTIC_FN SEM (sat);
+extern SEMANTIC_CACHE_FN SEMC (sat);
+extern SEMANTIC_FN SEM (pcmpbz);
+extern SEMANTIC_CACHE_FN SEMC (pcmpbz);
+extern SEMANTIC_FN SEM (sadd);
+extern SEMANTIC_CACHE_FN SEMC (sadd);
+extern SEMANTIC_FN SEM (macwu1);
+extern SEMANTIC_CACHE_FN SEMC (macwu1);
+extern SEMANTIC_FN SEM (msblo);
+extern SEMANTIC_CACHE_FN SEMC (msblo);
+extern SEMANTIC_FN SEM (mulwu1);
+extern SEMANTIC_CACHE_FN SEMC (mulwu1);
+extern SEMANTIC_FN SEM (maclh1);
+extern SEMANTIC_CACHE_FN SEMC (maclh1);
+extern SEMANTIC_FN SEM (sc);
+extern SEMANTIC_CACHE_FN SEMC (sc);
+extern SEMANTIC_FN SEM (snc);
+extern SEMANTIC_CACHE_FN SEMC (snc);
+
+#undef EX
+#undef SEM
+#undef SEMC
+
+#endif /* M32RX_DECODE_H */

diff --git a/sim/m32r/model.c b/sim/m32r/model.c
index 7ab18a4..8efca7e 100644 (file)
--- a/sim/m32r/model.c
+++ b/sim/m32r/model.c
@@ -1,5 +1,7 @@
 /* Simulator model support for m32r.
 
 /* Simulator model support for m32r.
 

+This file is machine generated with CGEN.
+

 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of the GNU Simulators.
 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of the GNU Simulators.


@@ -35,7 +37,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* Track function unit usage for an instruction.  */
 
 void
 /* Track function unit usage for an instruction.  */
 
 void

-model_profile_insn (SIM_CPU *current_cpu, ARGBUF *abuf)
+m32r_model_profile_insn (SIM_CPU *current_cpu, ARGBUF *abuf)

 {
   const MODEL *model = CPU_MODEL (current_cpu);
   const INSN_TIMING *timing = MODEL_TIMING (model);
 {
   const MODEL *model = CPU_MODEL (current_cpu);
   const INSN_TIMING *timing = MODEL_TIMING (model);


@@ -72,7 +74,7 @@ model_profile_insn (SIM_CPU *current_cpu, ARGBUF *abuf)
 /* Track function unit usage for an instruction.  */
 
 void
 /* Track function unit usage for an instruction.  */
 
 void

-model_profile_cti_insn (SIM_CPU *current_cpu, ARGBUF *abuf, int taken_p)
+m32r_model_profile_cti_insn (SIM_CPU *current_cpu, ARGBUF *abuf, int taken_p)

 {
   const MODEL *model = CPU_MODEL (current_cpu);
   const INSN_TIMING *timing = MODEL_TIMING (model);
 {
   const MODEL *model = CPU_MODEL (current_cpu);
   const INSN_TIMING *timing = MODEL_TIMING (model);


@@ -120,15 +122,21 @@ static const INSN_TIMING m32r_d_timing[] = {
   { { (UQI) UNIT_NONE } }, /* illegal insn */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* add */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* add3 */
   { { (UQI) UNIT_NONE } }, /* illegal insn */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* add */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* add3 */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* add3.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* and */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* and3 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* and */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* and3 */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* and3.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* or */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* or3 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* or */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* or3 */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* or3.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* xor */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* xor3 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* xor */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* xor3 */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* xor3.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addi */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addi */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addi.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addv */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addv3 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addv */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addv3 */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addv3.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addx */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bc8 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bc8.s */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addx */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bc8 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bc8.s */


@@ -156,38 +164,44 @@ static const INSN_TIMING m32r_d_timing[] = {
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bra24.l */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmp */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpi */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bra24.l */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmp */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpi */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpi.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpu */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpui */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpu */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpui */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpui.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* div */
   { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* div */

-  { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* divu */
+  { { (UQI) UNIT_M32R_D_U_EXEC, 27, 27 } }, /* divu */

   { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* rem */
   { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* rem */

-  { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* remu */
+  { { (UQI) UNIT_M32R_D_U_EXEC, 27, 27 } }, /* remu */
+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* divh */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* jl */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* jmp */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld-2 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* jl */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* jmp */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld-2 */

-  { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld-d */
-  { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld-d2 */
+  { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ld-d */
+  { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ld-d2 */

   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldb */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldb-2 */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldb */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldb-2 */

-  { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldb-d */
-  { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldb-d2 */
+  { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ldb-d */
+  { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ldb-d2 */

   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldh */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldh-2 */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldh */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldh-2 */

-  { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldh-d */
-  { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldh-d2 */
+  { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ldh-d */
+  { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ldh-d2 */

   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldub */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldub-2 */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldub */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldub-2 */

-  { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldub-d */
-  { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldub-d2 */
+  { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ldub-d */
+  { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ldub-d2 */

   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* lduh */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* lduh-2 */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* lduh */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* lduh-2 */

-  { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* lduh-d */
-  { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* lduh-d2 */
+  { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* lduh-d */
+  { { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* lduh-d2 */

   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld-plus */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ld24 */
   { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld-plus */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ld24 */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ld24.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi8 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi8 */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi8.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi8a */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi8a */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi8a.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi16 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi16a */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* lock */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi16 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi16a */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* lock */


@@ -195,7 +209,7 @@ static const INSN_TIMING m32r_d_timing[] = {
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* maclo */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* macwhi */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* macwlo */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* maclo */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* macwhi */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* macwlo */

-  { { (UQI) UNIT_M32R_D_U_EXEC, 3, 3 } }, /* mul */
+  { { (UQI) UNIT_M32R_D_U_EXEC, 4, 4 } }, /* mul */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulhi */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mullo */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulwhi */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulhi */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mullo */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulwhi */


@@ -215,33 +229,41 @@ static const INSN_TIMING m32r_d_timing[] = {
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* rach */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* rte */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* seth */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* rach */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* rte */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* seth */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* seth.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sll */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sll3 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sll */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sll3 */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sll3.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* slli */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* slli */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* slli.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sra */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sra3 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sra */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sra3 */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sra3.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srai */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srai */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srai.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srl */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srl3 */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srl */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srl3 */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srl3.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srli */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srli */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srli.a */

   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st */
   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st-2 */
   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st */
   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st-2 */

-  { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st-d */
-  { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st-d2 */
+  { { (UQI) UNIT_M32R_D_U_STORE, 2, 2 } }, /* st-d */
+  { { (UQI) UNIT_M32R_D_U_STORE, 2, 2 } }, /* st-d2 */

   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* stb */
   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* stb-2 */
   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* stb */
   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* stb-2 */

-  { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* stb-d */
-  { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* stb-d2 */
+  { { (UQI) UNIT_M32R_D_U_STORE, 2, 2 } }, /* stb-d */
+  { { (UQI) UNIT_M32R_D_U_STORE, 2, 2 } }, /* stb-d2 */

   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* sth */
   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* sth-2 */
   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* sth */
   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* sth-2 */

-  { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* sth-d */
-  { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* sth-d2 */
+  { { (UQI) UNIT_M32R_D_U_STORE, 2, 2 } }, /* sth-d */
+  { { (UQI) UNIT_M32R_D_U_STORE, 2, 2 } }, /* sth-d2 */

   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st-plus */
   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st-minus */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sub */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* subv */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* subx */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* trap */
   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st-plus */
   { { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st-minus */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sub */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* subv */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* subx */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* trap */

+  { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* trap.a */

   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* unlock */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* push */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* pop */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* unlock */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* push */
   { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* pop */


@@ -253,15 +275,21 @@ static const INSN_TIMING test_timing[] = {
   { { (UQI) UNIT_NONE } }, /* illegal insn */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* add */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* add3 */
   { { (UQI) UNIT_NONE } }, /* illegal insn */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* add */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* add3 */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* add3.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* and */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* and3 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* and */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* and3 */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* and3.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* or */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* or3 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* or */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* or3 */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* or3.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* xor */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* xor3 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* xor */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* xor3 */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* xor3.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addi */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addi */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addi.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addv */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addv3 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addv */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addv3 */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addv3.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addx */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bc8 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bc8.s */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addx */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bc8 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bc8.s */


@@ -289,12 +317,15 @@ static const INSN_TIMING test_timing[] = {
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bra24.l */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmp */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpi */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bra24.l */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmp */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpi */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpi.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpu */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpui */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpu */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpui */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpui.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* div */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* divu */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rem */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* remu */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* div */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* divu */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rem */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* remu */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* divh */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* jl */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* jmp */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* jl */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* jmp */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld */


@@ -319,8 +350,11 @@ static const INSN_TIMING test_timing[] = {
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* lduh-d2 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld-plus */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld24 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* lduh-d2 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld-plus */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld24 */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld24.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi8 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi8 */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi8.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi8a */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi8a */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi8a.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi16 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi16a */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* lock */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi16 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi16a */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* lock */


@@ -348,15 +382,22 @@ static const INSN_TIMING test_timing[] = {
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rach */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rte */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* seth */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rach */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rte */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* seth */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* seth.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sll */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sll3 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sll */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sll3 */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sll3.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* slli */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* slli */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* slli.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sra */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sra3 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sra */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sra3 */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sra3.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srai */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srai */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srai.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srl */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srl3 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srl */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srl3 */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srl3.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srli */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srli */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srli.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st-2 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st-d */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st-2 */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st-d */


@@ -375,6 +416,7 @@ static const INSN_TIMING test_timing[] = {
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* subv */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* subx */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* trap */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* subv */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* subx */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* trap */

+  { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* trap.a */

   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* unlock */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* push */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* pop */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* unlock */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* push */
   { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* pop */

diff --git a/sim/m32r/modelx.c b/sim/m32r/modelx.c
new file mode 100644 (file)
index 0000000..fda2e48
--- /dev/null
+++ b/sim/m32r/modelx.c
@@ -0,0 +1,291 @@
+/* Simulator model support for m32rx.
+
+This file is machine generated with CGEN.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU
+#define WANT_CPU_M32RX
+
+#include "sim-main.h"
+#include "cpu-sim.h"
+#include "cpu-opc.h"
+
+/* The profiling data is recorded here, but is accessed via the profiling
+   mechanism.  After all, this is information for profiling.  */
+
+#if WITH_PROFILE_MODEL_P
+
+/* Track function unit usage for an instruction.  */
+
+void
+m32rx_model_profile_insn (SIM_CPU *current_cpu, ARGBUF *abuf)
+{
+  const MODEL *model = CPU_MODEL (current_cpu);
+  const INSN_TIMING *timing = MODEL_TIMING (model);
+  const CGEN_INSN *insn = abuf->opcode;
+  const UNIT *unit = &timing[CGEN_INSN_INDEX (insn)].units[0];
+  const UNIT *unit_end = unit + MAX_UNITS;
+  PROFILE_DATA *profile = CPU_PROFILE_DATA (current_cpu);
+
+  do
+    {
+      switch (unit->name)
+        {
+        case UNIT_M32RX_U_EXEC :
+          PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done;
+          break;
+        }
+      ++unit;
+    }
+  while (unit != unit_end && unit->name != UNIT_NONE);
+}
+
+/* Track function unit usage for an instruction.  */
+
+void
+m32rx_model_profile_cti_insn (SIM_CPU *current_cpu, ARGBUF *abuf, int taken_p)
+{
+  const MODEL *model = CPU_MODEL (current_cpu);
+  const INSN_TIMING *timing = MODEL_TIMING (model);
+  const CGEN_INSN *insn = abuf->opcode;
+  const UNIT *unit = &timing[CGEN_INSN_INDEX (insn)].units[0];
+  const UNIT *unit_end = unit + MAX_UNITS;
+  PROFILE_DATA *profile = CPU_PROFILE_DATA (current_cpu);
+
+  do
+    {
+      switch (unit->name)
+        {
+        case UNIT_M32RX_U_EXEC :
+          PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done;
+          break;
+        }
+      if (taken_p)
+        PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
+      else
+        PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
+      ++unit;
+    }
+  while (unit != unit_end && unit->name != UNIT_NONE);
+}
+
+/* We assume UNIT_NONE == 0 because the tables don't always terminate
+   entries with it.  */
+
+/* Model timing data for `m32rx'.  */
+
+static const INSN_TIMING m32rx_timing[] = {
+  { { (UQI) UNIT_NONE } }, /* illegal insn */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* add */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* add3 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* add3.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* and */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* and3 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* and3.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* or */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* or3 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* or3.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* xor */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* xor3 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* xor3.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* addi */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* addi.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* addv */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* addv3 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* addv3.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* addx */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bc8 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bc8.s */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bc24 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bc24.l */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* beq */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* beqz */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bgez */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bgtz */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* blez */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bltz */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bnez */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bl8 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bl8.s */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bl24 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bl24.l */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bcl8 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bcl8.s */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bcl24 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bcl24.l */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bnc8 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bnc8.s */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bnc24 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bnc24.l */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bne */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bra8 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bra8.s */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bra24 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bra24.l */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bncl8 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bncl8.s */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bncl24 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* bncl24.l */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmp */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmpi */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmpi.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmpu */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmpui */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmpui.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmpeq */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* cmpz */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* div */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* divu */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* rem */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* remu */
+  { { (UQI) UNIT_M32RX_U_EXEC, 27, 27 } }, /* divh */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* jc */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* jnc */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* jl */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* jmp */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ld */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ld-2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ld-d */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ld-d2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldb */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldb-2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldb-d */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldb-d2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldh */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldh-2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldh-d */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldh-d2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldub */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldub-2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldub-d */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldub-d2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* lduh */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* lduh-2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* lduh-d */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* lduh-d2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ld-plus */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ld24 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ld24.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldi8 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldi8.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldi8a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldi8a.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldi16 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* ldi16a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* lock */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* machi-a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* maclo-a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mul */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mulhi-a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mullo-a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mv */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mvfachi-a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mvfaclo-a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mvfacmi-a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mvfc */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mvtachi-a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mvtaclo-a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mvtc */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* neg */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* nop */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* not */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* rac-d */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* rac-ds */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* rac-dsi */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* rach-d */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* rach-ds */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* rach-dsi */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* rte */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* seth */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* seth.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sll */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sll3 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sll3.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* slli */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* slli.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sra */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sra3 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sra3.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* srai */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* srai.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* srl */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* srl3 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* srl3.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* srli */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* srli.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* st */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* st-2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* st-d */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* st-d2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* stb */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* stb-2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* stb-d */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* stb-d2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sth */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sth-2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sth-d */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sth-d2 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* st-plus */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* st-minus */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sub */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* subv */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* subx */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* trap */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* trap.a */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* unlock */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* push */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* pop */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* satb */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sath */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sat */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* pcmpbz */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sadd */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* macwu1 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* msblo */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* mulwu1 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* maclh1 */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* sc */
+  { { (UQI) UNIT_M32RX_U_EXEC, 1, 1 } }, /* snc */
+};
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+#if WITH_PROFILE_MODEL_P
+#define TIMING_DATA(td) td
+#else
+#define TIMING_DATA(td) 0
+#endif
+
+const MODEL m32rx_models[] = {
+  { "m32rx", &machs[MACH_M32RX], TIMING_DATA (& m32rx_timing[0]) },
+  { 0 }
+};
+
+/* The properties of this cpu's implementation.  */
+
+const IMP_PROPERTIES m32rx_imp_properties = {
+  sizeof (SIM_CPU)
+#if WITH_SCACHE
+  , sizeof (SCACHE)
+#endif
+};
+

diff --git a/sim/m32r/readx.c b/sim/m32r/readx.c
index ef699ff..2f46e06 100644 (file)
--- a/sim/m32r/readx.c
+++ b/sim/m32r/readx.c
@@ -75,6 +75,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     && case_read_READ_FMT_21_DIV,
     && case_read_READ_FMT_21_DIV,
     && case_read_READ_FMT_21_DIV,
     && case_read_READ_FMT_21_DIV,
     && case_read_READ_FMT_21_DIV,
     && case_read_READ_FMT_21_DIV,

+    && case_read_READ_FMT_21_DIV,

     && case_read_READ_FMT_22_JC,
     && case_read_READ_FMT_22_JC,
     && case_read_READ_FMT_23_JL,
     && case_read_READ_FMT_22_JC,
     && case_read_READ_FMT_22_JC,
     && case_read_READ_FMT_23_JL,


@@ -110,43 +111,47 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     && case_read_READ_FMT_36_MV,
     && case_read_READ_FMT_41_NOP,
     && case_read_READ_FMT_36_MV,
     && case_read_READ_FMT_36_MV,
     && case_read_READ_FMT_41_NOP,
     && case_read_READ_FMT_36_MV,

-    && case_read_READ_FMT_42_RAC_A,
-    && case_read_READ_FMT_42_RAC_A,
-    && case_read_READ_FMT_43_RTE,
-    && case_read_READ_FMT_44_SETH,
+    && case_read_READ_FMT_42_RAC_D,
+    && case_read_READ_FMT_43_RAC_DS,
+    && case_read_READ_FMT_44_RAC_DSI,
+    && case_read_READ_FMT_42_RAC_D,
+    && case_read_READ_FMT_43_RAC_DS,
+    && case_read_READ_FMT_44_RAC_DSI,
+    && case_read_READ_FMT_45_RTE,
+    && case_read_READ_FMT_46_SETH,

     && case_read_READ_FMT_0_ADD,
     && case_read_READ_FMT_5_ADDV3,
     && case_read_READ_FMT_0_ADD,
     && case_read_READ_FMT_5_ADDV3,

-    && case_read_READ_FMT_45_SLLI,
+    && case_read_READ_FMT_47_SLLI,

     && case_read_READ_FMT_0_ADD,
     && case_read_READ_FMT_5_ADDV3,
     && case_read_READ_FMT_0_ADD,
     && case_read_READ_FMT_5_ADDV3,

-    && case_read_READ_FMT_45_SLLI,
+    && case_read_READ_FMT_47_SLLI,

     && case_read_READ_FMT_0_ADD,
     && case_read_READ_FMT_5_ADDV3,
     && case_read_READ_FMT_0_ADD,
     && case_read_READ_FMT_5_ADDV3,

-    && case_read_READ_FMT_45_SLLI,
+    && case_read_READ_FMT_47_SLLI,

     && case_read_READ_FMT_17_CMP,
     && case_read_READ_FMT_17_CMP,

-    && case_read_READ_FMT_46_ST_D,
+    && case_read_READ_FMT_48_ST_D,

     && case_read_READ_FMT_17_CMP,
     && case_read_READ_FMT_17_CMP,

-    && case_read_READ_FMT_46_ST_D,
+    && case_read_READ_FMT_48_ST_D,

     && case_read_READ_FMT_17_CMP,
     && case_read_READ_FMT_17_CMP,

-    && case_read_READ_FMT_46_ST_D,
+    && case_read_READ_FMT_48_ST_D,

     && case_read_READ_FMT_17_CMP,
     && case_read_READ_FMT_17_CMP,
     && case_read_READ_FMT_0_ADD,
     && case_read_READ_FMT_0_ADD,
     && case_read_READ_FMT_6_ADDX,
     && case_read_READ_FMT_17_CMP,
     && case_read_READ_FMT_17_CMP,
     && case_read_READ_FMT_0_ADD,
     && case_read_READ_FMT_0_ADD,
     && case_read_READ_FMT_6_ADDX,

-    && case_read_READ_FMT_47_TRAP,
+    && case_read_READ_FMT_49_TRAP,

     && case_read_READ_FMT_17_CMP,
     && case_read_READ_FMT_17_CMP,

-    && case_read_READ_FMT_48_SATB,
-    && case_read_READ_FMT_48_SATB,
-    && case_read_READ_FMT_49_SAT,
+    && case_read_READ_FMT_50_SATB,
+    && case_read_READ_FMT_50_SATB,
+    && case_read_READ_FMT_51_SAT,

     && case_read_READ_FMT_20_CMPZ,
     && case_read_READ_FMT_20_CMPZ,

-    && case_read_READ_FMT_50_SADD,
-    && case_read_READ_FMT_51_MACWU1,
-    && case_read_READ_FMT_52_MSBLO,
+    && case_read_READ_FMT_52_SADD,
+    && case_read_READ_FMT_53_MACWU1,
+    && case_read_READ_FMT_54_MSBLO,

     && case_read_READ_FMT_17_CMP,
     && case_read_READ_FMT_17_CMP,

-    && case_read_READ_FMT_51_MACWU1,
-    && case_read_READ_FMT_53_SC,
-    && case_read_READ_FMT_53_SC,
+    && case_read_READ_FMT_53_MACWU1,
+    && case_read_READ_FMT_55_SC,
+    && case_read_READ_FMT_55_SC,

     0
   };
   extern DECODE *m32rx_decode_vars[];
     0
   };
   extern DECODE *m32rx_decode_vars[];


@@ -711,23 +716,48 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
     }
     BREAK (read);
 

-    CASE (read, READ_FMT_42_RAC_A) : /* e.g. rac $accs */
+    CASE (read, READ_FMT_42_RAC_D) : /* e.g. rac $accd */
+    {
+#define OPRND(f) par_exec->operands.fmt_42_rac_d.f
+  EXTRACT_FMT_42_RAC_D_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
+  EXTRACT_FMT_42_RAC_D_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (accum) = CPU (h_accum);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_43_RAC_DS) : /* e.g. rac $accd,$accs */
+    {
+#define OPRND(f) par_exec->operands.fmt_43_rac_ds.f
+  EXTRACT_FMT_43_RAC_DS_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
+  EXTRACT_FMT_43_RAC_DS_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_44_RAC_DSI) : /* e.g. rac $accd,$accs,#$imm1 */

     {
     {

-#define OPRND(f) par_exec->operands.fmt_42_rac_a.f
-  EXTRACT_FMT_42_RAC_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
-  EXTRACT_FMT_42_RAC_A_CODE
+#define OPRND(f) par_exec->operands.fmt_44_rac_dsi.f
+  EXTRACT_FMT_44_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
+  EXTRACT_FMT_44_RAC_DSI_CODE

 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);

+      OPRND (imm1) = f_imm1;

 #undef OPRND
     }
     BREAK (read);
 
 #undef OPRND
     }
     BREAK (read);
 

-    CASE (read, READ_FMT_43_RTE) : /* e.g. rte */
+    CASE (read, READ_FMT_45_RTE) : /* e.g. rte */

     {
     {

-#define OPRND(f) par_exec->operands.fmt_43_rte.f
-  EXTRACT_FMT_43_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
-  EXTRACT_FMT_43_RTE_CODE
+#define OPRND(f) par_exec->operands.fmt_45_rte.f
+  EXTRACT_FMT_45_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_45_RTE_CODE

 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (h_bcond_0) = CPU (h_bcond);
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (h_bcond_0) = CPU (h_bcond);


@@ -738,11 +768,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
     }
     BREAK (read);
 

-    CASE (read, READ_FMT_44_SETH) : /* e.g. seth $dr,#$hi16 */
+    CASE (read, READ_FMT_46_SETH) : /* e.g. seth $dr,#$hi16 */

     {
     {

-#define OPRND(f) par_exec->operands.fmt_44_seth.f
-  EXTRACT_FMT_44_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
-  EXTRACT_FMT_44_SETH_CODE
+#define OPRND(f) par_exec->operands.fmt_46_seth.f
+  EXTRACT_FMT_46_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
+  EXTRACT_FMT_46_SETH_CODE

 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (hi16) = f_hi16;
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (hi16) = f_hi16;


@@ -750,11 +780,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
     }
     BREAK (read);
 

-    CASE (read, READ_FMT_45_SLLI) : /* e.g. slli $dr,#$uimm5 */
+    CASE (read, READ_FMT_47_SLLI) : /* e.g. slli $dr,#$uimm5 */

     {
     {

-#define OPRND(f) par_exec->operands.fmt_45_slli.f
-  EXTRACT_FMT_45_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
-  EXTRACT_FMT_45_SLLI_CODE
+#define OPRND(f) par_exec->operands.fmt_47_slli.f
+  EXTRACT_FMT_47_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+  EXTRACT_FMT_47_SLLI_CODE

 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (dr) = CPU (h_gr[f_r1]);
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (dr) = CPU (h_gr[f_r1]);


@@ -763,11 +793,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
     }
     BREAK (read);
 

-    CASE (read, READ_FMT_46_ST_D) : /* e.g. st $src1,@($slo16,$src2) */
+    CASE (read, READ_FMT_48_ST_D) : /* e.g. st $src1,@($slo16,$src2) */

     {
     {

-#define OPRND(f) par_exec->operands.fmt_46_st_d.f
-  EXTRACT_FMT_46_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-  EXTRACT_FMT_46_ST_D_CODE
+#define OPRND(f) par_exec->operands.fmt_48_st_d.f
+  EXTRACT_FMT_48_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_48_ST_D_CODE

 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (slo16) = f_simm16;
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (slo16) = f_simm16;


@@ -777,11 +807,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
     }
     BREAK (read);
 

-    CASE (read, READ_FMT_47_TRAP) : /* e.g. trap #$uimm4 */
+    CASE (read, READ_FMT_49_TRAP) : /* e.g. trap #$uimm4 */

     {
     {

-#define OPRND(f) par_exec->operands.fmt_47_trap.f
-  EXTRACT_FMT_47_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
-  EXTRACT_FMT_47_TRAP_CODE
+#define OPRND(f) par_exec->operands.fmt_49_trap.f
+  EXTRACT_FMT_49_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
+  EXTRACT_FMT_49_TRAP_CODE

 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (uimm4) = f_uimm4;
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (uimm4) = f_uimm4;


@@ -789,11 +819,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
     }
     BREAK (read);
 

-    CASE (read, READ_FMT_48_SATB) : /* e.g. satb $dr,$src2 */
+    CASE (read, READ_FMT_50_SATB) : /* e.g. satb $dr,$src2 */

     {
     {

-#define OPRND(f) par_exec->operands.fmt_48_satb.f
-  EXTRACT_FMT_48_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-  EXTRACT_FMT_48_SATB_CODE
+#define OPRND(f) par_exec->operands.fmt_50_satb.f
+  EXTRACT_FMT_50_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_50_SATB_CODE

 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (src2) = CPU (h_gr[f_r2]);
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (src2) = CPU (h_gr[f_r2]);


@@ -801,11 +831,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
     }
     BREAK (read);
 

-    CASE (read, READ_FMT_49_SAT) : /* e.g. sat $dr,$src2 */
+    CASE (read, READ_FMT_51_SAT) : /* e.g. sat $dr,$src2 */

     {
     {

-#define OPRND(f) par_exec->operands.fmt_49_sat.f
-  EXTRACT_FMT_49_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-  EXTRACT_FMT_49_SAT_CODE
+#define OPRND(f) par_exec->operands.fmt_51_sat.f
+  EXTRACT_FMT_51_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_51_SAT_CODE

 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (condbit) = CPU (h_cond);
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (condbit) = CPU (h_cond);


@@ -814,11 +844,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
     }
     BREAK (read);
 

-    CASE (read, READ_FMT_50_SADD) : /* e.g. sadd */
+    CASE (read, READ_FMT_52_SADD) : /* e.g. sadd */

     {
     {

-#define OPRND(f) par_exec->operands.fmt_50_sadd.f
-  EXTRACT_FMT_50_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-  EXTRACT_FMT_50_SADD_CODE
+#define OPRND(f) par_exec->operands.fmt_52_sadd.f
+  EXTRACT_FMT_52_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_52_SADD_CODE

 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (h_accums_0) = m32rx_h_accums_get (current_cpu, 0);
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (h_accums_0) = m32rx_h_accums_get (current_cpu, 0);


@@ -827,11 +857,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
     }
     BREAK (read);
 

-    CASE (read, READ_FMT_51_MACWU1) : /* e.g. macwu1 $src1,$src2 */
+    CASE (read, READ_FMT_53_MACWU1) : /* e.g. macwu1 $src1,$src2 */

     {
     {

-#define OPRND(f) par_exec->operands.fmt_51_macwu1.f
-  EXTRACT_FMT_51_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
-  EXTRACT_FMT_51_MACWU1_CODE
+#define OPRND(f) par_exec->operands.fmt_53_macwu1.f
+  EXTRACT_FMT_53_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_53_MACWU1_CODE

 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, 1);
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, 1);


@@ -841,11 +871,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
     }
     BREAK (read);
 

-    CASE (read, READ_FMT_52_MSBLO) : /* e.g. msblo $src1,$src2 */
+    CASE (read, READ_FMT_54_MSBLO) : /* e.g. msblo $src1,$src2 */

     {
     {

-#define OPRND(f) par_exec->operands.fmt_52_msblo.f
-  EXTRACT_FMT_52_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */
-  EXTRACT_FMT_52_MSBLO_CODE
+#define OPRND(f) par_exec->operands.fmt_54_msblo.f
+  EXTRACT_FMT_54_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_54_MSBLO_CODE

 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (accum) = CPU (h_accum);
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (accum) = CPU (h_accum);


@@ -855,11 +885,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     }
     BREAK (read);
 
     }
     BREAK (read);
 

-    CASE (read, READ_FMT_53_SC) : /* e.g. sc */
+    CASE (read, READ_FMT_55_SC) : /* e.g. sc */

     {
     {

-#define OPRND(f) par_exec->operands.fmt_53_sc.f
-  EXTRACT_FMT_53_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-  EXTRACT_FMT_53_SC_CODE
+#define OPRND(f) par_exec->operands.fmt_55_sc.f
+  EXTRACT_FMT_55_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_55_SC_CODE

 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (condbit) = CPU (h_cond);
 
       /* Fetch the input operands for the semantic handler.  */
       OPRND (condbit) = CPU (h_cond);

diff --git a/sim/m32r/sem-switch.c b/sim/m32r/sem-switch.c
index 773a6fa..d944096 100644 (file)
--- a/sim/m32r/sem-switch.c
+++ b/sim/m32r/sem-switch.c
@@ -1,5 +1,7 @@
 /* Simulator instruction semantics for m32r.
 
 /* Simulator instruction semantics for m32r.
 

+This file is machine generated with CGEN.
+

 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of the GNU Simulators.
 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of the GNU Simulators.


@@ -23,7 +25,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #ifdef DEFINE_LABELS
 #undef DEFINE_LABELS
 
 #ifdef DEFINE_LABELS
 #undef DEFINE_LABELS
 

-

   /* The labels have the case they have because the enum of insn types
      is all uppercase and in the non-stdc case the insn symbol is built
      into the enum name.
   /* The labels have the case they have because the enum of insn types
      is all uppercase and in the non-stdc case the insn symbol is built
      into the enum name.


@@ -68,6 +69,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
     && case_sem_INSN_DIVU,
     && case_sem_INSN_REM,
     && case_sem_INSN_REMU,
     && case_sem_INSN_DIVU,
     && case_sem_INSN_REM,
     && case_sem_INSN_REMU,

+    && case_sem_INSN_DIVH,

     && case_sem_INSN_JL,
     && case_sem_INSN_JMP,
     && case_sem_INSN_LD,
     && case_sem_INSN_JL,
     && case_sem_INSN_JMP,
     && case_sem_INSN_LD,


@@ -160,7 +162,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 {
   SEM_ARG sem_arg = sc;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 {
   SEM_ARG sem_arg = sc;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);

-  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CIA new_pc;

 
   SWITCH (sem, sem_arg->semantic.sem_case)
     {
 
   SWITCH (sem, sem_arg->semantic.sem_case)
     {


@@ -175,17 +177,23 @@ with this program; if not, write to the Free Software Foundation, Inc.,
   CASE (sem, INSN_ADD) : /* add $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f
   CASE (sem, INSN_ADD) : /* add $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = ADDSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = ADDSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$slo16 */
+  CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,#$slo16 */

 {
 #define FLD(f) abuf->fields.fmt_1_add3.f
 {
 #define FLD(f) abuf->fields.fmt_1_add3.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = ADDSI (* FLD (f_r2), FLD (f_simm16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = ADDSI (* FLD (f_r2), FLD (f_simm16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -193,17 +201,23 @@ with this program; if not, write to the Free Software Foundation, Inc.,
   CASE (sem, INSN_AND) : /* and $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f
   CASE (sem, INSN_AND) : /* and $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = ANDSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = ANDSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
+  CASE (sem, INSN_AND3) : /* and3 $dr,$sr,#$uimm16 */

 {
 #define FLD(f) abuf->fields.fmt_2_and3.f
 {
 #define FLD(f) abuf->fields.fmt_2_and3.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = ANDSI (* FLD (f_r2), FLD (f_uimm16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = ANDSI (* FLD (f_r2), FLD (f_uimm16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -211,17 +225,23 @@ with this program; if not, write to the Free Software Foundation, Inc.,
   CASE (sem, INSN_OR) : /* or $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f
   CASE (sem, INSN_OR) : /* or $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = ORSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = ORSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$ulo16 */
+  CASE (sem, INSN_OR3) : /* or3 $dr,$sr,#$ulo16 */

 {
 #define FLD(f) abuf->fields.fmt_3_or3.f
 {
 #define FLD(f) abuf->fields.fmt_3_or3.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = ORSI (* FLD (f_r2), FLD (f_uimm16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = ORSI (* FLD (f_r2), FLD (f_uimm16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -229,26 +249,35 @@ with this program; if not, write to the Free Software Foundation, Inc.,
   CASE (sem, INSN_XOR) : /* xor $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f
   CASE (sem, INSN_XOR) : /* xor $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = XORSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = XORSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
+  CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,#$uimm16 */

 {
 #define FLD(f) abuf->fields.fmt_2_and3.f
 {
 #define FLD(f) abuf->fields.fmt_2_and3.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = XORSI (* FLD (f_r2), FLD (f_uimm16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = XORSI (* FLD (f_r2), FLD (f_uimm16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
+  CASE (sem, INSN_ADDI) : /* addi $dr,#$simm8 */

 {
 #define FLD(f) abuf->fields.fmt_4_addi.f
 {
 #define FLD(f) abuf->fields.fmt_4_addi.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = ADDSI (* FLD (f_r1), FLD (f_simm8));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = ADDSI (* FLD (f_r1), FLD (f_simm8));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -256,6 +285,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
   CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f
   CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
   BI temp1;SI temp0;
   temp0 = ADDSI (* FLD (f_r1), * FLD (f_r2));
 do {
   BI temp1;SI temp0;
   temp0 = ADDSI (* FLD (f_r1), * FLD (f_r2));


@@ -265,13 +296,16 @@ do {
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
+  CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,#$simm16 */

 {
 #define FLD(f) abuf->fields.fmt_5_addv3.f
 {
 #define FLD(f) abuf->fields.fmt_5_addv3.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
   BI temp1;SI temp0;
   temp0 = ADDSI (* FLD (f_r2), FLD (f_simm16));
 do {
   BI temp1;SI temp0;
   temp0 = ADDSI (* FLD (f_r2), FLD (f_simm16));


@@ -281,6 +315,7 @@ do {
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -288,6 +323,8 @@ do {
   CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_6_addx.f
   CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_6_addx.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
   BI temp1;SI temp0;
   temp0 = ADDCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
 do {
   BI temp1;SI temp0;
   temp0 = ADDCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));


@@ -297,6 +334,7 @@ do {
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -304,9 +342,12 @@ do {
   CASE (sem, INSN_BC8) : /* bc $disp8 */
 {
 #define FLD(f) abuf->fields.fmt_7_bc8.f
   CASE (sem, INSN_BC8) : /* bc $disp8 */
 {
 #define FLD(f) abuf->fields.fmt_7_bc8.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (CPU (h_cond)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 }
 if (CPU (h_cond)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -314,9 +355,12 @@ if (CPU (h_cond)) {
   CASE (sem, INSN_BC24) : /* bc $disp24 */
 {
 #define FLD(f) abuf->fields.fmt_8_bc24.f
   CASE (sem, INSN_BC24) : /* bc $disp24 */
 {
 #define FLD(f) abuf->fields.fmt_8_bc24.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (CPU (h_cond)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 }
 if (CPU (h_cond)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -324,9 +368,12 @@ if (CPU (h_cond)) {
   CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_9_beq.f
   CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_9_beq.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (EQSI (* FLD (f_r1), * FLD (f_r2))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }
 if (EQSI (* FLD (f_r1), * FLD (f_r2))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -334,9 +381,12 @@ if (EQSI (* FLD (f_r1), * FLD (f_r2))) {
   CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_10_beqz.f
   CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_10_beqz.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (EQSI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }
 if (EQSI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -344,9 +394,12 @@ if (EQSI (* FLD (f_r2), 0)) {
   CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_10_beqz.f
   CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_10_beqz.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (GESI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }
 if (GESI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -354,9 +407,12 @@ if (GESI (* FLD (f_r2), 0)) {
   CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_10_beqz.f
   CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_10_beqz.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (GTSI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }
 if (GTSI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -364,9 +420,12 @@ if (GTSI (* FLD (f_r2), 0)) {
   CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_10_beqz.f
   CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_10_beqz.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (LESI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }
 if (LESI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -374,9 +433,12 @@ if (LESI (* FLD (f_r2), 0)) {
   CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_10_beqz.f
   CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_10_beqz.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (LTSI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }
 if (LTSI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -384,9 +446,12 @@ if (LTSI (* FLD (f_r2), 0)) {
   CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_10_beqz.f
   CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_10_beqz.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (NESI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }
 if (NESI (* FLD (f_r2), 0)) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -394,11 +459,14 @@ if (NESI (* FLD (f_r2), 0)) {
   CASE (sem, INSN_BL8) : /* bl $disp8 */
 {
 #define FLD(f) abuf->fields.fmt_11_bl8.f
   CASE (sem, INSN_BL8) : /* bl $disp8 */
 {
 #define FLD(f) abuf->fields.fmt_11_bl8.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
   CPU (h_gr[14]) = ADDSI (ANDSI (CPU (h_pc), -4), 4);
 do {
   CPU (h_gr[14]) = ADDSI (ANDSI (CPU (h_pc), -4), 4);

-  TRACE_RESULT (current_cpu, "h-gr", 'x', CPU (h_gr[14]));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));

   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 } while (0);
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -406,11 +474,14 @@ do {
   CASE (sem, INSN_BL24) : /* bl $disp24 */
 {
 #define FLD(f) abuf->fields.fmt_12_bl24.f
   CASE (sem, INSN_BL24) : /* bl $disp24 */
 {
 #define FLD(f) abuf->fields.fmt_12_bl24.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
   CPU (h_gr[14]) = ADDSI (CPU (h_pc), 4);
 do {
   CPU (h_gr[14]) = ADDSI (CPU (h_pc), 4);

-  TRACE_RESULT (current_cpu, "h-gr", 'x', CPU (h_gr[14]));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));

   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 } while (0);
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -418,9 +489,12 @@ do {
   CASE (sem, INSN_BNC8) : /* bnc $disp8 */
 {
 #define FLD(f) abuf->fields.fmt_7_bc8.f
   CASE (sem, INSN_BNC8) : /* bnc $disp8 */
 {
 #define FLD(f) abuf->fields.fmt_7_bc8.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (NOTBI (CPU (h_cond))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 }
 if (NOTBI (CPU (h_cond))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -428,9 +502,12 @@ if (NOTBI (CPU (h_cond))) {
   CASE (sem, INSN_BNC24) : /* bnc $disp24 */
 {
 #define FLD(f) abuf->fields.fmt_8_bc24.f
   CASE (sem, INSN_BNC24) : /* bnc $disp24 */
 {
 #define FLD(f) abuf->fields.fmt_8_bc24.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (NOTBI (CPU (h_cond))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 }
 if (NOTBI (CPU (h_cond))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -438,9 +515,12 @@ if (NOTBI (CPU (h_cond))) {
   CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_9_beq.f
   CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
 {
 #define FLD(f) abuf->fields.fmt_9_beq.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (NESI (* FLD (f_r1), * FLD (f_r2))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }
 if (NESI (* FLD (f_r1), * FLD (f_r2))) {
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp16)));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -448,7 +528,10 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) {
   CASE (sem, INSN_BRA8) : /* bra $disp8 */
 {
 #define FLD(f) abuf->fields.fmt_13_bra8.f
   CASE (sem, INSN_BRA8) : /* bra $disp8 */
 {
 #define FLD(f) abuf->fields.fmt_13_bra8.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp8)));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -456,7 +539,10 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) {
   CASE (sem, INSN_BRA24) : /* bra $disp24 */
 {
 #define FLD(f) abuf->fields.fmt_14_bra24.f
   CASE (sem, INSN_BRA24) : /* bra $disp24 */
 {
 #define FLD(f) abuf->fields.fmt_14_bra24.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, FLD (f_disp24)));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -464,17 +550,23 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) {
   CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_cond) = LTSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
   CPU (h_cond) = LTSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
+  CASE (sem, INSN_CMPI) : /* cmpi $src2,#$simm16 */

 {
 #define FLD(f) abuf->fields.fmt_16_cmpi.f
 {
 #define FLD(f) abuf->fields.fmt_16_cmpi.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_cond) = LTSI (* FLD (f_r2), FLD (f_simm16));
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
   CPU (h_cond) = LTSI (* FLD (f_r2), FLD (f_simm16));
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -482,17 +574,23 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) {
   CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_cond) = LTUSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
   CPU (h_cond) = LTUSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_CMPUI) : /* cmpui $src2,$uimm16 */
+  CASE (sem, INSN_CMPUI) : /* cmpui $src2,#$uimm16 */

 {
 #define FLD(f) abuf->fields.fmt_17_cmpui.f
 {
 #define FLD(f) abuf->fields.fmt_17_cmpui.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_cond) = LTUSI (* FLD (f_r2), FLD (f_uimm16));
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
   CPU (h_cond) = LTUSI (* FLD (f_r2), FLD (f_uimm16));
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -500,10 +598,13 @@ if (NESI (* FLD (f_r1), * FLD (f_r2))) {
   CASE (sem, INSN_DIV) : /* div $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_18_div.f
   CASE (sem, INSN_DIV) : /* div $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_18_div.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (NESI (* FLD (f_r2), 0)) {
 * FLD (f_r1) = DIVSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 }
 if (NESI (* FLD (f_r2), 0)) {
 * FLD (f_r1) = DIVSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -511,10 +612,13 @@ if (NESI (* FLD (f_r2), 0)) {
   CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_18_div.f
   CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_18_div.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (NESI (* FLD (f_r2), 0)) {
 * FLD (f_r1) = UDIVSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 }
 if (NESI (* FLD (f_r2), 0)) {
 * FLD (f_r1) = UDIVSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -522,10 +626,13 @@ if (NESI (* FLD (f_r2), 0)) {
   CASE (sem, INSN_REM) : /* rem $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_18_div.f
   CASE (sem, INSN_REM) : /* rem $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_18_div.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (NESI (* FLD (f_r2), 0)) {
 * FLD (f_r1) = MODSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 }
 if (NESI (* FLD (f_r2), 0)) {
 * FLD (f_r1) = MODSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 }

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -533,10 +640,27 @@ if (NESI (* FLD (f_r2), 0)) {
   CASE (sem, INSN_REMU) : /* remu $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_18_div.f
   CASE (sem, INSN_REMU) : /* remu $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_18_div.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 if (NESI (* FLD (f_r2), 0)) {
 * FLD (f_r1) = UMODSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 }
 if (NESI (* FLD (f_r2), 0)) {
 * FLD (f_r1) = UMODSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 }

+
+#undef FLD
+}
+  BREAK (sem);
+
+  CASE (sem, INSN_DIVH) : /* divh $dr,$sr */
+{
+#define FLD(f) abuf->fields.fmt_18_div.f
+  new_pc = SEM_NEXT_PC (sem_arg);
+
+if (NESI (* FLD (f_r2), 0)) {
+* FLD (f_r1) = DIVSI (EXTHISI (TRUNCSIHI (* FLD (f_r1))), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+}
+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -544,14 +668,17 @@ if (NESI (* FLD (f_r2), 0)) {
   CASE (sem, INSN_JL) : /* jl $sr */
 {
 #define FLD(f) abuf->fields.fmt_19_jl.f
   CASE (sem, INSN_JL) : /* jl $sr */
 {
 #define FLD(f) abuf->fields.fmt_19_jl.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
 do {

-  USI temp1;SI temp0;
+  SI temp1;SI temp0;

   temp0 = ADDSI (ANDSI (CPU (h_pc), -4), 4);
   temp1 = * FLD (f_r2);
   CPU (h_gr[14]) = temp0;
   temp0 = ADDSI (ANDSI (CPU (h_pc), -4), 4);
   temp1 = * FLD (f_r2);
   CPU (h_gr[14]) = temp0;

-  TRACE_RESULT (current_cpu, "h-gr", 'x', CPU (h_gr[14]));
+  TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));

   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1));
 } while (0);
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1));
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -559,7 +686,10 @@ do {
   CASE (sem, INSN_JMP) : /* jmp $sr */
 {
 #define FLD(f) abuf->fields.fmt_20_jmp.f
   CASE (sem, INSN_JMP) : /* jmp $sr */
 {
 #define FLD(f) abuf->fields.fmt_20_jmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, * FLD (f_r2)));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, * FLD (f_r2)));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -567,8 +697,11 @@ do {
   CASE (sem, INSN_LD) : /* ld $dr,@$sr */
 {
 #define FLD(f) abuf->fields.fmt_21_ld.f
   CASE (sem, INSN_LD) : /* ld $dr,@$sr */
 {
 #define FLD(f) abuf->fields.fmt_21_ld.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = GETMEMSI (current_cpu, * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = GETMEMSI (current_cpu, * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -576,8 +709,11 @@ do {
   CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
 {
 #define FLD(f) abuf->fields.fmt_22_ld_d.f
   CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
 {
 #define FLD(f) abuf->fields.fmt_22_ld_d.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -585,8 +721,11 @@ do {
   CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
 {
 #define FLD(f) abuf->fields.fmt_23_ldb.f
   CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
 {
 #define FLD(f) abuf->fields.fmt_23_ldb.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -594,8 +733,11 @@ do {
   CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
 {
 #define FLD(f) abuf->fields.fmt_24_ldb_d.f
   CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
 {
 #define FLD(f) abuf->fields.fmt_24_ldb_d.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -603,8 +745,11 @@ do {
   CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
 {
 #define FLD(f) abuf->fields.fmt_25_ldh.f
   CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
 {
 #define FLD(f) abuf->fields.fmt_25_ldh.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -612,8 +757,11 @@ do {
   CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
 {
 #define FLD(f) abuf->fields.fmt_26_ldh_d.f
   CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
 {
 #define FLD(f) abuf->fields.fmt_26_ldh_d.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -621,8 +769,11 @@ do {
   CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
 {
 #define FLD(f) abuf->fields.fmt_23_ldb.f
   CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
 {
 #define FLD(f) abuf->fields.fmt_23_ldb.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, * FLD (f_r2)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -630,8 +781,11 @@ do {
   CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
 {
 #define FLD(f) abuf->fields.fmt_24_ldb_d.f
   CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
 {
 #define FLD(f) abuf->fields.fmt_24_ldb_d.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -639,8 +793,11 @@ do {
   CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
 {
 #define FLD(f) abuf->fields.fmt_25_ldh.f
   CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
 {
 #define FLD(f) abuf->fields.fmt_25_ldh.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, * FLD (f_r2)));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -648,8 +805,11 @@ do {
   CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
 {
 #define FLD(f) abuf->fields.fmt_26_ldh_d.f
   CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
 {
 #define FLD(f) abuf->fields.fmt_26_ldh_d.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -657,6 +817,8 @@ do {
   CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
 {
 #define FLD(f) abuf->fields.fmt_21_ld.f
   CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
 {
 #define FLD(f) abuf->fields.fmt_21_ld.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
   SI temp1;SI temp0;
   temp0 = GETMEMSI (current_cpu, * FLD (f_r2));
 do {
   SI temp1;SI temp0;
   temp0 = GETMEMSI (current_cpu, * FLD (f_r2));


@@ -666,24 +828,31 @@ do {
 * FLD (f_r2) = temp1;
   TRACE_RESULT (current_cpu, "sr", 'x', * FLD (f_r2));
 } while (0);
 * FLD (f_r2) = temp1;
   TRACE_RESULT (current_cpu, "sr", 'x', * FLD (f_r2));
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
+  CASE (sem, INSN_LD24) : /* ld24 $dr,#$uimm24 */

 {
 #define FLD(f) abuf->fields.fmt_27_ld24.f
 {
 #define FLD(f) abuf->fields.fmt_27_ld24.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = FLD (f_uimm24);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = FLD (f_uimm24);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_LDI8) : /* ldi $dr,$simm8 */
+  CASE (sem, INSN_LDI8) : /* ldi $dr,#$simm8 */

 {
 #define FLD(f) abuf->fields.fmt_28_ldi8.f
 {
 #define FLD(f) abuf->fields.fmt_28_ldi8.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = FLD (f_simm8);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = FLD (f_simm8);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -691,8 +860,11 @@ do {
   CASE (sem, INSN_LDI16) : /* ldi $dr,$slo16 */
 {
 #define FLD(f) abuf->fields.fmt_29_ldi16.f
   CASE (sem, INSN_LDI16) : /* ldi $dr,$slo16 */
 {
 #define FLD(f) abuf->fields.fmt_29_ldi16.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = FLD (f_simm16);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = FLD (f_simm16);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -700,7 +872,10 @@ do {
   CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f
   CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
 do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -708,8 +883,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_30_machi.f
   CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_30_machi.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -717,8 +895,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_30_machi.f
   CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_30_machi.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -726,8 +907,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_30_machi.f
   CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_30_machi.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16))))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -735,8 +919,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_30_machi.f
   CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_30_machi.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
   CPU (h_accum) = SRADI (SLLDI (ADDDI (CPU (h_accum), MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2))))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -744,8 +931,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MUL) : /* mul $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f
   CASE (sem, INSN_MUL) : /* mul $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = MULSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = MULSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -753,8 +943,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 16), 16);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (f_r1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 16), 16);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -762,8 +955,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 16), 16);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (f_r1), 16)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 16), 16);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -771,8 +967,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (f_r2), 16)))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -780,8 +979,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
   CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (f_r1)), EXTHIDI (TRUNCSIHI (* FLD (f_r2)))), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -789,8 +991,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MV) : /* mv $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_31_mv.f
   CASE (sem, INSN_MV) : /* mv $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_31_mv.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = * FLD (f_r2);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = * FLD (f_r2);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -798,8 +1003,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
 {
 #define FLD(f) abuf->fields.fmt_32_mvfachi.f
   CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
 {
 #define FLD(f) abuf->fields.fmt_32_mvfachi.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 32));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 32));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -807,8 +1015,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
 {
 #define FLD(f) abuf->fields.fmt_32_mvfachi.f
   CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
 {
 #define FLD(f) abuf->fields.fmt_32_mvfachi.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = TRUNCDISI (CPU (h_accum));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = TRUNCDISI (CPU (h_accum));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -816,8 +1027,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
 {
 #define FLD(f) abuf->fields.fmt_32_mvfachi.f
   CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
 {
 #define FLD(f) abuf->fields.fmt_32_mvfachi.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = TRUNCDISI (SRADI (CPU (h_accum), 16));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -825,8 +1039,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
 {
 #define FLD(f) abuf->fields.fmt_33_mvfc.f
   CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
 {
 #define FLD(f) abuf->fields.fmt_33_mvfc.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = m32r_h_cr_get (current_cpu, FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = m32r_h_cr_get (current_cpu, FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -834,8 +1051,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
 {
 #define FLD(f) abuf->fields.fmt_34_mvtachi.f
   CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
 {
 #define FLD(f) abuf->fields.fmt_34_mvtachi.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (f_r1)), 32));
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
   CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (f_r1)), 32));
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -843,8 +1063,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
 {
 #define FLD(f) abuf->fields.fmt_34_mvtachi.f
   CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
 {
 #define FLD(f) abuf->fields.fmt_34_mvtachi.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

   CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0xffffffff, 0)), EXTSIDI (* FLD (f_r1)));
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
   CPU (h_accum) = ORDI (ANDDI (CPU (h_accum), MAKEDI (0xffffffff, 0)), EXTSIDI (* FLD (f_r1)));
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -852,8 +1075,11 @@ do_lock (current_cpu, * FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
 {
 #define FLD(f) abuf->fields.fmt_35_mvtc.f
   CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
 {
 #define FLD(f) abuf->fields.fmt_35_mvtc.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 m32r_h_cr_set (current_cpu, FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dcr", 'x', m32r_h_cr_get (current_cpu, FLD (f_r1)));
 m32r_h_cr_set (current_cpu, FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dcr", 'x', m32r_h_cr_get (current_cpu, FLD (f_r1)));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -861,8 +1087,11 @@ m32r_h_cr_set (current_cpu, FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_NEG) : /* neg $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_31_mv.f
   CASE (sem, INSN_NEG) : /* neg $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_31_mv.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = NEGSI (* FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = NEGSI (* FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -870,7 +1099,10 @@ m32r_h_cr_set (current_cpu, FLD (f_r1), * FLD (f_r2));
   CASE (sem, INSN_NOP) : /* nop */
 {
 #define FLD(f) abuf->fields.fmt_36_nop.f
   CASE (sem, INSN_NOP) : /* nop */
 {
 #define FLD(f) abuf->fields.fmt_36_nop.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -878,8 +1110,11 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
   CASE (sem, INSN_NOT) : /* not $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_31_mv.f
   CASE (sem, INSN_NOT) : /* not $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_31_mv.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = INVSI (* FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = INVSI (* FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -887,22 +1122,16 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
   CASE (sem, INSN_RAC) : /* rac */
 {
 #define FLD(f) abuf->fields.fmt_37_rac.f
   CASE (sem, INSN_RAC) : /* rac */
 {
 #define FLD(f) abuf->fields.fmt_37_rac.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
   DI tmp_tmp1;
 do {
   DI tmp_tmp1;

-  tmp_tmp1 = ANDDI (CPU (h_accum), MAKEDI (16777215, 0xffffffff));
-if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0xffff8000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
-  tmp_tmp1 = MAKEDI (16383, 0xffff8000);
-} else {
-if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
-  tmp_tmp1 = MAKEDI (16760832, 0);
-} else {
-  tmp_tmp1 = ANDDI (ADDDI (CPU (h_accum), MAKEDI (0, 16384)), MAKEDI (16777215, 0xffff8000));
-}
-}
-  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
-  CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
+  tmp_tmp1 = SLLDI (CPU (h_accum), 1);
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
+  CPU (h_accum) = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));

   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 } while (0);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -910,6 +1139,8 @@ if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760
   CASE (sem, INSN_RACH) : /* rach */
 {
 #define FLD(f) abuf->fields.fmt_37_rac.f
   CASE (sem, INSN_RACH) : /* rach */
 {
 #define FLD(f) abuf->fields.fmt_37_rac.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
   DI tmp_tmp1;
   tmp_tmp1 = ANDDI (CPU (h_accum), MAKEDI (16777215, 0xffffffff));
 do {
   DI tmp_tmp1;
   tmp_tmp1 = ANDDI (CPU (h_accum), MAKEDI (16777215, 0xffffffff));


@@ -926,32 +1157,39 @@ if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760
   CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 } while (0);
   CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 
   CASE (sem, INSN_RTE) : /* rte */
 {
 #undef FLD
 }
   BREAK (sem);
 
   CASE (sem, INSN_RTE) : /* rte */
 {

-#define FLD(f) abuf->fields.fmt_36_nop.f
+#define FLD(f) abuf->fields.fmt_38_rte.f
+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
   CPU (h_sm) = CPU (h_bsm);
 do {
   CPU (h_sm) = CPU (h_bsm);

-  TRACE_RESULT (current_cpu, "h-sm", 'x', CPU (h_sm));
+  TRACE_RESULT (current_cpu, "h-sm-0", 'x', CPU (h_sm));

   CPU (h_ie) = CPU (h_bie);
   CPU (h_ie) = CPU (h_bie);

-  TRACE_RESULT (current_cpu, "h-ie", 'x', CPU (h_ie));
+  TRACE_RESULT (current_cpu, "h-ie-0", 'x', CPU (h_ie));

   CPU (h_cond) = CPU (h_bcond);
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, CPU (h_bpc)));
   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 } while (0);
   CPU (h_cond) = CPU (h_bcond);
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, CPU (h_bpc)));
   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_SETH) : /* seth $dr,$hi16 */
+  CASE (sem, INSN_SETH) : /* seth $dr,#$hi16 */

 {
 {

-#define FLD(f) abuf->fields.fmt_38_seth.f
+#define FLD(f) abuf->fields.fmt_39_seth.f
+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = SLLSI (FLD (f_hi16), 16);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = SLLSI (FLD (f_hi16), 16);
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -959,26 +1197,35 @@ do {
   CASE (sem, INSN_SLL) : /* sll $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f
   CASE (sem, INSN_SLL) : /* sll $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = SLLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = SLLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
+  CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,#$simm16 */

 {
 #define FLD(f) abuf->fields.fmt_5_addv3.f
 {
 #define FLD(f) abuf->fields.fmt_5_addv3.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = SLLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = SLLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
+  CASE (sem, INSN_SLLI) : /* slli $dr,#$uimm5 */

 {
 {

-#define FLD(f) abuf->fields.fmt_39_slli.f
+#define FLD(f) abuf->fields.fmt_40_slli.f
+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = SLLSI (* FLD (f_r1), FLD (f_uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = SLLSI (* FLD (f_r1), FLD (f_uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -986,26 +1233,35 @@ do {
   CASE (sem, INSN_SRA) : /* sra $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f
   CASE (sem, INSN_SRA) : /* sra $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = SRASI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = SRASI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
+  CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,#$simm16 */

 {
 #define FLD(f) abuf->fields.fmt_5_addv3.f
 {
 #define FLD(f) abuf->fields.fmt_5_addv3.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = SRASI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = SRASI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
+  CASE (sem, INSN_SRAI) : /* srai $dr,#$uimm5 */

 {
 {

-#define FLD(f) abuf->fields.fmt_39_slli.f
+#define FLD(f) abuf->fields.fmt_40_slli.f
+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = SRASI (* FLD (f_r1), FLD (f_uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = SRASI (* FLD (f_r1), FLD (f_uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -1013,26 +1269,35 @@ do {
   CASE (sem, INSN_SRL) : /* srl $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f
   CASE (sem, INSN_SRL) : /* srl $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = SRLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = SRLSI (* FLD (f_r1), ANDSI (* FLD (f_r2), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
+  CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,#$simm16 */

 {
 #define FLD(f) abuf->fields.fmt_5_addv3.f
 {
 #define FLD(f) abuf->fields.fmt_5_addv3.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = SRLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = SRLSI (* FLD (f_r2), ANDSI (FLD (f_simm16), 31));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
+  CASE (sem, INSN_SRLI) : /* srli $dr,#$uimm5 */

 {
 {

-#define FLD(f) abuf->fields.fmt_39_slli.f
+#define FLD(f) abuf->fields.fmt_40_slli.f
+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = SRLSI (* FLD (f_r1), FLD (f_uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = SRLSI (* FLD (f_r1), FLD (f_uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -1040,17 +1305,23 @@ do {
   CASE (sem, INSN_ST) : /* st $src1,@$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   CASE (sem, INSN_ST) : /* st $src1,@$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));

-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
+

 #undef FLD
 }
   BREAK (sem);
 
   CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
 {
 #undef FLD
 }
   BREAK (sem);
 
   CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
 {

-#define FLD(f) abuf->fields.fmt_40_st_d.f
+#define FLD(f) abuf->fields.fmt_41_st_d.f
+  new_pc = SEM_NEXT_PC (sem_arg);
+

 SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
 SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));

-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+  TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -1058,17 +1329,23 @@ SETMEMSI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
   CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1));
 SETMEMQI (current_cpu, * FLD (f_r2), * FLD (f_r1));

-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMQI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMQI (current_cpu, * FLD (f_r2)));
+

 #undef FLD
 }
   BREAK (sem);
 
   CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
 {
 #undef FLD
 }
   BREAK (sem);
 
   CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
 {

-#define FLD(f) abuf->fields.fmt_40_st_d.f
+#define FLD(f) abuf->fields.fmt_41_st_d.f
+  new_pc = SEM_NEXT_PC (sem_arg);
+

 SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
 SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));

-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+  TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -1076,17 +1353,23 @@ SETMEMQI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
   CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1));
 SETMEMHI (current_cpu, * FLD (f_r2), * FLD (f_r1));

-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMHI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMHI (current_cpu, * FLD (f_r2)));
+

 #undef FLD
 }
   BREAK (sem);
 
   CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
 {
 #undef FLD
 }
   BREAK (sem);
 
   CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
 {

-#define FLD(f) abuf->fields.fmt_40_st_d.f
+#define FLD(f) abuf->fields.fmt_41_st_d.f
+  new_pc = SEM_NEXT_PC (sem_arg);
+

 SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
 SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));

-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+  TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16))));
+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -1094,12 +1377,15 @@ SETMEMHI (current_cpu, ADDSI (* FLD (f_r2), FLD (f_simm16)), * FLD (f_r1));
   CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
 * FLD (f_r2) = ADDSI (* FLD (f_r2), 4);
   TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
 do {
 * FLD (f_r2) = ADDSI (* FLD (f_r2), 4);
   TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));

-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));

 } while (0);
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -1107,12 +1393,15 @@ SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
   CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
 * FLD (f_r2) = SUBSI (* FLD (f_r2), 4);
   TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
 do {
 * FLD (f_r2) = SUBSI (* FLD (f_r2), 4);
   TRACE_RESULT (current_cpu, "src2", 'x', * FLD (f_r2));
 SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));

-  TRACE_RESULT (current_cpu, "h-memory", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));
+  TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, * FLD (f_r2)));

 } while (0);
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -1120,8 +1409,11 @@ SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
   CASE (sem, INSN_SUB) : /* sub $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f
   CASE (sem, INSN_SUB) : /* sub $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 * FLD (f_r1) = SUBSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
 * FLD (f_r1) = SUBSI (* FLD (f_r1), * FLD (f_r2));
   TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -1129,6 +1421,8 @@ SETMEMSI (current_cpu, * FLD (f_r2), * FLD (f_r1));
   CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f
   CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_0_add.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
   BI temp1;SI temp0;
   temp0 = SUBSI (* FLD (f_r1), * FLD (f_r2));
 do {
   BI temp1;SI temp0;
   temp0 = SUBSI (* FLD (f_r1), * FLD (f_r2));


@@ -1138,6 +1432,7 @@ do {
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -1145,6 +1440,8 @@ do {
   CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_6_addx.f
   CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
 {
 #define FLD(f) abuf->fields.fmt_6_addx.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do {
   BI temp1;SI temp0;
   temp0 = SUBCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));
 do {
   BI temp1;SI temp0;
   temp0 = SUBCSI (* FLD (f_r1), * FLD (f_r2), CPU (h_cond));


@@ -1154,14 +1451,18 @@ do {
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);
   CPU (h_cond) = temp1;
   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 } while (0);

+

 #undef FLD
 }
   BREAK (sem);
 
 #undef FLD
 }
   BREAK (sem);
 

-  CASE (sem, INSN_TRAP) : /* trap $uimm4 */
+  CASE (sem, INSN_TRAP) : /* trap #$uimm4 */

 {
 {

-#define FLD(f) abuf->fields.fmt_41_trap.f
+#define FLD(f) abuf->fields.fmt_42_trap.f
+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do_trap (current_cpu, FLD (f_uimm4));
 do_trap (current_cpu, FLD (f_uimm4));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);


@@ -1169,7 +1470,10 @@ do_trap (current_cpu, FLD (f_uimm4));
   CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f
   CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
 {
 #define FLD(f) abuf->fields.fmt_15_cmp.f

+  new_pc = SEM_NEXT_PC (sem_arg);
+

 do_unlock (current_cpu, * FLD (f_r1), * FLD (f_r2));
 do_unlock (current_cpu, * FLD (f_r1), * FLD (f_r2));

+

 #undef FLD
 }
   BREAK (sem);
 #undef FLD
 }
   BREAK (sem);

diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c
index 3e5d4db..7ba6f3c 100644 (file)
--- a/sim/m32r/sem.c
+++ b/sim/m32r/sem.c
@@ -950,6 +950,32 @@ if (NESI (* FLD (f_r2), 0)) {
 #undef FLD
 }
 
 #undef FLD
 }
 

+/* Perform divh: divh $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32r,divh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_18_div.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+
+if (NESI (* FLD (f_r2), 0)) {
+* FLD (f_r1) = DIVSI (EXTHISI (TRUNCSIHI (* FLD (f_r1))), * FLD (f_r2));
+  TRACE_RESULT (current_cpu, "dr", 'x', * FLD (f_r1));
+}
+
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32r_model_mark_get_h_gr (current_cpu, abuf);
+      m32r_model_mark_set_h_gr (current_cpu, abuf);
+      m32r_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+
+  return new_pc;
+#undef FLD
+}
+

 /* Perform jl: jl $sr.  */
 CIA
 SEM_FN_NAME (m32r,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 /* Perform jl: jl $sr.  */
 CIA
 SEM_FN_NAME (m32r,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)


@@ -960,7 +986,7 @@ SEM_FN_NAME (m32r,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   int taken_p = 0;
 
 do {
   int taken_p = 0;
 
 do {

-  USI temp1;SI temp0;
+  SI temp1;SI temp0;

   temp0 = ADDSI (ANDSI (CPU (h_pc), -4), 4);
   temp1 = * FLD (f_r2);
   CPU (h_gr[14]) = temp0;
   temp0 = ADDSI (ANDSI (CPU (h_pc), -4), 4);
   temp1 = * FLD (f_r2);
   CPU (h_gr[14]) = temp0;


@@ -1841,18 +1867,9 @@ SEM_FN_NAME (m32r,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 do {
   DI tmp_tmp1;
 
 do {
   DI tmp_tmp1;

-  tmp_tmp1 = ANDDI (CPU (h_accum), MAKEDI (16777215, 0xffffffff));
-if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0xffff8000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
-  tmp_tmp1 = MAKEDI (16383, 0xffff8000);
-} else {
-if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
-  tmp_tmp1 = MAKEDI (16760832, 0);
-} else {
-  tmp_tmp1 = ANDDI (ADDDI (CPU (h_accum), MAKEDI (0, 16384)), MAKEDI (16777215, 0xffff8000));
-}
-}
-  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
-  CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
+  tmp_tmp1 = SLLDI (CPU (h_accum), 1);
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
+  CPU (h_accum) = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));

   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 } while (0);
 
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 } while (0);
 


@@ -2496,10 +2513,7 @@ do_unlock (current_cpu, * FLD (f_r1), * FLD (f_r2));
 #undef FLD
 }
 
 #undef FLD
 }
 

-/* FIXME: Add "no return" attribute to illegal insn handlers.
-   They all call longjmp.  */
-
-PCADDR
+CIA

 SEM_FN_NAME (m32r,illegal) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
   sim_engine_illegal_insn (current_cpu, NULL_CIA /*FIXME*/);
 SEM_FN_NAME (m32r,illegal) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
   sim_engine_illegal_insn (current_cpu, NULL_CIA /*FIXME*/);

diff --git a/sim/m32r/semx.c b/sim/m32r/semx.c
index 519dda2..19d9a1e 100644 (file)
--- a/sim/m32r/semx.c
+++ b/sim/m32r/semx.c
@@ -1222,6 +1222,35 @@ if (NESI (OPRND (sr), 0)) {
 #undef OPRND
 }
 
 #undef OPRND
 }
 

+/* Perform divh: divh $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,divh) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
+{
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) par_exec->operands.fmt_21_div.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = CPU (h_pc) + 4;
+  EXTRACT_FMT_21_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_21_DIV_CODE
+
+if (NESI (OPRND (sr), 0)) {
+  CPU (h_gr[f_r1]) = DIVSI (EXTHISI (TRUNCSIHI (OPRND (dr))), OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
+}
+
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+
+  return new_pc;
+#undef OPRND
+}
+

 /* Perform jc: jc $sr.  */
 CIA
 SEM_FN_NAME (m32rx,jc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 /* Perform jc: jc $sr.  */
 CIA
 SEM_FN_NAME (m32rx,jc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)


@@ -1291,7 +1320,7 @@ SEM_FN_NAME (m32rx,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec
   EXTRACT_FMT_23_JL_CODE
 
 do {
   EXTRACT_FMT_23_JL_CODE
 
 do {

-  USI temp1;SI temp0;
+  SI temp1;SI temp0;

   temp0 = ADDSI (ANDSI (OPRND (pc), -4), 4);
   temp1 = OPRND (sr);
   CPU (h_gr[14]) = temp0;
   temp0 = ADDSI (ANDSI (OPRND (pc), -4), 4);
   temp1 = OPRND (sr);
   CPU (h_gr[14]) = temp0;


@@ -2164,32 +2193,23 @@ SEM_FN_NAME (m32rx,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exe
 #undef OPRND
 }
 
 #undef OPRND
 }
 

-/* Perform rac-a: rac $accs.  */
+/* Perform rac-d: rac $accd.  */

 CIA
 CIA

-SEM_FN_NAME (m32rx,rac_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
+SEM_FN_NAME (m32rx,rac_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)

 {
   insn_t insn = SEM_INSN (sem_arg);
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_42_rac_a.f
+#define OPRND(f) par_exec->operands.fmt_42_rac_d.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;

-  EXTRACT_FMT_42_RAC_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
-  EXTRACT_FMT_42_RAC_A_CODE
+  EXTRACT_FMT_42_RAC_D_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
+  EXTRACT_FMT_42_RAC_D_CODE

 
 do {
   DI tmp_tmp1;
 
 do {
   DI tmp_tmp1;

-  tmp_tmp1 = ANDDI (OPRND (accs), MAKEDI (16777215, 0xffffffff));
-if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0xffff8000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
-  tmp_tmp1 = MAKEDI (16383, 0xffff8000);
-} else {
-if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
-  tmp_tmp1 = MAKEDI (16760832, 0);
-} else {
-  tmp_tmp1 = ANDDI (ADDDI (OPRND (accs), MAKEDI (0, 16384)), MAKEDI (16777215, 0xffff8000));
-}
-}
-  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
-m32rx_h_accums_set (current_cpu, f_accs, SRADI (SLLDI (tmp_tmp1, 7), 7));
-  TRACE_RESULT (current_cpu, "accs", 'D', m32rx_h_accums_get (current_cpu, f_accs));
+  tmp_tmp1 = SLLDI (OPRND (accum), 1);
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
+m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000))));
+  TRACE_RESULT (current_cpu, "accd", 'D', m32rx_h_accums_get (current_cpu, f_accd));

 } while (0);
 
 #if WITH_PROFILE_MODEL_P
 } while (0);
 
 #if WITH_PROFILE_MODEL_P


@@ -2203,32 +2223,143 @@ m32rx_h_accums_set (current_cpu, f_accs, SRADI (SLLDI (tmp_tmp1, 7), 7));
 #undef OPRND
 }
 
 #undef OPRND
 }
 

-/* Perform rach-a: rach $accs.  */
+/* Perform rac-ds: rac $accd,$accs.  */

 CIA
 CIA

-SEM_FN_NAME (m32rx,rach_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
+SEM_FN_NAME (m32rx,rac_ds) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)

 {
   insn_t insn = SEM_INSN (sem_arg);
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_42_rac_a.f
+#define OPRND(f) par_exec->operands.fmt_43_rac_ds.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;

-  EXTRACT_FMT_42_RAC_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
-  EXTRACT_FMT_42_RAC_A_CODE
+  EXTRACT_FMT_43_RAC_DS_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
+  EXTRACT_FMT_43_RAC_DS_CODE

 
 do {
   DI tmp_tmp1;
 
 do {
   DI tmp_tmp1;

-  tmp_tmp1 = ANDDI (OPRND (accs), MAKEDI (16777215, 0xffffffff));
-if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
-  tmp_tmp1 = MAKEDI (16383, 0x80000000);
-} else {
-if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
-  tmp_tmp1 = MAKEDI (16760832, 0);
-} else {
-  tmp_tmp1 = ANDDI (ADDDI (OPRND (accs), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
-}
-}
-  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
-m32rx_h_accums_set (current_cpu, f_accs, SRADI (SLLDI (tmp_tmp1, 7), 7));
-  TRACE_RESULT (current_cpu, "accs", 'D', m32rx_h_accums_get (current_cpu, f_accs));
+  tmp_tmp1 = SLLDI (OPRND (accs), 1);
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
+m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000))));
+  TRACE_RESULT (current_cpu, "accd", 'D', m32rx_h_accums_get (current_cpu, f_accd));
+} while (0);
+
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+
+  return new_pc;
+#undef OPRND
+}
+
+/* Perform rac-dsi: rac $accd,$accs,#$imm1.  */
+CIA
+SEM_FN_NAME (m32rx,rac_dsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
+{
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) par_exec->operands.fmt_44_rac_dsi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_44_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
+  EXTRACT_FMT_44_RAC_DSI_CODE
+
+do {
+  DI tmp_tmp1;
+  tmp_tmp1 = SLLDI (OPRND (accs), OPRND (imm1));
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
+m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000))));
+  TRACE_RESULT (current_cpu, "accd", 'D', m32rx_h_accums_get (current_cpu, f_accd));
+} while (0);
+
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+
+  return new_pc;
+#undef OPRND
+}
+
+/* Perform rach-d: rach $accd.  */
+CIA
+SEM_FN_NAME (m32rx,rach_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
+{
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) par_exec->operands.fmt_42_rac_d.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_42_RAC_D_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
+  EXTRACT_FMT_42_RAC_D_CODE
+
+do {
+  DI tmp_tmp1;
+  tmp_tmp1 = SLLDI (OPRND (accum), 1);
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
+m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0))));
+  TRACE_RESULT (current_cpu, "accd", 'D', m32rx_h_accums_get (current_cpu, f_accd));
+} while (0);
+
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+
+  return new_pc;
+#undef OPRND
+}
+
+/* Perform rach-ds: rach $accd,$accs.  */
+CIA
+SEM_FN_NAME (m32rx,rach_ds) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
+{
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) par_exec->operands.fmt_43_rac_ds.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_43_RAC_DS_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
+  EXTRACT_FMT_43_RAC_DS_CODE
+
+do {
+  DI tmp_tmp1;
+  tmp_tmp1 = SLLDI (OPRND (accs), 1);
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
+m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0))));
+  TRACE_RESULT (current_cpu, "accd", 'D', m32rx_h_accums_get (current_cpu, f_accd));
+} while (0);
+
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+
+  return new_pc;
+#undef OPRND
+}
+
+/* Perform rach-dsi: rach $accd,$accs,#$imm1.  */
+CIA
+SEM_FN_NAME (m32rx,rach_dsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
+{
+  insn_t insn = SEM_INSN (sem_arg);
+#define OPRND(f) par_exec->operands.fmt_44_rac_dsi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = CPU (h_pc) + 2;
+  EXTRACT_FMT_44_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
+  EXTRACT_FMT_44_RAC_DSI_CODE
+
+do {
+  DI tmp_tmp1;
+  tmp_tmp1 = SLLDI (OPRND (accs), OPRND (imm1));
+  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
+m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0))));
+  TRACE_RESULT (current_cpu, "accd", 'D', m32rx_h_accums_get (current_cpu, f_accd));

 } while (0);
 
 #if WITH_PROFILE_MODEL_P
 } while (0);
 
 #if WITH_PROFILE_MODEL_P


@@ -2247,12 +2378,12 @@ CIA
 SEM_FN_NAME (m32rx,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_43_rte.f
+#define OPRND(f) par_exec->operands.fmt_45_rte.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;

-  EXTRACT_FMT_43_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
-  EXTRACT_FMT_43_RTE_CODE
+  EXTRACT_FMT_45_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_45_RTE_CODE

 
 do {
   CPU (h_sm) = OPRND (h_bsm_0);
 
 do {
   CPU (h_sm) = OPRND (h_bsm_0);


@@ -2281,11 +2412,11 @@ CIA
 SEM_FN_NAME (m32rx,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_44_seth.f
+#define OPRND(f) par_exec->operands.fmt_46_seth.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;

-  EXTRACT_FMT_44_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
-  EXTRACT_FMT_44_SETH_CODE
+  EXTRACT_FMT_46_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
+  EXTRACT_FMT_46_SETH_CODE

 
   CPU (h_gr[f_r1]) = SLLSI (OPRND (hi16), 16);
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 
   CPU (h_gr[f_r1]) = SLLSI (OPRND (hi16), 16);
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));


@@ -2361,11 +2492,11 @@ CIA
 SEM_FN_NAME (m32rx,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_45_slli.f
+#define OPRND(f) par_exec->operands.fmt_47_slli.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;

-  EXTRACT_FMT_45_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
-  EXTRACT_FMT_45_SLLI_CODE
+  EXTRACT_FMT_47_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+  EXTRACT_FMT_47_SLLI_CODE

 
   CPU (h_gr[f_r1]) = SLLSI (OPRND (dr), OPRND (uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 
   CPU (h_gr[f_r1]) = SLLSI (OPRND (dr), OPRND (uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));


@@ -2442,11 +2573,11 @@ CIA
 SEM_FN_NAME (m32rx,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_45_slli.f
+#define OPRND(f) par_exec->operands.fmt_47_slli.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;

-  EXTRACT_FMT_45_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
-  EXTRACT_FMT_45_SLLI_CODE
+  EXTRACT_FMT_47_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+  EXTRACT_FMT_47_SLLI_CODE

 
   CPU (h_gr[f_r1]) = SRASI (OPRND (dr), OPRND (uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 
   CPU (h_gr[f_r1]) = SRASI (OPRND (dr), OPRND (uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));


@@ -2523,11 +2654,11 @@ CIA
 SEM_FN_NAME (m32rx,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_45_slli.f
+#define OPRND(f) par_exec->operands.fmt_47_slli.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;

-  EXTRACT_FMT_45_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
-  EXTRACT_FMT_45_SLLI_CODE
+  EXTRACT_FMT_47_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+  EXTRACT_FMT_47_SLLI_CODE

 
   CPU (h_gr[f_r1]) = SRLSI (OPRND (dr), OPRND (uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 
   CPU (h_gr[f_r1]) = SRLSI (OPRND (dr), OPRND (uimm5));
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));


@@ -2576,11 +2707,11 @@ CIA
 SEM_FN_NAME (m32rx,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_46_st_d.f
+#define OPRND(f) par_exec->operands.fmt_48_st_d.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;

-  EXTRACT_FMT_46_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-  EXTRACT_FMT_46_ST_D_CODE
+  EXTRACT_FMT_48_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_48_ST_D_CODE

 
 SETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
   TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16))));
 
 SETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
   TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16))));


@@ -2628,11 +2759,11 @@ CIA
 SEM_FN_NAME (m32rx,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_46_st_d.f
+#define OPRND(f) par_exec->operands.fmt_48_st_d.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;

-  EXTRACT_FMT_46_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-  EXTRACT_FMT_46_ST_D_CODE
+  EXTRACT_FMT_48_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_48_ST_D_CODE

 
 SETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
   TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16))));
 
 SETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
   TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16))));


@@ -2680,11 +2811,11 @@ CIA
 SEM_FN_NAME (m32rx,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_46_st_d.f
+#define OPRND(f) par_exec->operands.fmt_48_st_d.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;

-  EXTRACT_FMT_46_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-  EXTRACT_FMT_46_ST_D_CODE
+  EXTRACT_FMT_48_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+  EXTRACT_FMT_48_ST_D_CODE

 
 SETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
   TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16))));
 
 SETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
   TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16))));


@@ -2861,12 +2992,12 @@ CIA
 SEM_FN_NAME (m32rx,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_47_trap.f
+#define OPRND(f) par_exec->operands.fmt_49_trap.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   int taken_p = 0;

-  EXTRACT_FMT_47_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
-  EXTRACT_FMT_47_TRAP_CODE
+  EXTRACT_FMT_49_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
+  EXTRACT_FMT_49_TRAP_CODE

 
 do_trap (current_cpu, OPRND (uimm4));
 
 
 do_trap (current_cpu, OPRND (uimm4));
 


@@ -2911,11 +3042,11 @@ CIA
 SEM_FN_NAME (m32rx,satb) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,satb) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_48_satb.f
+#define OPRND(f) par_exec->operands.fmt_50_satb.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;

-  EXTRACT_FMT_48_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-  EXTRACT_FMT_48_SATB_CODE
+  EXTRACT_FMT_50_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_50_SATB_CODE

 
   CPU (h_gr[f_r1]) = (GESI (OPRND (src2), 127)) ? (127) : (LESI (OPRND (src2), -128)) ? (-128) : (OPRND (src2));
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 
   CPU (h_gr[f_r1]) = (GESI (OPRND (src2), 127)) ? (127) : (LESI (OPRND (src2), -128)) ? (-128) : (OPRND (src2));
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));


@@ -2938,11 +3069,11 @@ CIA
 SEM_FN_NAME (m32rx,sath) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,sath) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_48_satb.f
+#define OPRND(f) par_exec->operands.fmt_50_satb.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;

-  EXTRACT_FMT_48_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-  EXTRACT_FMT_48_SATB_CODE
+  EXTRACT_FMT_50_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_50_SATB_CODE

 
   CPU (h_gr[f_r1]) = (GESI (OPRND (src2), 32767)) ? (32767) : (LESI (OPRND (src2), -32768)) ? (-32768) : (OPRND (src2));
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 
   CPU (h_gr[f_r1]) = (GESI (OPRND (src2), 32767)) ? (32767) : (LESI (OPRND (src2), -32768)) ? (-32768) : (OPRND (src2));
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));


@@ -2965,11 +3096,11 @@ CIA
 SEM_FN_NAME (m32rx,sat) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,sat) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_49_sat.f
+#define OPRND(f) par_exec->operands.fmt_51_sat.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 4;

-  EXTRACT_FMT_49_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-  EXTRACT_FMT_49_SAT_CODE
+  EXTRACT_FMT_51_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+  EXTRACT_FMT_51_SAT_CODE

 
   CPU (h_gr[f_r1]) = (OPRND (condbit)) ? ((LTSI (OPRND (src2), 0)) ? (2147483647) : (0x80000000)) : (OPRND (src2));
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 
   CPU (h_gr[f_r1]) = (OPRND (condbit)) ? ((LTSI (OPRND (src2), 0)) ? (2147483647) : (0x80000000)) : (OPRND (src2));
   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));


@@ -3018,11 +3149,11 @@ CIA
 SEM_FN_NAME (m32rx,sadd) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,sadd) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_50_sadd.f
+#define OPRND(f) par_exec->operands.fmt_52_sadd.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;

-  EXTRACT_FMT_50_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-  EXTRACT_FMT_50_SADD_CODE
+  EXTRACT_FMT_52_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_52_SADD_CODE

 
 m32rx_h_accums_set (current_cpu, 0, ADDDI (SRADI (OPRND (h_accums_1), 16), OPRND (h_accums_0)));
   TRACE_RESULT (current_cpu, "h-accums-0", 'D', m32rx_h_accums_get (current_cpu, 0));
 
 m32rx_h_accums_set (current_cpu, 0, ADDDI (SRADI (OPRND (h_accums_1), 16), OPRND (h_accums_0)));
   TRACE_RESULT (current_cpu, "h-accums-0", 'D', m32rx_h_accums_get (current_cpu, 0));


@@ -3043,11 +3174,11 @@ CIA
 SEM_FN_NAME (m32rx,macwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,macwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_51_macwu1.f
+#define OPRND(f) par_exec->operands.fmt_53_macwu1.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;

-  EXTRACT_FMT_51_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
-  EXTRACT_FMT_51_MACWU1_CODE
+  EXTRACT_FMT_53_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_53_MACWU1_CODE

 
 m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums_1), MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535)))), 8), 8));
   TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1));
 
 m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums_1), MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535)))), 8), 8));
   TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1));


@@ -3069,11 +3200,11 @@ CIA
 SEM_FN_NAME (m32rx,msblo) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,msblo) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_52_msblo.f
+#define OPRND(f) par_exec->operands.fmt_54_msblo.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;

-  EXTRACT_FMT_52_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */
-  EXTRACT_FMT_52_MSBLO_CODE
+  EXTRACT_FMT_54_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_54_MSBLO_CODE

 
   CPU (h_accum) = SRADI (SLLDI (SUBDI (OPRND (accum), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (OPRND (src1))), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
 
   CPU (h_accum) = SRADI (SLLDI (SUBDI (OPRND (accum), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (OPRND (src1))), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8);
   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));


@@ -3116,16 +3247,16 @@ m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)),
 #undef OPRND
 }
 
 #undef OPRND
 }
 

-/* Perform machl1: machl1 $src1,$src2.  */
+/* Perform maclh1: maclh1 $src1,$src2.  */

 CIA
 CIA

-SEM_FN_NAME (m32rx,machl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
+SEM_FN_NAME (m32rx,maclh1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)

 {
   insn_t insn = SEM_INSN (sem_arg);
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_51_macwu1.f
+#define OPRND(f) par_exec->operands.fmt_53_macwu1.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;

-  EXTRACT_FMT_51_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
-  EXTRACT_FMT_51_MACWU1_CODE
+  EXTRACT_FMT_53_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_53_MACWU1_CODE

 
 m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums_1), SRADI (SLLDI (MULDI (EXTSIDI (SRASI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8));
   TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1));
 
 m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums_1), SRADI (SLLDI (MULDI (EXTSIDI (SRASI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8));
   TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1));


@@ -3147,11 +3278,11 @@ CIA
 SEM_FN_NAME (m32rx,sc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,sc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_53_sc.f
+#define OPRND(f) par_exec->operands.fmt_55_sc.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;

-  EXTRACT_FMT_53_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-  EXTRACT_FMT_53_SC_CODE
+  EXTRACT_FMT_55_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_55_SC_CODE

 
 if (OPRND (condbit)) {
   CPU (h_abort) = 1;
 
 if (OPRND (condbit)) {
   CPU (h_abort) = 1;


@@ -3174,11 +3305,11 @@ CIA
 SEM_FN_NAME (m32rx,snc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);
 SEM_FN_NAME (m32rx,snc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 {
   insn_t insn = SEM_INSN (sem_arg);

-#define OPRND(f) par_exec->operands.fmt_53_sc.f
+#define OPRND(f) par_exec->operands.fmt_55_sc.f

   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   CIA new_pc = CPU (h_pc) + 2;

-  EXTRACT_FMT_53_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-  EXTRACT_FMT_53_SC_CODE
+  EXTRACT_FMT_55_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+  EXTRACT_FMT_55_SC_CODE

 
 if (NOTBI (OPRND (condbit))) {
   CPU (h_abort) = 1;
 
 if (NOTBI (OPRND (condbit))) {
   CPU (h_abort) = 1;