+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id)
+{
+ switch (gmac_id) {
+ case PERIPH_ID_GMAC:
+ /* set rgmii m1 pins mux */
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B0_SEL_MASK |
+ GPIO1B1_SEL_MASK |
+ GPIO1B2_SEL_MASK |
+ GPIO1B3_SEL_MASK |
+ GPIO1B4_SEL_MASK |
+ GPIO1B5_SEL_MASK |
+ GPIO1B6_SEL_MASK |
+ GPIO1B7_SEL_MASK,
+ GPIO1B0_GMAC_TXD1M1 << GPIO1B0_SEL_SHIFT |
+ GPIO1B1_GMAC_TXD0M1 << GPIO1B1_SEL_SHIFT |
+ GPIO1B2_GMAC_RXD1M1 << GPIO1B2_SEL_SHIFT |
+ GPIO1B3_GMAC_RXD0M1 << GPIO1B3_SEL_SHIFT |
+ GPIO1B4_GMAC_TXCLKM1 << GPIO1B4_SEL_SHIFT |
+ GPIO1B5_GMAC_RXCLKM1 << GPIO1B5_SEL_SHIFT |
+ GPIO1B6_GMAC_RXD3M1 << GPIO1B6_SEL_SHIFT |
+ GPIO1B7_GMAC_RXD2M1 << GPIO1B7_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C0_SEL_MASK |
+ GPIO1C1_SEL_MASK |
+ GPIO1C3_SEL_MASK |
+ GPIO1C5_SEL_MASK |
+ GPIO1C6_SEL_MASK |
+ GPIO1C7_SEL_MASK,
+ GPIO1C0_GMAC_TXD3M1 << GPIO1C0_SEL_SHIFT |
+ GPIO1C1_GMAC_TXD2M1 << GPIO1C1_SEL_SHIFT |
+ GPIO1C3_GMAC_MDIOM1 << GPIO1C3_SEL_SHIFT |
+ GPIO1C5_GMAC_CLKM1 << GPIO1C5_SEL_SHIFT |
+ GPIO1C6_GMAC_RXDVM1 << GPIO1C6_SEL_SHIFT |
+ GPIO1C7_GMAC_MDCM1 << GPIO1C7_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D1_SEL_MASK,
+ GPIO1D1_GMAC_TXENM1 << GPIO1D1_SEL_SHIFT);
+
+ /* set rgmii m0 tx pins mux */
+ rk_clrsetreg(&grf->gpio0b_iomux,
+ GPIO0B0_SEL_MASK |
+ GPIO0B4_SEL_MASK,
+ GPIO0B0_GAMC_CLKTXM0 << GPIO0B0_SEL_SHIFT |
+ GPIO0B4_GAMC_TXENM0 << GPIO0B4_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio0c_iomux,
+ GPIO0C0_SEL_MASK |
+ GPIO0C1_SEL_MASK |
+ GPIO0C6_SEL_MASK |
+ GPIO0C7_SEL_MASK,
+ GPIO0C0_GAMC_TXD1M0 << GPIO0C0_SEL_SHIFT |
+ GPIO0C1_GAMC_TXD0M0 << GPIO0C1_SEL_SHIFT |
+ GPIO0C6_GAMC_TXD2M0 << GPIO0C6_SEL_SHIFT |
+ GPIO0C7_GAMC_TXD3M0 << GPIO0C7_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio0d_iomux,
+ GPIO0D0_SEL_MASK,
+ GPIO0D0_GMAC_CLKM0 << GPIO0D0_SEL_SHIFT);
+
+ /* set com mux */
+ rk_clrsetreg(&grf->com_iomux,
+ IOMUX_SEL_GMAC_MASK |
+ IOMUX_SEL_GMACM1_OPTIMIZATION_MASK,
+ IOMUX_SEL_GMAC_M1 << IOMUX_SEL_GMAC_SHIFT |
+ IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER <<
+ IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT);
+
+ /*
+ * set rgmii m1 tx pins to 12ma drive-strength,
+ * and clean others to 2ma.
+ */
+ rk_clrsetreg(&grf->gpio1b_e,
+ GRF_GPIO1B0_E_MASK |
+ GRF_GPIO1B1_E_MASK |
+ GRF_GPIO1B2_E_MASK |
+ GRF_GPIO1B3_E_MASK |
+ GRF_GPIO1B4_E_MASK |
+ GRF_GPIO1B5_E_MASK |
+ GRF_GPIO1B6_E_MASK |
+ GRF_GPIO1B7_E_MASK,
+ GPIO_BIAS_12MA << GRF_GPIO1B0_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO1B1_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B2_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B3_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO1B4_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B5_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B6_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1B7_E_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1c_e,
+ GRF_GPIO1C0_E_MASK |
+ GRF_GPIO1C1_E_MASK |
+ GRF_GPIO1C3_E_MASK |
+ GRF_GPIO1C5_E_MASK |
+ GRF_GPIO1C6_E_MASK |
+ GRF_GPIO1C7_E_MASK,
+ GPIO_BIAS_12MA << GRF_GPIO1C0_E_SHIFT |
+ GPIO_BIAS_12MA << GRF_GPIO1C1_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1C3_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1C5_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1C6_E_SHIFT |
+ GPIO_BIAS_2MA << GRF_GPIO1C7_E_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1d_e,
+ GRF_GPIO1D1_E_MASK,
+ GPIO_BIAS_12MA << GRF_GPIO1D1_E_SHIFT);
+ break;
+ default:
+ debug("gmac id = %d iomux error!\n", gmac_id);
+ break;
+ }
+}
+#endif
+