Document the UNCACHEABLE_ADDR definitions for footbridge and SA1100
so that we know where they're located and/or what they're accessing.
Change RiscPC to calculate the UNCACHEABLE_ADDR value from FLUSH_BASE
as that's where we locate that.
UNCACHEABLE_ADDR is used to perform an uncached access (ARMv4
terminology) necessary to force a CPU clock-switch to the memory-
speed clock, as required for entering WFI.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
#define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5))
#define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6))
#define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5))
#define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6))
-#define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108)
+#define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) /* CSR_ROMBASEMASK */
#define SCREEN_END 0xdfc00000
#define SCREEN_BASE 0xdf800000
#define SCREEN_END 0xdfc00000
#define SCREEN_BASE 0xdf800000
-#define UNCACHEABLE_ADDR 0xdf010000
+#define UNCACHEABLE_ADDR (FLUSH_BASE + 0x10000)
#define __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
-#define UNCACHEABLE_ADDR 0xfa050000
+#define UNCACHEABLE_ADDR 0xfa050000 /* ICIP */