Since hardware revision 1.11.0, the following interrupt status
registers are now W1C (i.e., write 1 clear):
1. Interrupt Source Group 0 Register (0x144) (EP0 Abort: BIT5)
2. Interrupt Source Group 2 Register (0x14C) (All bits)
And before revision 1.11.0, these registers are all R/W.
Which means software must write a 0 to clear the status.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Marek Vasut <marex@denx.de>
/* CX interrupts */
if (gisr & GISR_GRP0) {
st = readl(®s->gisr0);
/* CX interrupts */
if (gisr & GISR_GRP0) {
st = readl(®s->gisr0);
+ /*
+ * Write 1 and then 0 works for both W1C & RW.
+ *
+ * HW v1.11.0+: It's a W1C register (write 1 clear)
+ * HW v1.10.0-: It's a R/W register (write 0 clear)
+ */
+ writel(st & GISR0_CXABORT, ®s->gisr0);
writel(0, ®s->gisr0);
if (st & GISR0_CXERR)
writel(0, ®s->gisr0);
if (st & GISR0_CXERR)
/* Device Status Interrupts */
if (gisr & GISR_GRP2) {
st = readl(®s->gisr2);
/* Device Status Interrupts */
if (gisr & GISR_GRP2) {
st = readl(®s->gisr2);
+ /*
+ * Write 1 and then 0 works for both W1C & RW.
+ *
+ * HW v1.11.0+: It's a W1C register (write 1 clear)
+ * HW v1.10.0-: It's a R/W register (write 0 clear)
+ */
+ writel(st, ®s->gisr2);
writel(0, ®s->gisr2);
if (st & GISR2_RESET)
writel(0, ®s->gisr2);
if (st & GISR2_RESET)