microblaze: Improve srl

write_carry only looks at bit zero, no need to mask out the others.

Meassured a 12% speed improvement in linux-user srl loops.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>

diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 916db15c9992facb68f15cd468b2abddbe282071..93aafac6919e061dbc7235769611d13b02344b8c 100644 (file)
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -780,13 +780,10 @@ static void dec_bit(DisasContext *dc)
         case 0x1:
         case 0x41:
             /* srl.  */
         case 0x1:
         case 0x41:
             /* srl.  */

-            t0 = tcg_temp_new();

             LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
 
             LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
 

-            /* Update carry.  */
-            tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
-            write_carry(dc, t0);
-            tcg_temp_free(t0);
+            /* Update carry. Note that write carry only looks at the LSB.  */
+            write_carry(dc, cpu_R[dc->ra]);

             if (dc->rd) {
                 if (op == 0x41)
                     tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
             if (dc->rd) {
                 if (op == 0x41)
                     tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);