+static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
+{
+ /* read mode */
+ tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
+ (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
+ RENESAS_SDHI_SCC_TMPPORT5);
+
+ /* access start and stop */
+ tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
+ RENESAS_SDHI_SCC_TMPPORT4);
+ tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
+
+ return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
+}
+
+static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
+{
+ /* write mode */
+ tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
+ (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
+ RENESAS_SDHI_SCC_TMPPORT5);
+ tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
+
+ /* access start and stop */
+ tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
+ RENESAS_SDHI_SCC_TMPPORT4);
+ tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
+}
+
+static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
+{
+ u32 calib_code;
+
+ if (!priv->adjust_hs400_enable)
+ return;
+
+ if (!priv->needs_adjust_hs400)
+ return;
+
+ /*
+ * Enabled Manual adjust HS400 mode
+ *
+ * 1) Disabled Write Protect
+ * W(addr=0x00, WP_DISABLE_CODE)
+ * 2) Read Calibration code and adjust
+ * R(addr=0x26) - adjust value
+ * 3) Enabled Manual Calibration
+ * W(addr=0x22, manual mode | Calibration code)
+ * 4) Set Offset value to TMPPORT3 Reg
+ */
+ sd_scc_tmpport_write32(priv, 0x00,
+ RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
+ calib_code = sd_scc_tmpport_read32(priv, 0x26);
+ calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
+ if (calib_code > priv->adjust_hs400_calibrate)
+ calib_code -= priv->adjust_hs400_calibrate;
+ else
+ calib_code = 0;
+ sd_scc_tmpport_write32(priv, 0x22,
+ RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
+ calib_code);
+ tmio_sd_writel(priv, priv->adjust_hs400_offset,
+ RENESAS_SDHI_SCC_TMPPORT3);
+
+ /* Clear flag */
+ priv->needs_adjust_hs400 = false;
+}
+
+static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
+{
+
+ /* Disabled Manual adjust HS400 mode
+ *
+ * 1) Disabled Write Protect
+ * W(addr=0x00, WP_DISABLE_CODE)
+ * 2) Disabled Manual Calibration
+ * W(addr=0x22, 0)
+ * 3) Clear offset value to TMPPORT3 Reg
+ */
+ sd_scc_tmpport_write32(priv, 0x00,
+ RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
+ sd_scc_tmpport_write32(priv, 0x22, 0);
+ tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
+}
+