drm/i915/pps: move pps (panel) modeset asserts to intel_pps.c

Move assert_panel_unlocked() to intel_pps.c and rename
assert_pps_unlocked(). Keep the functionality and the assert code
together.

There's still a bit of a split between the eDP PPS usage in intel_pps.c
and all the other PPS usage, and assert_pps_unlocked() is arguably more
related to the latter. However, intel_pps.c is the best fit for anything
touching the PPS registers.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a9b77692a145891789eefb0447e082cfc22aaa85.1632992608.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 05e42903bde0dd99c762bf59764c748bf7bb27ee..34201e71593bcf06898e878d15d06496facc4d7c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -428,64 +428,6 @@ void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
                        onoff(state), onoff(cur_state));
 }
 
                        onoff(state), onoff(cur_state));
 }
 

-void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
-{
-       i915_reg_t pp_reg;
-       u32 val;
-       enum pipe panel_pipe = INVALID_PIPE;
-       bool locked = true;
-
-       if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
-               return;
-
-       if (HAS_PCH_SPLIT(dev_priv)) {
-               u32 port_sel;
-
-               pp_reg = PP_CONTROL(0);
-               port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
-
-               switch (port_sel) {
-               case PANEL_PORT_SELECT_LVDS:
-                       intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
-                       break;
-               case PANEL_PORT_SELECT_DPA:
-                       g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
-                       break;
-               case PANEL_PORT_SELECT_DPC:
-                       g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
-                       break;
-               case PANEL_PORT_SELECT_DPD:
-                       g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
-                       break;
-               default:
-                       MISSING_CASE(port_sel);
-                       break;
-               }
-       } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-               /* presumably write lock depends on pipe, not port select */
-               pp_reg = PP_CONTROL(pipe);
-               panel_pipe = pipe;
-       } else {
-               u32 port_sel;
-
-               pp_reg = PP_CONTROL(0);
-               port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
-
-               drm_WARN_ON(&dev_priv->drm,
-                           port_sel != PANEL_PORT_SELECT_LVDS);
-               intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
-       }
-
-       val = intel_de_read(dev_priv, pp_reg);
-       if (!(val & PANEL_POWER_ON) ||
-           ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
-               locked = false;
-
-       I915_STATE_WARN(panel_pipe == pipe && locked,
-            "panel assertion failure, pipe %c regs locked\n",
-            pipe_name(pipe));
-}
-

 void assert_transcoder(struct drm_i915_private *dev_priv,
                       enum transcoder cpu_transcoder, bool state)
 {
 void assert_transcoder(struct drm_i915_private *dev_priv,
                       enum transcoder cpu_transcoder, bool state)
 {


@@ -2128,7 +2070,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state,
        intel_enable_shared_dpll(crtc_state);
 
        /* set transcoder timing, panel must allow it */
        intel_enable_shared_dpll(crtc_state);
 
        /* set transcoder timing, panel must allow it */

-       assert_panel_unlocked(dev_priv, pipe);
+       assert_pps_unlocked(dev_priv, pipe);

        ilk_pch_transcoder_set_timings(crtc_state, pipe);
 
        intel_fdi_normal_train(crtc);
        ilk_pch_transcoder_set_timings(crtc_state, pipe);
 
        intel_fdi_normal_train(crtc);

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 8cb3bb33cbe0b6408ec43770c8dff40ce4e96a30..5306d119b2c035ca747cffed2394646028f8bbd4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -645,8 +645,6 @@ void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
 int intel_modeset_all_pipes(struct intel_atomic_state *state);
 
 /* modesetting asserts */
 int intel_modeset_all_pipes(struct intel_atomic_state *state);
 
 /* modesetting asserts */

-void assert_panel_unlocked(struct drm_i915_private *dev_priv,
-                          enum pipe pipe);

 void assert_pll(struct drm_i915_private *dev_priv,
                enum pipe pipe, bool state);
 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 void assert_pll(struct drm_i915_private *dev_priv,
                enum pipe pipe, bool state);
 #define assert_pll_enabled(d, p) assert_pll(d, p, true)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 784e3ee658b5c15709ce3af971429d62a30c2754..66784204f6f75e9f270b32be0210e1659f91f1f6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -2,16 +2,19 @@
 /*
  * Copyright © 2020 Intel Corporation
  */
 /*
  * Copyright © 2020 Intel Corporation
  */

+

 #include <linux/kernel.h>
 #include <linux/kernel.h>

+

 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_crtc.h"
 #include "intel_de.h"

-#include "intel_display_types.h"

 #include "intel_display.h"
 #include "intel_display.h"

+#include "intel_display_types.h"

 #include "intel_dpll.h"
 #include "intel_lvds.h"
 #include "intel_panel.h"
 #include "intel_dpll.h"
 #include "intel_lvds.h"
 #include "intel_panel.h"

+#include "intel_pps.h"

 #include "intel_sideband.h"
 #include "intel_sideband.h"

-#include "display/intel_snps_phy.h"
+#include "intel_snps_phy.h"

 
 struct intel_limit {
        struct {
 
 struct intel_limit {
        struct {


@@ -1438,7 +1441,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
 
        /* PLL is protected by panel, make sure we can write it */
        if (i9xx_has_pps(dev_priv))
 
        /* PLL is protected by panel, make sure we can write it */
        if (i9xx_has_pps(dev_priv))

-               assert_panel_unlocked(dev_priv, pipe);
+               assert_pps_unlocked(dev_priv, pipe);

 
        intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0);
        intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1);
 
        intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0);
        intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1);


@@ -1617,7 +1620,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
        assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
 
        /* PLL is protected by panel, make sure we can write it */
        assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
 
        /* PLL is protected by panel, make sure we can write it */

-       assert_panel_unlocked(dev_priv, pipe);
+       assert_pps_unlocked(dev_priv, pipe);

 
        /* Enable Refclk */
        intel_de_write(dev_priv, DPLL(pipe),
 
        /* Enable Refclk */
        intel_de_write(dev_priv, DPLL(pipe),


@@ -1769,7 +1772,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
        assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
 
        /* PLL is protected by panel, make sure we can write it */
        assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
 
        /* PLL is protected by panel, make sure we can write it */

-       assert_panel_unlocked(dev_priv, pipe);
+       assert_pps_unlocked(dev_priv, pipe);

 
        /* Enable Refclk and SSC */
        intel_de_write(dev_priv, DPLL(pipe),
 
        /* Enable Refclk and SSC */
        intel_de_write(dev_priv, DPLL(pipe),

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index a36ec4a818ff518fc6a9fb945f140676a08abf7a..e9c679bb1b2ebeb18fcb59c4201b07e0ae09e185 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -9,6 +9,7 @@
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dpll.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dpll.h"

+#include "intel_lvds.h"

 #include "intel_pps.h"
 
 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 #include "intel_pps.h"
 
 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,


@@ -1408,3 +1409,61 @@ void intel_pps_setup(struct drm_i915_private *i915)
        else
                i915->pps_mmio_base = PPS_BASE;
 }
        else
                i915->pps_mmio_base = PPS_BASE;
 }

+
+void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
+{
+       i915_reg_t pp_reg;
+       u32 val;
+       enum pipe panel_pipe = INVALID_PIPE;
+       bool locked = true;
+
+       if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
+               return;
+
+       if (HAS_PCH_SPLIT(dev_priv)) {
+               u32 port_sel;
+
+               pp_reg = PP_CONTROL(0);
+               port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
+
+               switch (port_sel) {
+               case PANEL_PORT_SELECT_LVDS:
+                       intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
+                       break;
+               case PANEL_PORT_SELECT_DPA:
+                       g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
+                       break;
+               case PANEL_PORT_SELECT_DPC:
+                       g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
+                       break;
+               case PANEL_PORT_SELECT_DPD:
+                       g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
+                       break;
+               default:
+                       MISSING_CASE(port_sel);
+                       break;
+               }
+       } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+               /* presumably write lock depends on pipe, not port select */
+               pp_reg = PP_CONTROL(pipe);
+               panel_pipe = pipe;
+       } else {
+               u32 port_sel;
+
+               pp_reg = PP_CONTROL(0);
+               port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
+
+               drm_WARN_ON(&dev_priv->drm,
+                           port_sel != PANEL_PORT_SELECT_LVDS);
+               intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
+       }
+
+       val = intel_de_read(dev_priv, pp_reg);
+       if (!(val & PANEL_POWER_ON) ||
+           ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
+               locked = false;
+
+       I915_STATE_WARN(panel_pipe == pipe && locked,
+                       "panel assertion failure, pipe %c regs locked\n",
+                       pipe_name(pipe));
+}

diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index fbbcca782e7b6f8e5fe2e693d2d4db9cfc1b5ab2..fbb47f6f453e49353430ff00a406b2c2f732d90a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -10,6 +10,7 @@
 
 #include "intel_wakeref.h"
 
 
 #include "intel_wakeref.h"
 

+enum pipe;

 struct drm_i915_private;
 struct intel_connector;
 struct intel_crtc_state;
 struct drm_i915_private;
 struct intel_connector;
 struct intel_crtc_state;


@@ -49,4 +50,6 @@ void vlv_pps_init(struct intel_encoder *encoder,
 void intel_pps_unlock_regs_wa(struct drm_i915_private *i915);
 void intel_pps_setup(struct drm_i915_private *i915);
 
 void intel_pps_unlock_regs_wa(struct drm_i915_private *i915);
 void intel_pps_setup(struct drm_i915_private *i915);
 

+void assert_pps_unlocked(struct drm_i915_private *i915, enum pipe pipe);
+

 #endif /* __INTEL_PPS_H__ */
 #endif /* __INTEL_PPS_H__ */