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3db7b2b)
This converts the following to Kconfig:
CONFIG_BTB
Signed-off-by: Tom Rini <trini@konsulko.com>
13 files changed:
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A005125
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A005125
select FSL_LAW
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_NMG_DDR120
select FSL_LAW
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_NMG_DDR120
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_HAS_SERDES
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_HAS_SERDES
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004508
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004508
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004477
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004477
bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
depends on MPC85xx
bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
depends on MPC85xx
+config BTB
+ bool "toggle branch predition"
+
config BOOKE
bool
default y
config BOOKE
bool
default y
imply CMD_PCI
help
Enble PowerPC E500MC core
config E6500
bool
imply CMD_PCI
help
Enble PowerPC E500MC core
config E6500
bool
help
Enable PowerPC E6500 core
help
Enable PowerPC E6500 core
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
/*
* Only possible on E500 Version 2 or newer cores.
/*
* Only possible on E500 Version 2 or newer cores.
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_ENABLE_36BIT_PHYS
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_ENABLE_36BIT_PHYS
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */