rockchip: rk3328: add soc basic support

RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU.
It supports two USB2.0 EHCI ports. Other interfaces are very
much like RK3288, the DRAM are 32bit width address and support
address from 0 to 4GB-16MB range.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error:
Signed-off-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 565908a..bf8e6be 100644 (file)
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -38,6 +38,16 @@ config ROCKCHIP_RK3288
          and video codec support. Peripherals include Gigabit Ethernet,
          USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
 
          and video codec support. Peripherals include Gigabit Ethernet,
          USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
 

+config ROCKCHIP_RK3328
+       bool "Support Rockchip RK3328"
+       select ARM64
+       help
+         The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
+         including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
+         video interfaces supporting HDMI and eDP, several DDR3 options
+         and video codec support. Peripherals include Gigabit Ethernet,
+         USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+

 config ROCKCHIP_RK3399
        bool "Support Rockchip RK3399"
        select ARM64
 config ROCKCHIP_RK3399
        bool "Support Rockchip RK3399"
        select ARM64


@@ -70,5 +80,6 @@ config SPL_MMC_SUPPORT
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
 source "arch/arm/mach-rockchip/rk3188/Kconfig"
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
 source "arch/arm/mach-rockchip/rk3188/Kconfig"
 source "arch/arm/mach-rockchip/rk3288/Kconfig"

+source "arch/arm/mach-rockchip/rk3328/Kconfig"

 source "arch/arm/mach-rockchip/rk3399/Kconfig"
 endif
 source "arch/arm/mach-rockchip/rk3399/Kconfig"
 endif

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 151fa2d..6b251c7 100644 (file)
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -28,4 +28,5 @@ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
 endif
 
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
 endif
 
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/

+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/

 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/

diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/arch/arm/mach-rockchip/rk3328/Makefile b/arch/arm/mach-rockchip/rk3328/Makefile
new file mode 100644 (file)
index 0000000..8ecf8ee
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3328/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += rk3328.o
+obj-y += syscon_rk3328.o

diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
new file mode 100644 (file)
index 0000000..857f014
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+
+static struct mm_region rk3328_mem_map[] = {
+       {
+               .virt = 0x0UL,
+               .phys = 0x0UL,
+               .size = 0x80000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0xf0000000UL,
+               .phys = 0xf0000000UL,
+               .size = 0x10000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* List terminator */
+               0,
+       }
+};
+
+struct mm_region *mem_map = rk3328_mem_map;
+
+int arch_cpu_init(void)
+{
+       /* We do some SoC one time setting here. */
+
+       return 0;
+}

diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
new file mode 100644 (file)
index 0000000..a1a368f
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <dm.h>
+#include <syscon.h>
+
+static const struct udevice_id rk3328_syscon_ids[] = {
+       { .compatible = "rockchip,rk3328-grf", .data = ROCKCHIP_SYSCON_GRF },
+};
+
+U_BOOT_DRIVER(syscon_rk3328) = {
+       .name = "rk3328_syscon",
+       .id = UCLASS_SYSCON,
+       .of_match = rk3328_syscon_ids,
+};

diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
new file mode 100644 (file)
index 0000000..eacf716
--- /dev/null
+++ b/include/configs/rk3328_common.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_RK3328_COMMON_H
+#define __CONFIG_RK3328_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_ENV_SIZE                        0x2000
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_BAUDRATE                        1500000
+#define CONFIG_SYS_MALLOC_LEN          (32 << 20)
+#define CONFIG_SYS_CBSIZE              1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_SYS_TEXT_BASE           0x00200000
+#define CONFIG_SYS_INIT_SP_ADDR                0x00300000
+#define CONFIG_SYS_LOAD_ADDR           0x00800800
+
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* 64M */
+
+/* MMC/SD IP block */
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_FS_EXT4
+
+/* RAW SD card / eMMC locations. */
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     (128 << 10)
+
+/* FAT sd card locations. */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
+#define CONFIG_SYS_SDRAM_BASE          0
+#define CONFIG_NR_DRAM_BANKS           1
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+
+#ifndef CONFIG_SPL_BUILD
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+       "scriptaddr=0x00500000\0" \
+       "pxefile_addr_r=0x00600000\0" \
+       "fdt_addr_r=0x01f00000\0" \
+       "kernel_addr_r=0x02000000\0" \
+       "ramdisk_addr_r=0x04000000\0"
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       ENV_MEM_LAYOUT_SETTINGS \
+       "partitions=" PARTS_DEFAULT \
+       BOOTENV
+
+#endif
+
+#endif