* doc/as.texinfo (Overview): Remove @samp from MIPS ISA names.

	* doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names.
	Replace @sc{mips16} with literal `MIPS16'.
	(MIPS ISA): Replace @sc{mips3} with literal `MIPS III'.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d998e3b..5e7a493 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2013-06-26  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * doc/as.texinfo (Overview): Remove @samp from MIPS ISA names.
+       * doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names.
+       Replace @sc{mips16} with literal `MIPS16'.
+       (MIPS ISA): Replace @sc{mips3} with literal `MIPS III'.
+

 2013-06-26  Yufeng Zhang  <yufeng.zhang@arm.com>
 
        * config/tc-aarch64.c (reloc_table): Replace
 2013-06-26  Yufeng Zhang  <yufeng.zhang@arm.com>
 
        * config/tc-aarch64.c (reloc_table): Replace

diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index b02a34d..d1e397f 100644 (file)
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -1253,11 +1253,8 @@ Generate code for a particular MIPS Instruction Set Architecture level.
 alias for @samp{-march=r6000}, @samp{-mips3} is an alias for
 @samp{-march=r4000} and @samp{-mips4} is an alias for @samp{-march=r8000}.
 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and
 alias for @samp{-march=r6000}, @samp{-mips3} is an alias for
 @samp{-march=r4000} and @samp{-mips4} is an alias for @samp{-march=r8000}.
 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and

-@samp{-mips64r2}
-correspond to generic
-@samp{MIPS V}, @samp{MIPS32}, @samp{MIPS32 Release 2}, @samp{MIPS64},
-and @samp{MIPS64 Release 2}
-ISA processors, respectively.
+@samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
+MIPS64, and MIPS64 Release 2 ISA processors, respectively.

 
 @item -march=@var{cpu}
 Generate code for a particular MIPS CPU.
 
 @item -march=@var{cpu}
 Generate code for a particular MIPS CPU.

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index f377ef3..741237a 100644 (file)
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -87,15 +87,12 @@ VxWorks-style position-independent macro expansions.
 Generate code for a particular MIPS Instruction Set Architecture level.
 @samp{-mips1} corresponds to the R2000 and R3000 processors,
 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
 Generate code for a particular MIPS Instruction Set Architecture level.
 @samp{-mips1} corresponds to the R2000 and R3000 processors,
 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the

-R4000 processor, and @samp{-mips4} to the R8000 and
-R10000 processors.  @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
-@samp{-mips64}, and @samp{-mips64r2}
-correspond to generic
-@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
-and @sc{MIPS64 Release 2}
-ISA processors, respectively.  You can also switch
-instruction sets during the assembly; see @ref{MIPS ISA, Directives to
-override the ISA level}.
+R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
+@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and
+@samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
+MIPS64, and MIPS64 Release 2 ISA processors, respectively.  You can also
+switch instruction sets during the assembly; see @ref{MIPS ISA,
+Directives to override the ISA level}.

 
 @item -mgp32
 @itemx -mfp32
 
 @item -mgp32
 @itemx -mfp32


@@ -414,7 +411,7 @@ be relaxed with the use of a longer sequence involving another branch,
 however this has not been implemented and if their target turns out of
 reach, they produce an error even if branch relaxation is enabled.
 
 however this has not been implemented and if their target turns out of
 reach, they produce an error even if branch relaxation is enabled.
 

-Also no @sc{mips16} branches are ever relaxed.
+Also no MIPS16 branches are ever relaxed.

 
 By default @samp{--no-relax-branch} is selected, causing any out-of-range
 branches to produce an error.
 
 By default @samp{--no-relax-branch} is selected, causing any out-of-range
 branches to produce an error.


@@ -636,7 +633,7 @@ assembly.  @code{.set mips@var{n}} affects not only which instructions
 are permitted, but also how certain macros are expanded.  @code{.set
 mips0} restores the ISA level to its original level: either the
 level you selected with command line options, or the default for your
 are permitted, but also how certain macros are expanded.  @code{.set
 mips0} restores the ISA level to its original level: either the
 level you selected with command line options, or the default for your

-configuration.  You can use this feature to permit specific @sc{mips3}
+configuration.  You can use this feature to permit specific MIPS III

 instructions while assembling in 32 bit mode.  Use this directive with
 care!
 
 instructions while assembling in 32 bit mode.  Use this directive with
 care!