2013-06-17 Catherine Moore <clm@codesourcery.com>

	    Maciej W. Rozycki  <macro@codesourcery.com>
	    Chao-Ying Fu  <fu@mips.com>

	gas/testsuite/
	* gas/mips/mips.exp: Run new tests.
	* gas/mips/eva.d: New.
	* gas/mips/eva.s: New.
	* gas/mips/micromips@eva.d: New.

	gas/
	* config/tc-mips.c (mips_set_options): Add ase_eva.
	(mips_set_options mips_opts): Add ase_eva.
	(file_ase_eva): Declare.
	(ISA_SUPPORTS_EVA_ASE): Define.
	(IS_SEXT_9BIT_NUM): Define.
	(MIPS_CPU_ASE_EVA): Define.
	(is_opcode_valid): Add support for ase_eva.
	(macro_build): Likewise.
	(macro): Likewise.
	(validate_mips_insn): Likewise.
	(validate_micromips_insn): Likewise.
	(mips_ip): Likewise.
	(options): Add OPTION_EVA and OPTION_NO_EVA.
	(md_longopts): Add -meva and -mno-eva.
	(md_parse_option): Process new options.
	(mips_after_parse_args): Check for valid EVA combinations.
	(s_mipsset): Likewise.

	include/
	* opcode/mips.h (OP_SH_EVAOFFSET): Define.
	(OP_MASK_EVAOFFSET): Define.
	(INSN_ASE_MASK): Delete.
	(ASE_EVA): Define.
	(M_CACHEE_AB, M_CACHEE_OB): New.
	(M_LBE_OB, M_LBE_AB): New.
	(M_LBUE_OB, M_LBUE_AB): New.
	(M_LHE_OB, M_LHE_AB): New.
	(M_LHUE_OB, M_LHUE_AB): New.
	(M_LLE_AB, M_LLE_OB): New.
	(M_LWE_OB, M_LWE_AB): New.
	(M_LWLE_AB, M_LWLE_OB): New.
	(M_LWRE_AB, M_LWRE_OB): New.
	(M_PREFE_AB, M_PREFE_OB): New.
	(M_SCE_AB, M_SCE_OB): New.
	(M_SBE_OB, M_SBE_AB): New.
	(M_SHE_OB, M_SHE_AB): New.
	(M_SWE_OB, M_SWE_AB): New.
	(M_SWLE_AB, M_SWLE_OB): New.
	(M_SWRE_AB, M_SWRE_OB): New.
	(MICROMIPSOP_SH_EVAOFFSET): Define.
	(MICROMIPSOP_MASK_EVAOFFSET): Define.

	opcodes/
	* micromips-opc.c (EVA): Define.
	(TLBINV): Define.
	(micromips_opcodes): Add EVA opcodes.
	* mips-dis.c (mips_arch_choices): Update for ASE_EVA.
	(print_insn_args): Handle EVA offsets.
	(print_insn_micromips): Likewise.
	* mips-opc.c (EVA): Define.
	(TLBINV): Define.
	(mips_builtin_opcodes): Add EVA opcodes.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index fb59e46..9c0147f 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,25 @@
+2013-06-17  Catherine Moore  <clm@codesourcery.com>
+           Maciej W. Rozycki  <macro@codesourcery.com>
+           Chao-Ying Fu  <fu@mips.com>
+
+       * config/tc-mips.c (mips_set_options): Add ase_eva.
+       (mips_set_options mips_opts): Add ase_eva.
+       (file_ase_eva): Declare.
+       (ISA_SUPPORTS_EVA_ASE): Define.
+       (IS_SEXT_9BIT_NUM): Define.
+       (MIPS_CPU_ASE_EVA): Define.
+       (is_opcode_valid): Add support for ase_eva.
+       (macro_build): Likewise.
+       (macro): Likewise.
+       (validate_mips_insn): Likewise.
+       (validate_micromips_insn): Likewise.
+       (mips_ip): Likewise.
+       (options): Add OPTION_EVA and OPTION_NO_EVA.
+       (md_longopts): Add -meva and -mno-eva.
+       (md_parse_option): Process new options.
+       (mips_after_parse_args): Check for valid EVA combinations.
+       (s_mipsset): Likewise.
+

 2013-06-14  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 
        * dwarf2dbg.h (dwarf2_move_insn): Declare.
 2013-06-14  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 
        * dwarf2dbg.h (dwarf2_move_insn): Declare.

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 106f754..c819865 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -216,6 +216,7 @@ struct mips_set_options
   int ase_smartmips;
   int ase_dsp;
   int ase_dspr2;
   int ase_smartmips;
   int ase_dsp;
   int ase_dspr2;

+  int ase_eva;

   int ase_mt;
   int ase_mcu;
   int ase_virt;
   int ase_mt;
   int ase_mcu;
   int ase_virt;


@@ -292,8 +293,9 @@ static int file_mips_single_float = 0;
 static struct mips_set_options mips_opts =
 {
   /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
 static struct mips_set_options mips_opts =
 {
   /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,

-  /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
-  /* ase_mcu */ -1, /* ase_virt */ -1, /* mips16 */ -1,/* micromips */ -1,
+  /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1,
+  /* ase_eva */ -1, /* ase_mt */ -1, /* ase_mcu */ -1,
+  /* ase_virt */ -1, /* mips16 */ -1, /* micromips */ -1,

   /* noreorder */ 0,  /* at */ ATREG, /* warn_about_macros */ 0,
   /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0,
   /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
   /* noreorder */ 0,  /* at */ ATREG, /* warn_about_macros */ 0,
   /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0,
   /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,


@@ -365,6 +367,14 @@ static int file_ase_dspr2;
                                || mips_opts.isa == ISA_MIPS64R2        \
                                || mips_opts.micromips)
 
                                || mips_opts.isa == ISA_MIPS64R2        \
                                || mips_opts.micromips)
 

+/* True if -meva was passed or implied by arguments passed on the
+   command line (e.g., by -march).  */
+static int file_ase_eva;
+
+#define ISA_SUPPORTS_EVA_ASE (mips_opts.isa == ISA_MIPS32R2            \
+                             || mips_opts.isa == ISA_MIPS64R2          \
+                             || mips_opts.micromips)
+

 /* True if -mmt was passed or implied by arguments passed on the
    command line (e.g., by -march).  */
 static int file_ase_mt;
 /* True if -mmt was passed or implied by arguments passed on the
    command line (e.g., by -march).  */
 static int file_ase_mt;


@@ -1217,6 +1227,10 @@ static int mips_relax_branch;
 #define IS_SEXT_12BIT_NUM(x)                                           \
   (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
 
 #define IS_SEXT_12BIT_NUM(x)                                           \
   (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
 

+/* Is the given value a sign-extended 9-bit value?  */
+#define IS_SEXT_9BIT_NUM(x)                                            \
+  (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
+

 /* Is the given value a zero-extended 32-bit value?  Or a negated one?  */
 #define IS_ZEXT_32BIT_NUM(x)                                           \
   (((x) &~ (offsetT) 0xffffffff) == 0                                  \
 /* Is the given value a zero-extended 32-bit value?  Or a negated one?  */
 #define IS_ZEXT_32BIT_NUM(x)                                           \
   (((x) &~ (offsetT) 0xffffffff) == 0                                  \


@@ -1411,6 +1425,7 @@ struct mips_cpu_info
 #define MIPS_CPU_ASE_DSPR2     0x0040  /* CPU implements DSP R2 ASE */
 #define MIPS_CPU_ASE_MCU       0x0080  /* CPU implements MCU ASE */
 #define MIPS_CPU_ASE_VIRT      0x0100  /* CPU implements Virtualization ASE */
 #define MIPS_CPU_ASE_DSPR2     0x0040  /* CPU implements DSP R2 ASE */
 #define MIPS_CPU_ASE_MCU       0x0080  /* CPU implements MCU ASE */
 #define MIPS_CPU_ASE_VIRT      0x0100  /* CPU implements Virtualization ASE */

+#define MIPS_CPU_ASE_EVA       0x0200  /* CPU implements EVA ASE */

 
 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
 
 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);


@@ -2268,6 +2283,8 @@ is_opcode_valid (const struct mips_opcode *mo)
     ase |= ASE_DSP64;
   if (mips_opts.ase_dspr2)
     ase |= ASE_DSPR2;
     ase |= ASE_DSP64;
   if (mips_opts.ase_dspr2)
     ase |= ASE_DSPR2;

+  if (mips_opts.ase_eva)
+    ase |= ASE_EVA;

   if (mips_opts.ase_mt)
     ase |= ASE_MT;
   if (mips_opts.ase_mips3d)
   if (mips_opts.ase_mt)
     ase |= ASE_MT;
   if (mips_opts.ase_mips3d)


@@ -5076,6 +5093,10 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
              INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
              continue;
 
              INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
              continue;
 

+           case 'j':
+             INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int));
+             continue;
+

            default:
              abort ();
            }
            default:
              abort ();
            }


@@ -6453,7 +6474,7 @@ macro (struct mips_cl_insn *ip)
   const char *fmt;
   int likely = 0;
   int coproc = 0;
   const char *fmt;
   int likely = 0;
   int coproc = 0;

-  int off12 = 0;
+  int offbits = 16;

   int call = 0;
   int jals = 0;
   int dbl = 0;
   int call = 0;
   int jals = 0;
   int dbl = 0;


@@ -6461,7 +6482,6 @@ macro (struct mips_cl_insn *ip)
   int ust = 0;
   int lp = 0;
   int ab = 0;
   int ust = 0;
   int lp = 0;
   int ab = 0;

-  int off0 = 0;

   int off;
   offsetT maxnum;
   bfd_reloc_code_real_type r;
   int off;
   offsetT maxnum;
   bfd_reloc_code_real_type r;


@@ -8101,13 +8121,111 @@ macro (struct mips_cl_insn *ip)
 
       break;
 
 
       break;
 

+    case M_LBUE_AB:
+      ab = 1;
+    case M_LBUE_OB:
+      s = "lbue";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_LHUE_AB:
+      ab = 1;
+    case M_LHUE_OB:
+      s = "lhue";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_LBE_AB:
+      ab = 1;
+    case M_LBE_OB:
+      s = "lbe";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_LHE_AB:
+      ab = 1;
+    case M_LHE_OB:
+      s = "lhe";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_LLE_AB:
+      ab = 1;
+    case M_LLE_OB:
+      s = "lle";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_LWE_AB:
+      ab = 1;
+    case M_LWE_OB:
+      s = "lwe";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_LWLE_AB:
+      ab = 1;
+    case M_LWLE_OB:
+      s = "lwle";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_LWRE_AB:
+      ab = 1;
+    case M_LWRE_OB:
+      s = "lwre";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_SBE_AB:
+      ab = 1;
+    case M_SBE_OB:
+      s = "sbe";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_SCE_AB:
+      ab = 1;
+    case M_SCE_OB:
+      s = "sce";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_SHE_AB:
+      ab = 1;
+    case M_SHE_OB:
+      s = "she";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_SWE_AB:
+      ab = 1;
+    case M_SWE_OB:
+      s = "swe";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_SWLE_AB:
+      ab = 1;
+    case M_SWLE_OB:
+      s = "swle";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;
+    case M_SWRE_AB:
+      ab = 1;
+    case M_SWRE_OB:
+      s = "swre";
+      fmt = "t,+j(b)";
+      offbits = 9;
+      goto ld_st;

     case M_ACLR_AB:
       ab = 1;
     case M_ACLR_OB:
       s = "aclr";
       treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
       fmt = "\\,~(b)";
     case M_ACLR_AB:
       ab = 1;
     case M_ACLR_OB:
       s = "aclr";
       treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
       fmt = "\\,~(b)";

-      off12 = 1;
+      offbits = 12;

       goto ld_st;
     case M_ASET_AB:
       ab = 1;
       goto ld_st;
     case M_ASET_AB:
       ab = 1;


@@ -8115,7 +8233,7 @@ macro (struct mips_cl_insn *ip)
       s = "aset";
       treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
       fmt = "\\,~(b)";
       s = "aset";
       treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
       fmt = "\\,~(b)";

-      off12 = 1;
+      offbits = 12;

       goto ld_st;
     case M_LB_AB:
       ab = 1;
       goto ld_st;
     case M_LB_AB:
       ab = 1;


@@ -8162,7 +8280,7 @@ macro (struct mips_cl_insn *ip)
     case M_LWC2_OB:
       s = "lwc2";
       fmt = COP12_FMT;
     case M_LWC2_OB:
       s = "lwc2";
       fmt = COP12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld_st;
       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld_st;


@@ -8179,14 +8297,14 @@ macro (struct mips_cl_insn *ip)
     case M_LWL_OB:
       s = "lwl";
       fmt = MEM12_FMT;
     case M_LWL_OB:
       s = "lwl";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld_st;
     case M_LWR_AB:
       ab = 1;
     case M_LWR_OB:
       s = "lwr";
       fmt = MEM12_FMT;
       goto ld_st;
     case M_LWR_AB:
       ab = 1;
     case M_LWR_OB:
       s = "lwr";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld_st;
     case M_LDC1_AB:
       ab = 1;
       goto ld_st;
     case M_LDC1_AB:
       ab = 1;


@@ -8200,7 +8318,7 @@ macro (struct mips_cl_insn *ip)
     case M_LDC2_OB:
       s = "ldc2";
       fmt = COP12_FMT;
     case M_LDC2_OB:
       s = "ldc2";
       fmt = COP12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld_st;
       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld_st;


@@ -8223,35 +8341,35 @@ macro (struct mips_cl_insn *ip)
     case M_LDL_OB:
       s = "ldl";
       fmt = MEM12_FMT;
     case M_LDL_OB:
       s = "ldl";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld_st;
     case M_LDR_AB:
       ab = 1;
     case M_LDR_OB:
       s = "ldr";
       fmt = MEM12_FMT;
       goto ld_st;
     case M_LDR_AB:
       ab = 1;
     case M_LDR_OB:
       s = "ldr";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld_st;
     case M_LL_AB:
       ab = 1;
     case M_LL_OB:
       s = "ll";
       fmt = MEM12_FMT;
       goto ld_st;
     case M_LL_AB:
       ab = 1;
     case M_LL_OB:
       s = "ll";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld;
     case M_LLD_AB:
       ab = 1;
     case M_LLD_OB:
       s = "lld";
       fmt = MEM12_FMT;
       goto ld;
     case M_LLD_AB:
       ab = 1;
     case M_LLD_OB:
       s = "lld";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld;
     case M_LWU_AB:
       ab = 1;
     case M_LWU_OB:
       s = "lwu";
       fmt = MEM12_FMT;
       goto ld;
     case M_LWU_AB:
       ab = 1;
     case M_LWU_OB:
       s = "lwu";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld;
     case M_LWP_AB:
       ab = 1;
       goto ld;
     case M_LWP_AB:
       ab = 1;


@@ -8259,7 +8377,7 @@ macro (struct mips_cl_insn *ip)
       gas_assert (mips_opts.micromips);
       s = "lwp";
       fmt = "t,~(b)";
       gas_assert (mips_opts.micromips);
       s = "lwp";
       fmt = "t,~(b)";

-      off12 = 1;
+      offbits = 12;

       lp = 1;
       goto ld;
     case M_LDP_AB:
       lp = 1;
       goto ld;
     case M_LDP_AB:


@@ -8268,7 +8386,7 @@ macro (struct mips_cl_insn *ip)
       gas_assert (mips_opts.micromips);
       s = "ldp";
       fmt = "t,~(b)";
       gas_assert (mips_opts.micromips);
       s = "ldp";
       fmt = "t,~(b)";

-      off12 = 1;
+      offbits = 12;

       lp = 1;
       goto ld;
     case M_LWM_AB:
       lp = 1;
       goto ld;
     case M_LWM_AB:


@@ -8277,7 +8395,7 @@ macro (struct mips_cl_insn *ip)
       gas_assert (mips_opts.micromips);
       s = "lwm";
       fmt = "n,~(b)";
       gas_assert (mips_opts.micromips);
       s = "lwm";
       fmt = "n,~(b)";

-      off12 = 1;
+      offbits = 12;

       goto ld_st;
     case M_LDM_AB:
       ab = 1;
       goto ld_st;
     case M_LDM_AB:
       ab = 1;


@@ -8285,7 +8403,7 @@ macro (struct mips_cl_insn *ip)
       gas_assert (mips_opts.micromips);
       s = "ldm";
       fmt = "n,~(b)";
       gas_assert (mips_opts.micromips);
       s = "ldm";
       fmt = "n,~(b)";

-      off12 = 1;
+      offbits = 12;

       goto ld_st;
 
     ld:
       goto ld_st;
 
     ld:


@@ -8331,7 +8449,7 @@ macro (struct mips_cl_insn *ip)
     case M_SWC2_OB:
       s = "swc2";
       fmt = COP12_FMT;
     case M_SWC2_OB:
       s = "swc2";
       fmt = COP12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld_st;
       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld_st;


@@ -8348,42 +8466,56 @@ macro (struct mips_cl_insn *ip)
     case M_SWL_OB:
       s = "swl";
       fmt = MEM12_FMT;
     case M_SWL_OB:
       s = "swl";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld_st;
     case M_SWR_AB:
       ab = 1;
     case M_SWR_OB:
       s = "swr";
       fmt = MEM12_FMT;
       goto ld_st;
     case M_SWR_AB:
       ab = 1;
     case M_SWR_OB:
       s = "swr";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld_st;
     case M_SC_AB:
       ab = 1;
     case M_SC_OB:
       s = "sc";
       fmt = MEM12_FMT;
       goto ld_st;
     case M_SC_AB:
       ab = 1;
     case M_SC_OB:
       s = "sc";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld_st;
     case M_SCD_AB:
       ab = 1;
     case M_SCD_OB:
       s = "scd";
       fmt = MEM12_FMT;
       goto ld_st;
     case M_SCD_AB:
       ab = 1;
     case M_SCD_OB:
       s = "scd";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld_st;
     case M_CACHE_AB:
       ab = 1;
     case M_CACHE_OB:
       s = "cache";
       fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
       goto ld_st;
     case M_CACHE_AB:
       ab = 1;
     case M_CACHE_OB:
       s = "cache";
       fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);
+      goto ld_st;
+    case M_CACHEE_AB:
+      ab = 1;
+    case M_CACHEE_OB:
+      s = "cachee";
+      fmt = "k,+j(b)";
+      offbits = 9;

       goto ld_st;
     case M_PREF_AB:
       ab = 1;
     case M_PREF_OB:
       s = "pref";
       fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
       goto ld_st;
     case M_PREF_AB:
       ab = 1;
     case M_PREF_OB:
       s = "pref";
       fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);
+      goto ld_st;
+    case M_PREFE_AB:
+      ab = 1;
+    case M_PREFE_OB:
+      s = "prefe";
+      fmt = "k,+j(b)";
+      offbits = 9;

       goto ld_st;
     case M_SDC1_AB:
       ab = 1;
       goto ld_st;
     case M_SDC1_AB:
       ab = 1;


@@ -8397,7 +8529,7 @@ macro (struct mips_cl_insn *ip)
     case M_SDC2_OB:
       s = "sdc2";
       fmt = COP12_FMT;
     case M_SDC2_OB:
       s = "sdc2";
       fmt = COP12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld_st;
       /* Itbl support may require additional care here.  */
       coproc = 1;
       goto ld_st;


@@ -8421,14 +8553,14 @@ macro (struct mips_cl_insn *ip)
     case M_SDL_OB:
       s = "sdl";
       fmt = MEM12_FMT;
     case M_SDL_OB:
       s = "sdl";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld_st;
     case M_SDR_AB:
       ab = 1;
     case M_SDR_OB:
       s = "sdr";
       fmt = MEM12_FMT;
       goto ld_st;
     case M_SDR_AB:
       ab = 1;
     case M_SDR_OB:
       s = "sdr";
       fmt = MEM12_FMT;

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       goto ld_st;
     case M_SWP_AB:
       ab = 1;
       goto ld_st;
     case M_SWP_AB:
       ab = 1;


@@ -8436,7 +8568,7 @@ macro (struct mips_cl_insn *ip)
       gas_assert (mips_opts.micromips);
       s = "swp";
       fmt = "t,~(b)";
       gas_assert (mips_opts.micromips);
       s = "swp";
       fmt = "t,~(b)";

-      off12 = 1;
+      offbits = 12;

       goto ld_st;
     case M_SDP_AB:
       ab = 1;
       goto ld_st;
     case M_SDP_AB:
       ab = 1;


@@ -8444,7 +8576,7 @@ macro (struct mips_cl_insn *ip)
       gas_assert (mips_opts.micromips);
       s = "sdp";
       fmt = "t,~(b)";
       gas_assert (mips_opts.micromips);
       s = "sdp";
       fmt = "t,~(b)";

-      off12 = 1;
+      offbits = 12;

       goto ld_st;
     case M_SWM_AB:
       ab = 1;
       goto ld_st;
     case M_SWM_AB:
       ab = 1;


@@ -8452,7 +8584,7 @@ macro (struct mips_cl_insn *ip)
       gas_assert (mips_opts.micromips);
       s = "swm";
       fmt = "n,~(b)";
       gas_assert (mips_opts.micromips);
       s = "swm";
       fmt = "n,~(b)";

-      off12 = 1;
+      offbits = 12;

       goto ld_st;
     case M_SDM_AB:
       ab = 1;
       goto ld_st;
     case M_SDM_AB:
       ab = 1;


@@ -8460,7 +8592,7 @@ macro (struct mips_cl_insn *ip)
       gas_assert (mips_opts.micromips);
       s = "sdm";
       fmt = "n,~(b)";
       gas_assert (mips_opts.micromips);
       s = "sdm";
       fmt = "n,~(b)";

-      off12 = 1;
+      offbits = 12;

 
     ld_st:
       tempreg = AT;
 
     ld_st:
       tempreg = AT;


@@ -8490,18 +8622,25 @@ macro (struct mips_cl_insn *ip)
 
          expr1.X_add_number = offset_expr.X_add_number;
          normalize_address_expr (&expr1);
 
          expr1.X_add_number = offset_expr.X_add_number;
          normalize_address_expr (&expr1);

-         if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
+         if ((offbits == 0 || offbits == 16)
+             && !IS_SEXT_16BIT_NUM (expr1.X_add_number))

            {
              expr1.X_add_number = ((expr1.X_add_number + 0x8000)
                                    & ~(bfd_vma) 0xffff);
              hipart = 1;
            }
            {
              expr1.X_add_number = ((expr1.X_add_number + 0x8000)
                                    & ~(bfd_vma) 0xffff);
              hipart = 1;
            }

-         else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
+         else if (offbits == 12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))

            {
              expr1.X_add_number = ((expr1.X_add_number + 0x800)
                                    & ~(bfd_vma) 0xfff);
              hipart = 1;
            }
            {
              expr1.X_add_number = ((expr1.X_add_number + 0x800)
                                    & ~(bfd_vma) 0xfff);
              hipart = 1;
            }

+         else if (offbits == 9 && !IS_SEXT_9BIT_NUM (expr1.X_add_number))
+           {
+             expr1.X_add_number = ((expr1.X_add_number + 0x100)
+                                   & ~(bfd_vma) 0x1ff);
+             hipart = 1;
+           }

          if (hipart)
            {
              load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
          if (hipart)
            {
              load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);


@@ -8510,7 +8649,7 @@ macro (struct mips_cl_insn *ip)
                             tempreg, tempreg, breg);
              breg = tempreg;
            }
                             tempreg, tempreg, breg);
              breg = tempreg;
            }

-         if (off0)
+         if (offbits == 0)

            {
              if (offset_expr.X_add_number == 0)
                tempreg = breg;
            {
              if (offset_expr.X_add_number == 0)
                tempreg = breg;


@@ -8519,20 +8658,20 @@ macro (struct mips_cl_insn *ip)
                             "t,r,j", tempreg, breg, BFD_RELOC_LO16);
              macro_build (NULL, s, fmt, treg, tempreg);
            }
                             "t,r,j", tempreg, breg, BFD_RELOC_LO16);
              macro_build (NULL, s, fmt, treg, tempreg);
            }

-         else if (!off12)
+         else if (offbits == 16)

            macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
          else
            macro_build (NULL, s, fmt,
                         treg, (unsigned long) offset_expr.X_add_number, breg);
        }
            macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
          else
            macro_build (NULL, s, fmt,
                         treg, (unsigned long) offset_expr.X_add_number, breg);
        }

-      else if (off12 || off0)
+      else if (offbits != 16)

        {
        {

-         /* A 12-bit or 0-bit offset field is too narrow to be used
-            for a low-part relocation, so load the whole address into
-            the auxillary register.  In the case of "A(b)" addresses,
-            we first load absolute address "A" into the register and
-            then add base register "b".  In the case of "o(b)" addresses,
-            we simply need to add 16-bit offset "o" to base register "b", and
+         /* The offset field is too narrow to be used for a low-part
+            relocation, so load the whole address into the auxillary
+            register.  In the case of "A(b)" addresses, we first load
+            absolute address "A" into the register and then add base
+            register "b".  In the case of "o(b)" addresses, we simply
+            need to add 16-bit offset "o" to base register "b", and

             offset_reloc already contains the relocations associated
             with "o".  */
          if (ab)
             offset_reloc already contains the relocations associated
             with "o".  */
          if (ab)


@@ -8547,7 +8686,7 @@ macro (struct mips_cl_insn *ip)
                         tempreg, breg, -1,
                         offset_reloc[0], offset_reloc[1], offset_reloc[2]);
          expr1.X_add_number = 0;
                         tempreg, breg, -1,
                         offset_reloc[0], offset_reloc[1], offset_reloc[2]);
          expr1.X_add_number = 0;

-         if (off0)
+         if (offbits == 0)

            macro_build (NULL, s, fmt, treg, tempreg);
          else
            macro_build (NULL, s, fmt,
            macro_build (NULL, s, fmt, treg, tempreg);
          else
            macro_build (NULL, s, fmt,


@@ -9360,14 +9499,14 @@ macro (struct mips_cl_insn *ip)
       ab = 1;
     case M_SAA_OB:
       s = "saa";
       ab = 1;
     case M_SAA_OB:
       s = "saa";

-      off0 = 1;
+      offbits = 0;

       fmt = "t,(b)";
       goto ld_st;
     case M_SAAD_AB:
       ab = 1;
     case M_SAAD_OB:
       s = "saad";
       fmt = "t,(b)";
       goto ld_st;
     case M_SAAD_AB:
       ab = 1;
     case M_SAAD_OB:
       s = "saad";

-      off0 = 1;
+      offbits = 0;

       fmt = "t,(b)";
       goto ld_st;
 
       fmt = "t,(b)";
       goto ld_st;
 


@@ -10029,7 +10168,7 @@ macro (struct mips_cl_insn *ip)
     case M_ULW:
       s = "lwl";
       s2 = "lwr";
     case M_ULW:
       s = "lwl";
       s2 = "lwr";

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       off = 3;
       goto uld_st;
     case M_ULD_A:
       off = 3;
       goto uld_st;
     case M_ULD_A:


@@ -10037,7 +10176,7 @@ macro (struct mips_cl_insn *ip)
     case M_ULD:
       s = "ldl";
       s2 = "ldr";
     case M_ULD:
       s = "ldl";
       s2 = "ldr";

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       off = 7;
       goto uld_st;
     case M_USH_A:
       off = 7;
       goto uld_st;
     case M_USH_A:


@@ -10053,7 +10192,7 @@ macro (struct mips_cl_insn *ip)
     case M_USW:
       s = "swl";
       s2 = "swr";
     case M_USW:
       s = "swl";
       s2 = "swr";

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       off = 3;
       ust = 1;
       goto uld_st;
       off = 3;
       ust = 1;
       goto uld_st;


@@ -10062,7 +10201,7 @@ macro (struct mips_cl_insn *ip)
     case M_USD:
       s = "sdl";
       s2 = "sdr";
     case M_USD:
       s = "sdl";
       s2 = "sdr";

-      off12 = mips_opts.micromips;
+      offbits = (mips_opts.micromips ? 12 : 16);

       off = 7;
       ust = 1;
 
       off = 7;
       ust = 1;
 


@@ -10084,7 +10223,7 @@ macro (struct mips_cl_insn *ip)
          tempreg = treg;
          ep = &expr1;
        }
          tempreg = treg;
          ep = &expr1;
        }

-      else if (off12
+      else if (offbits == 12

               && (offset_expr.X_op != O_constant
                   || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
                   || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
               && (offset_expr.X_op != O_constant
                   || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
                   || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))


@@ -10110,7 +10249,7 @@ macro (struct mips_cl_insn *ip)
 
       if (!target_big_endian)
        ep->X_add_number += off;
 
       if (!target_big_endian)
        ep->X_add_number += off;

-      if (!off12)
+      if (offbits != 12)

        macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
       else
        macro_build (NULL, s, "t,~(b)",
        macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
       else
        macro_build (NULL, s, "t,~(b)",


@@ -10120,7 +10259,7 @@ macro (struct mips_cl_insn *ip)
        ep->X_add_number -= off;
       else
        ep->X_add_number += off;
        ep->X_add_number -= off;
       else
        ep->X_add_number += off;

-      if (!off12)
+      if (offbits != 12)

        macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
       else
        macro_build (NULL, s2, "t,~(b)",
        macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
       else
        macro_build (NULL, s2, "t,~(b)",


@@ -10471,6 +10610,7 @@ validate_mips_insn (const struct mips_opcode *opc)
          case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
          case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
          case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
          case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
          case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
          case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;

+         case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break;

 
          default:
            as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
 
          default:
            as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),


@@ -10632,6 +10772,7 @@ validate_micromips_insn (const struct mips_opcode *opc)
          case 'F': USE_BITS (INSMSB);  break;
          case 'G': USE_BITS (EXTMSBD); break;
          case 'H': USE_BITS (EXTMSBD); break;
          case 'F': USE_BITS (INSMSB);  break;
          case 'G': USE_BITS (EXTMSBD); break;
          case 'H': USE_BITS (EXTMSBD); break;

+         case 'j': USE_BITS (EVAOFFSET);       break;

          default:
            as_bad (_("Internal error: bad mips opcode "
                      "(unknown extension operand type `%c%c'): %s %s"),
          default:
            as_bad (_("Internal error: bad mips opcode "
                      "(unknown extension operand type `%c%c'): %s %s"),


@@ -11739,6 +11880,35 @@ mips_ip (char *str, struct mips_cl_insn *ip)
                  INSERT_OPERAND (0, FZ, *ip, regno);
                  continue;
 
                  INSERT_OPERAND (0, FZ, *ip, regno);
                  continue;
 

+               case 'j':
+                 {
+                   int shift = 8;
+                   size_t i;
+                   /* Check whether there is only a single bracketed expression
+                      left.  If so, it must be the base register and the
+                      constant must be zero.  */
+                   if (*s == '(' && strchr (s + 1, '(') == 0)
+                     continue;
+
+                   /* If this value won't fit into the offset, then go find
+                      a macro that will generate a 16- or 32-bit offset code
+                      pattern.  */
+                   i = my_getSmallExpression (&imm_expr, imm_reloc, s);
+                   if ((i == 0 && (imm_expr.X_op != O_constant
+                                   || imm_expr.X_add_number >= 1 << shift
+                                   || imm_expr.X_add_number < -1 << shift))
+                       || i > 0)
+                     {
+                       imm_expr.X_op = O_absent;
+                       break;
+                     }
+                   INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip,
+                                   imm_expr.X_add_number);
+                   imm_expr.X_op = O_absent;
+                   s = expr_end;
+                 }
+                 continue;
+

                default:
                  as_bad (_("Internal error: bad %s opcode "
                            "(unknown extension operand type `+%c'): %s %s"),
                default:
                  as_bad (_("Internal error: bad %s opcode "
                            "(unknown extension operand type `+%c'): %s %s"),


@@ -14559,6 +14729,8 @@ enum options
     OPTION_NO_SMARTMIPS,
     OPTION_DSPR2,
     OPTION_NO_DSPR2,
     OPTION_NO_SMARTMIPS,
     OPTION_DSPR2,
     OPTION_NO_DSPR2,

+    OPTION_EVA,
+    OPTION_NO_EVA,

     OPTION_MICROMIPS,
     OPTION_NO_MICROMIPS,
     OPTION_MCU,
     OPTION_MICROMIPS,
     OPTION_NO_MICROMIPS,
     OPTION_MCU,


@@ -14655,6 +14827,8 @@ struct option md_longopts[] =
   {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
   {"mdspr2", no_argument, NULL, OPTION_DSPR2},
   {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
   {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
   {"mdspr2", no_argument, NULL, OPTION_DSPR2},
   {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},

+  {"meva", no_argument, NULL, OPTION_EVA},
+  {"mno-eva", no_argument, NULL, OPTION_NO_EVA},

   {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
   {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
   {"mmcu", no_argument, NULL, OPTION_MCU},
   {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
   {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
   {"mmcu", no_argument, NULL, OPTION_MCU},


@@ -14907,6 +15081,14 @@ md_parse_option (int c, char *arg)
       mips_opts.ase_dsp = 0;
       break;
 
       mips_opts.ase_dsp = 0;
       break;
 

+    case OPTION_EVA:
+      mips_opts.ase_eva = 1;
+      break;
+
+    case OPTION_NO_EVA:
+      mips_opts.ase_eva = 0;
+      break;
+

     case OPTION_MT:
       mips_opts.ase_mt = 1;
       break;
     case OPTION_MT:
       mips_opts.ase_mt = 1;
       break;


@@ -15427,6 +15609,12 @@ mips_after_parse_args (void)
     as_warn (_("%s ISA does not support DSP R2 ASE"),
             mips_cpu_info_from_isa (mips_opts.isa)->name);
 
     as_warn (_("%s ISA does not support DSP R2 ASE"),
             mips_cpu_info_from_isa (mips_opts.isa)->name);
 

+  if (mips_opts.ase_eva == -1)
+    mips_opts.ase_eva = (arch_info->flags & MIPS_CPU_ASE_EVA) ? 1 : 0;
+  if (mips_opts.ase_eva && !ISA_SUPPORTS_EVA_ASE)
+    as_warn (_("%s ISA does not support EVA ASE"),
+            mips_cpu_info_from_isa (mips_opts.isa)->name);
+

   if (mips_opts.ase_mt == -1)
     mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
   if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
   if (mips_opts.ase_mt == -1)
     mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
   if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)


@@ -15451,6 +15639,7 @@ mips_after_parse_args (void)
   file_ase_smartmips = mips_opts.ase_smartmips;
   file_ase_dsp = mips_opts.ase_dsp;
   file_ase_dspr2 = mips_opts.ase_dspr2;
   file_ase_smartmips = mips_opts.ase_smartmips;
   file_ase_dsp = mips_opts.ase_dsp;
   file_ase_dspr2 = mips_opts.ase_dspr2;

+  file_ase_eva = mips_opts.ase_eva;

   file_ase_mt = mips_opts.ase_mt;
   file_ase_virt = mips_opts.ase_virt;
   mips_opts.gp32 = file_mips_gp32;
   file_ase_mt = mips_opts.ase_mt;
   file_ase_virt = mips_opts.ase_virt;
   mips_opts.gp32 = file_mips_gp32;


@@ -16510,6 +16699,15 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
       mips_opts.ase_dspr2 = 0;
       mips_opts.ase_dsp = 0;
     }
       mips_opts.ase_dspr2 = 0;
       mips_opts.ase_dsp = 0;
     }

+  else if (strcmp (name, "eva") == 0)
+    {
+      if (!ISA_SUPPORTS_EVA_ASE)
+       as_warn (_("%s ISA does not support EVA ASE"),
+                mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.ase_eva = 1;
+    }
+  else if (strcmp (name, "noeva") == 0)
+    mips_opts.ase_eva = 0;

   else if (strcmp (name, "mt") == 0)
     {
       if (!ISA_SUPPORTS_MT_ASE)
   else if (strcmp (name, "mt") == 0)
     {
       if (!ISA_SUPPORTS_MT_ASE)

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 93270dc..cd52e9d 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2013-06-17  Catherine Moore  <clm@codesourcery.com>
+           Maciej W. Rozycki  <macro@codesourcery.com>
+           Chao-Ying Fu  <fu@mips.com>
+
+       * gas/mips/mips.exp: Run new tests.
+       * gas/mips/eva.d: New.
+       * gas/mips/eva.s: New.
+       * gas/mips/micromips@eva.d: New.
+

 2013-06-15  Richard Sandiford  <rdsandiford@googlemail.com>
 
        * gas/mips/loc-swap-3.d: Require -32.
 2013-06-15  Richard Sandiford  <rdsandiford@googlemail.com>
 
        * gas/mips/loc-swap-3.d: Require -32.

diff --git a/gas/testsuite/gas/mips/eva.d b/gas/testsuite/gas/mips/eva.d
new file mode 100644 (file)
index 0000000..30b62c0
--- /dev/null
+++ b/gas/testsuite/gas/mips/eva.d
@@ -0,0 +1,1442 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS EVA 
+#as: -meva
+
+# Test the EVA instructions
+
+.*: +file format .*mips.*
+
+
+Disassembly of section .text:
+0+0000 <[^>]*> 7c408028        lbue    zero,-256\(v0\)
+0+0004 <[^>]*> 7c038028        lbue    v1,-256\(zero\)
+0+0008 <[^>]*> 7ca47fa8        lbue    a0,255\(a1\)
+0+000c <[^>]*> 7c067fa8        lbue    a2,255\(zero\)
+0+0010 <[^>]*> 2401fe00        li      at,-512
+0+0014 <[^>]*> 00280821        addu    at,at,t0
+0+0018 <[^>]*> 7c277fa8        lbue    a3,255\(at\)
+0+001c <[^>]*> 2401fe00        li      at,-512
+0+0020 <[^>]*> 7c297fa8        lbue    t1,255\(at\)
+0+0024 <[^>]*> 24010200        li      at,512
+0+0028 <[^>]*> 002b0821        addu    at,at,t3
+0+002c <[^>]*> 7c2a8028        lbue    t2,-256\(at\)
+0+0030 <[^>]*> 24010200        li      at,512
+0+0034 <[^>]*> 7c2c8028        lbue    t4,-256\(at\)
+0+0038 <[^>]*> 2401fe00        li      at,-512
+0+003c <[^>]*> 002e0821        addu    at,at,t6
+0+0040 <[^>]*> 7c2d0028        lbue    t5,0\(at\)
+0+0044 <[^>]*> 2401fe00        li      at,-512
+0+0048 <[^>]*> 7c2f0028        lbue    t7,0\(at\)
+0+004c <[^>]*> 24010200        li      at,512
+0+0050 <[^>]*> 00310821        addu    at,at,s1
+0+0054 <[^>]*> 7c30ffa8        lbue    s0,-1\(at\)
+0+0058 <[^>]*> 24010200        li      at,512
+0+005c <[^>]*> 7c32ffa8        lbue    s2,-1\(at\)
+0+0060 <[^>]*> 2401fc00        li      at,-1024
+0+0064 <[^>]*> 00340821        addu    at,at,s4
+0+0068 <[^>]*> 7c330028        lbue    s3,0\(at\)
+0+006c <[^>]*> 2401fc00        li      at,-1024
+0+0070 <[^>]*> 7c350028        lbue    s5,0\(at\)
+0+0074 <[^>]*> 24010400        li      at,1024
+0+0078 <[^>]*> 00370821        addu    at,at,s7
+0+007c <[^>]*> 7c36ffa8        lbue    s6,-1\(at\)
+0+0080 <[^>]*> 24010400        li      at,1024
+0+0084 <[^>]*> 7c38ffa8        lbue    t8,-1\(at\)
+0+0088 <[^>]*> 2401f800        li      at,-2048
+0+008c <[^>]*> 003a0821        addu    at,at,k0
+0+0090 <[^>]*> 7c390028        lbue    t9,0\(at\)
+0+0094 <[^>]*> 2401f800        li      at,-2048
+0+0098 <[^>]*> 7c3b0028        lbue    k1,0\(at\)
+0+009c <[^>]*> 24010800        li      at,2048
+0+00a0 <[^>]*> 003d0821        addu    at,at,sp
+0+00a4 <[^>]*> 7c3cffa8        lbue    gp,-1\(at\)
+0+00a8 <[^>]*> 24010800        li      at,2048
+0+00ac <[^>]*> 7c3effa8        lbue    s8,-1\(at\)
+0+00b0 <[^>]*> 2401f000        li      at,-4096
+0+00b4 <[^>]*> 7c3f0028        lbue    ra,0\(at\)
+0+00b8 <[^>]*> 2401f000        li      at,-4096
+0+00bc <[^>]*> 7c220028        lbue    v0,0\(at\)
+0+00c0 <[^>]*> 24011000        li      at,4096
+0+00c4 <[^>]*> 00240821        addu    at,at,a0
+0+00c8 <[^>]*> 7c23ffa8        lbue    v1,-1\(at\)
+0+00cc <[^>]*> 24011000        li      at,4096
+0+00d0 <[^>]*> 7c25ffa8        lbue    a1,-1\(at\)
+0+00d4 <[^>]*> 24018000        li      at,-32768
+0+00d8 <[^>]*> 00270821        addu    at,at,a3
+0+00dc <[^>]*> 7c260028        lbue    a2,0\(at\)
+0+00e0 <[^>]*> 24018000        li      at,-32768
+0+00e4 <[^>]*> 7c280028        lbue    t0,0\(at\)
+0+00e8 <[^>]*> 34018000        li      at,0x8000
+0+00ec <[^>]*> 002a0821        addu    at,at,t2
+0+00f0 <[^>]*> 7c29ffa8        lbue    t1,-1\(at\)
+0+00f4 <[^>]*> 34018000        li      at,0x8000
+0+00f8 <[^>]*> 7c2bffa8        lbue    t3,-1\(at\)
+0+00fc <[^>]*> 24018000        li      at,-32768
+0+0100 <[^>]*> 002d0821        addu    at,at,t5
+0+0104 <[^>]*> 7c2cffa8        lbue    t4,-1\(at\)
+0+0108 <[^>]*> 24018000        li      at,-32768
+0+010c <[^>]*> 7c2effa8        lbue    t6,-1\(at\)
+0+0110 <[^>]*> 34018000        li      at,0x8000
+0+0114 <[^>]*> 00300821        addu    at,at,s0
+0+0118 <[^>]*> 7c2f0028        lbue    t7,0\(at\)
+0+011c <[^>]*> 34018000        li      at,0x8000
+0+0120 <[^>]*> 7c310028        lbue    s1,0\(at\)
+0+0124 <[^>]*> 3c018000        lui     at,0x8000
+0+0128 <[^>]*> 00330821        addu    at,at,s3
+0+012c <[^>]*> 7c320028        lbue    s2,0\(at\)
+0+0130 <[^>]*> 3c018000        lui     at,0x8000
+0+0134 <[^>]*> 7c340028        lbue    s4,0\(at\)
+0+0138 <[^>]*> 3c018000        lui     at,0x8000
+0+013c <[^>]*> 00360821        addu    at,at,s6
+0+0140 <[^>]*> 7c35ffa8        lbue    s5,-1\(at\)
+0+0144 <[^>]*> 3c018000        lui     at,0x8000
+0+0148 <[^>]*> 7c37ffa8        lbue    s7,-1\(at\)
+0+014c <[^>]*> 7f380028        lbue    t8,0\(t9\)
+0+0150 <[^>]*> 3c010000        lui     at,0x0
+                       150: R_MIPS_HI16        MYDATA
+0+0154 <[^>]*> 24210000        addiu   at,at,0
+                       154: R_MIPS_LO16        MYDATA
+0+0158 <[^>]*> 7c3a0028        lbue    k0,0\(at\)
+0+015c <[^>]*> 7f9b8029        lhue    k1,-256\(gp\)
+0+0160 <[^>]*> 7c1d8029        lhue    sp,-256\(zero\)
+0+0164 <[^>]*> 7ffe7fa9        lhue    s8,255\(ra\)
+0+0168 <[^>]*> 7c007fa9        lhue    zero,255\(zero\)
+0+016c <[^>]*> 2401fe00        li      at,-512
+0+0170 <[^>]*> 00230821        addu    at,at,v1
+0+0174 <[^>]*> 7c227fa9        lhue    v0,255\(at\)
+0+0178 <[^>]*> 2401fe00        li      at,-512
+0+017c <[^>]*> 7c247fa9        lhue    a0,255\(at\)
+0+0180 <[^>]*> 24010200        li      at,512
+0+0184 <[^>]*> 00260821        addu    at,at,a2
+0+0188 <[^>]*> 7c258029        lhue    a1,-256\(at\)
+0+018c <[^>]*> 24010200        li      at,512
+0+0190 <[^>]*> 7c278029        lhue    a3,-256\(at\)
+0+0194 <[^>]*> 2401fe00        li      at,-512
+0+0198 <[^>]*> 00290821        addu    at,at,t1
+0+019c <[^>]*> 7c280029        lhue    t0,0\(at\)
+0+01a0 <[^>]*> 2401fe00        li      at,-512
+0+01a4 <[^>]*> 7c2a0029        lhue    t2,0\(at\)
+0+01a8 <[^>]*> 24010200        li      at,512
+0+01ac <[^>]*> 002c0821        addu    at,at,t4
+0+01b0 <[^>]*> 7c2bffa9        lhue    t3,-1\(at\)
+0+01b4 <[^>]*> 24010200        li      at,512
+0+01b8 <[^>]*> 7c2dffa9        lhue    t5,-1\(at\)
+0+01bc <[^>]*> 2401fc00        li      at,-1024
+0+01c0 <[^>]*> 002f0821        addu    at,at,t7
+0+01c4 <[^>]*> 7c2e0029        lhue    t6,0\(at\)
+0+01c8 <[^>]*> 2401fc00        li      at,-1024
+0+01cc <[^>]*> 7c300029        lhue    s0,0\(at\)
+0+01d0 <[^>]*> 24010400        li      at,1024
+0+01d4 <[^>]*> 00320821        addu    at,at,s2
+0+01d8 <[^>]*> 7c31ffa9        lhue    s1,-1\(at\)
+0+01dc <[^>]*> 24010400        li      at,1024
+0+01e0 <[^>]*> 7c33ffa9        lhue    s3,-1\(at\)
+0+01e4 <[^>]*> 2401f800        li      at,-2048
+0+01e8 <[^>]*> 00350821        addu    at,at,s5
+0+01ec <[^>]*> 7c340029        lhue    s4,0\(at\)
+0+01f0 <[^>]*> 2401f800        li      at,-2048
+0+01f4 <[^>]*> 7c360029        lhue    s6,0\(at\)
+0+01f8 <[^>]*> 24010800        li      at,2048
+0+01fc <[^>]*> 00380821        addu    at,at,t8
+0+0200 <[^>]*> 7c37ffa9        lhue    s7,-1\(at\)
+0+0204 <[^>]*> 24010800        li      at,2048
+0+0208 <[^>]*> 7c39ffa9        lhue    t9,-1\(at\)
+0+020c <[^>]*> 2401f000        li      at,-4096
+0+0210 <[^>]*> 003b0821        addu    at,at,k1
+0+0214 <[^>]*> 7c3a0029        lhue    k0,0\(at\)
+0+0218 <[^>]*> 2401f000        li      at,-4096
+0+021c <[^>]*> 7c3c0029        lhue    gp,0\(at\)
+0+0220 <[^>]*> 24011000        li      at,4096
+0+0224 <[^>]*> 003e0821        addu    at,at,s8
+0+0228 <[^>]*> 7c3dffa9        lhue    sp,-1\(at\)
+0+022c <[^>]*> 24011000        li      at,4096
+0+0230 <[^>]*> 7c3fffa9        lhue    ra,-1\(at\)
+0+0234 <[^>]*> 24018000        li      at,-32768
+0+0238 <[^>]*> 00220821        addu    at,at,v0
+0+023c <[^>]*> 7c200029        lhue    zero,0\(at\)
+0+0240 <[^>]*> 24018000        li      at,-32768
+0+0244 <[^>]*> 7c230029        lhue    v1,0\(at\)
+0+0248 <[^>]*> 34018000        li      at,0x8000
+0+024c <[^>]*> 00250821        addu    at,at,a1
+0+0250 <[^>]*> 7c24ffa9        lhue    a0,-1\(at\)
+0+0254 <[^>]*> 34018000        li      at,0x8000
+0+0258 <[^>]*> 7c26ffa9        lhue    a2,-1\(at\)
+0+025c <[^>]*> 24018000        li      at,-32768
+0+0260 <[^>]*> 00280821        addu    at,at,t0
+0+0264 <[^>]*> 7c27ffa9        lhue    a3,-1\(at\)
+0+0268 <[^>]*> 24018000        li      at,-32768
+0+026c <[^>]*> 7c29ffa9        lhue    t1,-1\(at\)
+0+0270 <[^>]*> 34018000        li      at,0x8000
+0+0274 <[^>]*> 002b0821        addu    at,at,t3
+0+0278 <[^>]*> 7c2a0029        lhue    t2,0\(at\)
+0+027c <[^>]*> 34018000        li      at,0x8000
+0+0280 <[^>]*> 7c2c0029        lhue    t4,0\(at\)
+0+0284 <[^>]*> 3c018000        lui     at,0x8000
+0+0288 <[^>]*> 002e0821        addu    at,at,t6
+0+028c <[^>]*> 7c2d0029        lhue    t5,0\(at\)
+0+0290 <[^>]*> 3c018000        lui     at,0x8000
+0+0294 <[^>]*> 7c2f0029        lhue    t7,0\(at\)
+0+0298 <[^>]*> 3c018000        lui     at,0x8000
+0+029c <[^>]*> 00310821        addu    at,at,s1
+0+02a0 <[^>]*> 7c30ffa9        lhue    s0,-1\(at\)
+0+02a4 <[^>]*> 3c018000        lui     at,0x8000
+0+02a8 <[^>]*> 7c32ffa9        lhue    s2,-1\(at\)
+0+02ac <[^>]*> 7e930029        lhue    s3,0\(s4\)
+0+02b0 <[^>]*> 3c010000        lui     at,0x0
+                       2b0: R_MIPS_HI16        MYDATA
+0+02b4 <[^>]*> 24210000        addiu   at,at,0
+                       2b4: R_MIPS_LO16        MYDATA
+0+02b8 <[^>]*> 7c350029        lhue    s5,0\(at\)
+0+02bc <[^>]*> 7ef6802c        lbe     s6,-256\(s7\)
+0+02c0 <[^>]*> 7c18802c        lbe     t8,-256\(zero\)
+0+02c4 <[^>]*> 7f597fac        lbe     t9,255\(k0\)
+0+02c8 <[^>]*> 7c1b7fac        lbe     k1,255\(zero\)
+0+02cc <[^>]*> 2401fe00        li      at,-512
+0+02d0 <[^>]*> 003d0821        addu    at,at,sp
+0+02d4 <[^>]*> 7c3c7fac        lbe     gp,255\(at\)
+0+02d8 <[^>]*> 2401fe00        li      at,-512
+0+02dc <[^>]*> 7c3e7fac        lbe     s8,255\(at\)
+0+02e0 <[^>]*> 24010200        li      at,512
+0+02e4 <[^>]*> 7c3f802c        lbe     ra,-256\(at\)
+0+02e8 <[^>]*> 24010200        li      at,512
+0+02ec <[^>]*> 7c22802c        lbe     v0,-256\(at\)
+0+02f0 <[^>]*> 2401fe00        li      at,-512
+0+02f4 <[^>]*> 00240821        addu    at,at,a0
+0+02f8 <[^>]*> 7c23002c        lbe     v1,0\(at\)
+0+02fc <[^>]*> 2401fe00        li      at,-512
+0+0300 <[^>]*> 7c25002c        lbe     a1,0\(at\)
+0+0304 <[^>]*> 24010200        li      at,512
+0+0308 <[^>]*> 00270821        addu    at,at,a3
+0+030c <[^>]*> 7c26ffac        lbe     a2,-1\(at\)
+0+0310 <[^>]*> 24010200        li      at,512
+0+0314 <[^>]*> 7c28ffac        lbe     t0,-1\(at\)
+0+0318 <[^>]*> 2401fc00        li      at,-1024
+0+031c <[^>]*> 002a0821        addu    at,at,t2
+0+0320 <[^>]*> 7c29002c        lbe     t1,0\(at\)
+0+0324 <[^>]*> 2401fc00        li      at,-1024
+0+0328 <[^>]*> 7c2b002c        lbe     t3,0\(at\)
+0+032c <[^>]*> 24010400        li      at,1024
+0+0330 <[^>]*> 002d0821        addu    at,at,t5
+0+0334 <[^>]*> 7c2cffac        lbe     t4,-1\(at\)
+0+0338 <[^>]*> 24010400        li      at,1024
+0+033c <[^>]*> 7c2effac        lbe     t6,-1\(at\)
+0+0340 <[^>]*> 2401f800        li      at,-2048
+0+0344 <[^>]*> 00300821        addu    at,at,s0
+0+0348 <[^>]*> 7c2f002c        lbe     t7,0\(at\)
+0+034c <[^>]*> 2401f800        li      at,-2048
+0+0350 <[^>]*> 7c31002c        lbe     s1,0\(at\)
+0+0354 <[^>]*> 24010800        li      at,2048
+0+0358 <[^>]*> 00330821        addu    at,at,s3
+0+035c <[^>]*> 7c32ffac        lbe     s2,-1\(at\)
+0+0360 <[^>]*> 24010800        li      at,2048
+0+0364 <[^>]*> 7c34ffac        lbe     s4,-1\(at\)
+0+0368 <[^>]*> 2401f000        li      at,-4096
+0+036c <[^>]*> 00360821        addu    at,at,s6
+0+0370 <[^>]*> 7c35002c        lbe     s5,0\(at\)
+0+0374 <[^>]*> 2401f000        li      at,-4096
+0+0378 <[^>]*> 7c37002c        lbe     s7,0\(at\)
+0+037c <[^>]*> 24011000        li      at,4096
+0+0380 <[^>]*> 00390821        addu    at,at,t9
+0+0384 <[^>]*> 7c38ffac        lbe     t8,-1\(at\)
+0+0388 <[^>]*> 24011000        li      at,4096
+0+038c <[^>]*> 7c3affac        lbe     k0,-1\(at\)
+0+0390 <[^>]*> 24018000        li      at,-32768
+0+0394 <[^>]*> 003c0821        addu    at,at,gp
+0+0398 <[^>]*> 7c3b002c        lbe     k1,0\(at\)
+0+039c <[^>]*> 24018000        li      at,-32768
+0+03a0 <[^>]*> 7c3d002c        lbe     sp,0\(at\)
+0+03a4 <[^>]*> 34018000        li      at,0x8000
+0+03a8 <[^>]*> 003f0821        addu    at,at,ra
+0+03ac <[^>]*> 7c3effac        lbe     s8,-1\(at\)
+0+03b0 <[^>]*> 34018000        li      at,0x8000
+0+03b4 <[^>]*> 7c20ffac        lbe     zero,-1\(at\)
+0+03b8 <[^>]*> 24018000        li      at,-32768
+0+03bc <[^>]*> 00230821        addu    at,at,v1
+0+03c0 <[^>]*> 7c22ffac        lbe     v0,-1\(at\)
+0+03c4 <[^>]*> 24018000        li      at,-32768
+0+03c8 <[^>]*> 7c24ffac        lbe     a0,-1\(at\)
+0+03cc <[^>]*> 34018000        li      at,0x8000
+0+03d0 <[^>]*> 00260821        addu    at,at,a2
+0+03d4 <[^>]*> 7c25002c        lbe     a1,0\(at\)
+0+03d8 <[^>]*> 34018000        li      at,0x8000
+0+03dc <[^>]*> 7c27002c        lbe     a3,0\(at\)
+0+03e0 <[^>]*> 3c018000        lui     at,0x8000
+0+03e4 <[^>]*> 00290821        addu    at,at,t1
+0+03e8 <[^>]*> 7c28002c        lbe     t0,0\(at\)
+0+03ec <[^>]*> 3c018000        lui     at,0x8000
+0+03f0 <[^>]*> 7c2a002c        lbe     t2,0\(at\)
+0+03f4 <[^>]*> 3c018000        lui     at,0x8000
+0+03f8 <[^>]*> 002c0821        addu    at,at,t4
+0+03fc <[^>]*> 7c2bffac        lbe     t3,-1\(at\)
+0+0400 <[^>]*> 3c018000        lui     at,0x8000
+0+0404 <[^>]*> 7c2dffac        lbe     t5,-1\(at\)
+0+0408 <[^>]*> 7dee002c        lbe     t6,0\(t7\)
+0+040c <[^>]*> 3c010000        lui     at,0x0
+                       40c: R_MIPS_HI16        MYDATA
+0+0410 <[^>]*> 24210000        addiu   at,at,0
+                       410: R_MIPS_LO16        MYDATA
+0+0414 <[^>]*> 7c30002c        lbe     s0,0\(at\)
+0+0418 <[^>]*> 7e51802d        lhe     s1,-256\(s2\)
+0+041c <[^>]*> 7c13802d        lhe     s3,-256\(zero\)
+0+0420 <[^>]*> 7eb47fad        lhe     s4,255\(s5\)
+0+0424 <[^>]*> 7c167fad        lhe     s6,255\(zero\)
+0+0428 <[^>]*> 2401fe00        li      at,-512
+0+042c <[^>]*> 00380821        addu    at,at,t8
+0+0430 <[^>]*> 7c377fad        lhe     s7,255\(at\)
+0+0434 <[^>]*> 2401fe00        li      at,-512
+0+0438 <[^>]*> 7c397fad        lhe     t9,255\(at\)
+0+043c <[^>]*> 24010200        li      at,512
+0+0440 <[^>]*> 003b0821        addu    at,at,k1
+0+0444 <[^>]*> 7c3a802d        lhe     k0,-256\(at\)
+0+0448 <[^>]*> 24010200        li      at,512
+0+044c <[^>]*> 7c3c802d        lhe     gp,-256\(at\)
+0+0450 <[^>]*> 2401fe00        li      at,-512
+0+0454 <[^>]*> 003e0821        addu    at,at,s8
+0+0458 <[^>]*> 7c3d002d        lhe     sp,0\(at\)
+0+045c <[^>]*> 2401fe00        li      at,-512
+0+0460 <[^>]*> 7c3f002d        lhe     ra,0\(at\)
+0+0464 <[^>]*> 24010200        li      at,512
+0+0468 <[^>]*> 00220821        addu    at,at,v0
+0+046c <[^>]*> 7c20ffad        lhe     zero,-1\(at\)
+0+0470 <[^>]*> 24010200        li      at,512
+0+0474 <[^>]*> 7c23ffad        lhe     v1,-1\(at\)
+0+0478 <[^>]*> 2401fc00        li      at,-1024
+0+047c <[^>]*> 00250821        addu    at,at,a1
+0+0480 <[^>]*> 7c24002d        lhe     a0,0\(at\)
+0+0484 <[^>]*> 2401fc00        li      at,-1024
+0+0488 <[^>]*> 7c26002d        lhe     a2,0\(at\)
+0+048c <[^>]*> 24010400        li      at,1024
+0+0490 <[^>]*> 00280821        addu    at,at,t0
+0+0494 <[^>]*> 7c27ffad        lhe     a3,-1\(at\)
+0+0498 <[^>]*> 24010400        li      at,1024
+0+049c <[^>]*> 7c29ffad        lhe     t1,-1\(at\)
+0+04a0 <[^>]*> 2401f800        li      at,-2048
+0+04a4 <[^>]*> 002b0821        addu    at,at,t3
+0+04a8 <[^>]*> 7c2a002d        lhe     t2,0\(at\)
+0+04ac <[^>]*> 2401f800        li      at,-2048
+0+04b0 <[^>]*> 7c2c002d        lhe     t4,0\(at\)
+0+04b4 <[^>]*> 24010800        li      at,2048
+0+04b8 <[^>]*> 002e0821        addu    at,at,t6
+0+04bc <[^>]*> 7c2dffad        lhe     t5,-1\(at\)
+0+04c0 <[^>]*> 24010800        li      at,2048
+0+04c4 <[^>]*> 7c2fffad        lhe     t7,-1\(at\)
+0+04c8 <[^>]*> 2401f000        li      at,-4096
+0+04cc <[^>]*> 00310821        addu    at,at,s1
+0+04d0 <[^>]*> 7c30002d        lhe     s0,0\(at\)
+0+04d4 <[^>]*> 2401f000        li      at,-4096
+0+04d8 <[^>]*> 7c32002d        lhe     s2,0\(at\)
+0+04dc <[^>]*> 24011000        li      at,4096
+0+04e0 <[^>]*> 00340821        addu    at,at,s4
+0+04e4 <[^>]*> 7c33ffad        lhe     s3,-1\(at\)
+0+04e8 <[^>]*> 24011000        li      at,4096
+0+04ec <[^>]*> 7c35ffad        lhe     s5,-1\(at\)
+0+04f0 <[^>]*> 24018000        li      at,-32768
+0+04f4 <[^>]*> 00370821        addu    at,at,s7
+0+04f8 <[^>]*> 7c36002d        lhe     s6,0\(at\)
+0+04fc <[^>]*> 24018000        li      at,-32768
+0+0500 <[^>]*> 7c38002d        lhe     t8,0\(at\)
+0+0504 <[^>]*> 34018000        li      at,0x8000
+0+0508 <[^>]*> 003a0821        addu    at,at,k0
+0+050c <[^>]*> 7c39ffad        lhe     t9,-1\(at\)
+0+0510 <[^>]*> 34018000        li      at,0x8000
+0+0514 <[^>]*> 7c3bffad        lhe     k1,-1\(at\)
+0+0518 <[^>]*> 24018000        li      at,-32768
+0+051c <[^>]*> 003d0821        addu    at,at,sp
+0+0520 <[^>]*> 7c3cffad        lhe     gp,-1\(at\)
+0+0524 <[^>]*> 24018000        li      at,-32768
+0+0528 <[^>]*> 7c3effad        lhe     s8,-1\(at\)
+0+052c <[^>]*> 34018000        li      at,0x8000
+0+0530 <[^>]*> 7c3f002d        lhe     ra,0\(at\)
+0+0534 <[^>]*> 34018000        li      at,0x8000
+0+0538 <[^>]*> 7c22002d        lhe     v0,0\(at\)
+0+053c <[^>]*> 3c018000        lui     at,0x8000
+0+0540 <[^>]*> 00240821        addu    at,at,a0
+0+0544 <[^>]*> 7c23002d        lhe     v1,0\(at\)
+0+0548 <[^>]*> 3c018000        lui     at,0x8000
+0+054c <[^>]*> 7c25002d        lhe     a1,0\(at\)
+0+0550 <[^>]*> 3c018000        lui     at,0x8000
+0+0554 <[^>]*> 00270821        addu    at,at,a3
+0+0558 <[^>]*> 7c26ffad        lhe     a2,-1\(at\)
+0+055c <[^>]*> 3c018000        lui     at,0x8000
+0+0560 <[^>]*> 7c28ffad        lhe     t0,-1\(at\)
+0+0564 <[^>]*> 7d49002d        lhe     t1,0\(t2\)
+0+0568 <[^>]*> 3c010000        lui     at,0x0
+                       568: R_MIPS_HI16        MYDATA
+0+056c <[^>]*> 24210000        addiu   at,at,0
+                       56c: R_MIPS_LO16        MYDATA
+0+0570 <[^>]*> 7c2b002d        lhe     t3,0\(at\)
+0+0574 <[^>]*> 7dac802e        lle     t4,-256\(t5\)
+0+0578 <[^>]*> 7c0e802e        lle     t6,-256\(zero\)
+0+057c <[^>]*> 7e0f7fae        lle     t7,255\(s0\)
+0+0580 <[^>]*> 7c117fae        lle     s1,255\(zero\)
+0+0584 <[^>]*> 2401fe00        li      at,-512
+0+0588 <[^>]*> 00330821        addu    at,at,s3
+0+058c <[^>]*> 7c327fae        lle     s2,255\(at\)
+0+0590 <[^>]*> 2401fe00        li      at,-512
+0+0594 <[^>]*> 7c347fae        lle     s4,255\(at\)
+0+0598 <[^>]*> 24010200        li      at,512
+0+059c <[^>]*> 00360821        addu    at,at,s6
+0+05a0 <[^>]*> 7c35802e        lle     s5,-256\(at\)
+0+05a4 <[^>]*> 24010200        li      at,512
+0+05a8 <[^>]*> 7c37802e        lle     s7,-256\(at\)
+0+05ac <[^>]*> 2401fe00        li      at,-512
+0+05b0 <[^>]*> 00390821        addu    at,at,t9
+0+05b4 <[^>]*> 7c38002e        lle     t8,0\(at\)
+0+05b8 <[^>]*> 2401fe00        li      at,-512
+0+05bc <[^>]*> 7c3a002e        lle     k0,0\(at\)
+0+05c0 <[^>]*> 24010200        li      at,512
+0+05c4 <[^>]*> 003c0821        addu    at,at,gp
+0+05c8 <[^>]*> 7c3bffae        lle     k1,-1\(at\)
+0+05cc <[^>]*> 24010200        li      at,512
+0+05d0 <[^>]*> 7c3dffae        lle     sp,-1\(at\)
+0+05d4 <[^>]*> 2401fc00        li      at,-1024
+0+05d8 <[^>]*> 003f0821        addu    at,at,ra
+0+05dc <[^>]*> 7c3e002e        lle     s8,0\(at\)
+0+05e0 <[^>]*> 2401fc00        li      at,-1024
+0+05e4 <[^>]*> 7c20002e        lle     zero,0\(at\)
+0+05e8 <[^>]*> 24010400        li      at,1024
+0+05ec <[^>]*> 00230821        addu    at,at,v1
+0+05f0 <[^>]*> 7c22ffae        lle     v0,-1\(at\)
+0+05f4 <[^>]*> 24010400        li      at,1024
+0+05f8 <[^>]*> 7c24ffae        lle     a0,-1\(at\)
+0+05fc <[^>]*> 2401f800        li      at,-2048
+0+0600 <[^>]*> 00260821        addu    at,at,a2
+0+0604 <[^>]*> 7c25002e        lle     a1,0\(at\)
+0+0608 <[^>]*> 2401f800        li      at,-2048
+0+060c <[^>]*> 7c27002e        lle     a3,0\(at\)
+0+0610 <[^>]*> 24010800        li      at,2048
+0+0614 <[^>]*> 00290821        addu    at,at,t1
+0+0618 <[^>]*> 7c28ffae        lle     t0,-1\(at\)
+0+061c <[^>]*> 24010800        li      at,2048
+0+0620 <[^>]*> 7c2affae        lle     t2,-1\(at\)
+0+0624 <[^>]*> 2401f000        li      at,-4096
+0+0628 <[^>]*> 002c0821        addu    at,at,t4
+0+062c <[^>]*> 7c2b002e        lle     t3,0\(at\)
+0+0630 <[^>]*> 2401f000        li      at,-4096
+0+0634 <[^>]*> 7c2d002e        lle     t5,0\(at\)
+0+0638 <[^>]*> 24011000        li      at,4096
+0+063c <[^>]*> 002f0821        addu    at,at,t7
+0+0640 <[^>]*> 7c2effae        lle     t6,-1\(at\)
+0+0644 <[^>]*> 24011000        li      at,4096
+0+0648 <[^>]*> 7c30ffae        lle     s0,-1\(at\)
+0+064c <[^>]*> 24018000        li      at,-32768
+0+0650 <[^>]*> 00320821        addu    at,at,s2
+0+0654 <[^>]*> 7c31002e        lle     s1,0\(at\)
+0+0658 <[^>]*> 24018000        li      at,-32768
+0+065c <[^>]*> 7c33002e        lle     s3,0\(at\)
+0+0660 <[^>]*> 34018000        li      at,0x8000
+0+0664 <[^>]*> 00350821        addu    at,at,s5
+0+0668 <[^>]*> 7c34ffae        lle     s4,-1\(at\)
+0+066c <[^>]*> 34018000        li      at,0x8000
+0+0670 <[^>]*> 7c36ffae        lle     s6,-1\(at\)
+0+0674 <[^>]*> 24018000        li      at,-32768
+0+0678 <[^>]*> 00380821        addu    at,at,t8
+0+067c <[^>]*> 7c37ffae        lle     s7,-1\(at\)
+0+0680 <[^>]*> 24018000        li      at,-32768
+0+0684 <[^>]*> 7c39ffae        lle     t9,-1\(at\)
+0+0688 <[^>]*> 34018000        li      at,0x8000
+0+068c <[^>]*> 003b0821        addu    at,at,k1
+0+0690 <[^>]*> 7c3a002e        lle     k0,0\(at\)
+0+0694 <[^>]*> 34018000        li      at,0x8000
+0+0698 <[^>]*> 7c3c002e        lle     gp,0\(at\)
+0+069c <[^>]*> 3c018000        lui     at,0x8000
+0+06a0 <[^>]*> 003e0821        addu    at,at,s8
+0+06a4 <[^>]*> 7c3d002e        lle     sp,0\(at\)
+0+06a8 <[^>]*> 3c018000        lui     at,0x8000
+0+06ac <[^>]*> 7c3f002e        lle     ra,0\(at\)
+0+06b0 <[^>]*> 3c018000        lui     at,0x8000
+0+06b4 <[^>]*> 00220821        addu    at,at,v0
+0+06b8 <[^>]*> 7c20ffae        lle     zero,-1\(at\)
+0+06bc <[^>]*> 3c018000        lui     at,0x8000
+0+06c0 <[^>]*> 7c23ffae        lle     v1,-1\(at\)
+0+06c4 <[^>]*> 7ca4002e        lle     a0,0\(a1\)
+0+06c8 <[^>]*> 3c010000        lui     at,0x0
+                       6c8: R_MIPS_HI16        MYDATA
+0+06cc <[^>]*> 24210000        addiu   at,at,0
+                       6cc: R_MIPS_LO16        MYDATA
+0+06d0 <[^>]*> 7c26002e        lle     a2,0\(at\)
+0+06d4 <[^>]*> 7d07802f        lwe     a3,-256\(t0\)
+0+06d8 <[^>]*> 7c09802f        lwe     t1,-256\(zero\)
+0+06dc <[^>]*> 7d6a7faf        lwe     t2,255\(t3\)
+0+06e0 <[^>]*> 7c0c7faf        lwe     t4,255\(zero\)
+0+06e4 <[^>]*> 2401fe00        li      at,-512
+0+06e8 <[^>]*> 002e0821        addu    at,at,t6
+0+06ec <[^>]*> 7c2d7faf        lwe     t5,255\(at\)
+0+06f0 <[^>]*> 2401fe00        li      at,-512
+0+06f4 <[^>]*> 7c2f7faf        lwe     t7,255\(at\)
+0+06f8 <[^>]*> 24010200        li      at,512
+0+06fc <[^>]*> 00310821        addu    at,at,s1
+0+0700 <[^>]*> 7c30802f        lwe     s0,-256\(at\)
+0+0704 <[^>]*> 24010200        li      at,512
+0+0708 <[^>]*> 7c32802f        lwe     s2,-256\(at\)
+0+070c <[^>]*> 2401fe00        li      at,-512
+0+0710 <[^>]*> 00340821        addu    at,at,s4
+0+0714 <[^>]*> 7c33002f        lwe     s3,0\(at\)
+0+0718 <[^>]*> 2401fe00        li      at,-512
+0+071c <[^>]*> 7c35002f        lwe     s5,0\(at\)
+0+0720 <[^>]*> 24010200        li      at,512
+0+0724 <[^>]*> 00370821        addu    at,at,s7
+0+0728 <[^>]*> 7c36ffaf        lwe     s6,-1\(at\)
+0+072c <[^>]*> 24010200        li      at,512
+0+0730 <[^>]*> 7c38ffaf        lwe     t8,-1\(at\)
+0+0734 <[^>]*> 2401fc00        li      at,-1024
+0+0738 <[^>]*> 003a0821        addu    at,at,k0
+0+073c <[^>]*> 7c39002f        lwe     t9,0\(at\)
+0+0740 <[^>]*> 2401fc00        li      at,-1024
+0+0744 <[^>]*> 7c3b002f        lwe     k1,0\(at\)
+0+0748 <[^>]*> 24010400        li      at,1024
+0+074c <[^>]*> 003d0821        addu    at,at,sp
+0+0750 <[^>]*> 7c3cffaf        lwe     gp,-1\(at\)
+0+0754 <[^>]*> 24010400        li      at,1024
+0+0758 <[^>]*> 7c3effaf        lwe     s8,-1\(at\)
+0+075c <[^>]*> 2401f800        li      at,-2048
+0+0760 <[^>]*> 7c3f002f        lwe     ra,0\(at\)
+0+0764 <[^>]*> 2401f800        li      at,-2048
+0+0768 <[^>]*> 7c22002f        lwe     v0,0\(at\)
+0+076c <[^>]*> 24010800        li      at,2048
+0+0770 <[^>]*> 00240821        addu    at,at,a0
+0+0774 <[^>]*> 7c23ffaf        lwe     v1,-1\(at\)
+0+0778 <[^>]*> 24010800        li      at,2048
+0+077c <[^>]*> 7c25ffaf        lwe     a1,-1\(at\)
+0+0780 <[^>]*> 2401f000        li      at,-4096
+0+0784 <[^>]*> 00270821        addu    at,at,a3
+0+0788 <[^>]*> 7c26002f        lwe     a2,0\(at\)
+0+078c <[^>]*> 2401f000        li      at,-4096
+0+0790 <[^>]*> 7c28002f        lwe     t0,0\(at\)
+0+0794 <[^>]*> 24011000        li      at,4096
+0+0798 <[^>]*> 002a0821        addu    at,at,t2
+0+079c <[^>]*> 7c29ffaf        lwe     t1,-1\(at\)
+0+07a0 <[^>]*> 24011000        li      at,4096
+0+07a4 <[^>]*> 7c2bffaf        lwe     t3,-1\(at\)
+0+07a8 <[^>]*> 24018000        li      at,-32768
+0+07ac <[^>]*> 002d0821        addu    at,at,t5
+0+07b0 <[^>]*> 7c2c002f        lwe     t4,0\(at\)
+0+07b4 <[^>]*> 24018000        li      at,-32768
+0+07b8 <[^>]*> 7c2e002f        lwe     t6,0\(at\)
+0+07bc <[^>]*> 34018000        li      at,0x8000
+0+07c0 <[^>]*> 00300821        addu    at,at,s0
+0+07c4 <[^>]*> 7c2fffaf        lwe     t7,-1\(at\)
+0+07c8 <[^>]*> 34018000        li      at,0x8000
+0+07cc <[^>]*> 7c31ffaf        lwe     s1,-1\(at\)
+0+07d0 <[^>]*> 24018000        li      at,-32768
+0+07d4 <[^>]*> 00330821        addu    at,at,s3
+0+07d8 <[^>]*> 7c32ffaf        lwe     s2,-1\(at\)
+0+07dc <[^>]*> 24018000        li      at,-32768
+0+07e0 <[^>]*> 7c34ffaf        lwe     s4,-1\(at\)
+0+07e4 <[^>]*> 34018000        li      at,0x8000
+0+07e8 <[^>]*> 00360821        addu    at,at,s6
+0+07ec <[^>]*> 7c35002f        lwe     s5,0\(at\)
+0+07f0 <[^>]*> 34018000        li      at,0x8000
+0+07f4 <[^>]*> 7c37002f        lwe     s7,0\(at\)
+0+07f8 <[^>]*> 3c018000        lui     at,0x8000
+0+07fc <[^>]*> 00390821        addu    at,at,t9
+0+0800 <[^>]*> 7c38002f        lwe     t8,0\(at\)
+0+0804 <[^>]*> 3c018000        lui     at,0x8000
+0+0808 <[^>]*> 7c3a002f        lwe     k0,0\(at\)
+0+080c <[^>]*> 3c018000        lui     at,0x8000
+0+0810 <[^>]*> 003c0821        addu    at,at,gp
+0+0814 <[^>]*> 7c3bffaf        lwe     k1,-1\(at\)
+0+0818 <[^>]*> 3c018000        lui     at,0x8000
+0+081c <[^>]*> 7c3dffaf        lwe     sp,-1\(at\)
+0+0820 <[^>]*> 7ffe002f        lwe     s8,0\(ra\)
+0+0824 <[^>]*> 3c010000        lui     at,0x0
+                       824: R_MIPS_HI16        MYDATA
+0+0828 <[^>]*> 24210000        addiu   at,at,0
+                       828: R_MIPS_LO16        MYDATA
+0+082c <[^>]*> 7c20002f        lwe     zero,0\(at\)
+0+0830 <[^>]*> 7c628019        lwle    v0,-256\(v1\)
+0+0834 <[^>]*> 7c048019        lwle    a0,-256\(zero\)
+0+0838 <[^>]*> 7cc57f99        lwle    a1,255\(a2\)
+0+083c <[^>]*> 7c077f99        lwle    a3,255\(zero\)
+0+0840 <[^>]*> 2401fe00        li      at,-512
+0+0844 <[^>]*> 00290821        addu    at,at,t1
+0+0848 <[^>]*> 7c287f99        lwle    t0,255\(at\)
+0+084c <[^>]*> 2401fe00        li      at,-512
+0+0850 <[^>]*> 7c2a7f99        lwle    t2,255\(at\)
+0+0854 <[^>]*> 24010200        li      at,512
+0+0858 <[^>]*> 002c0821        addu    at,at,t4
+0+085c <[^>]*> 7c2b8019        lwle    t3,-256\(at\)
+0+0860 <[^>]*> 24010200        li      at,512
+0+0864 <[^>]*> 7c2d8019        lwle    t5,-256\(at\)
+0+0868 <[^>]*> 2401fe00        li      at,-512
+0+086c <[^>]*> 002f0821        addu    at,at,t7
+0+0870 <[^>]*> 7c2e0019        lwle    t6,0\(at\)
+0+0874 <[^>]*> 2401fe00        li      at,-512
+0+0878 <[^>]*> 7c300019        lwle    s0,0\(at\)
+0+087c <[^>]*> 24010200        li      at,512
+0+0880 <[^>]*> 00320821        addu    at,at,s2
+0+0884 <[^>]*> 7c31ff99        lwle    s1,-1\(at\)
+0+0888 <[^>]*> 24010200        li      at,512
+0+088c <[^>]*> 7c33ff99        lwle    s3,-1\(at\)
+0+0890 <[^>]*> 2401fc00        li      at,-1024
+0+0894 <[^>]*> 00350821        addu    at,at,s5
+0+0898 <[^>]*> 7c340019        lwle    s4,0\(at\)
+0+089c <[^>]*> 2401fc00        li      at,-1024
+0+08a0 <[^>]*> 7c360019        lwle    s6,0\(at\)
+0+08a4 <[^>]*> 24010400        li      at,1024
+0+08a8 <[^>]*> 00380821        addu    at,at,t8
+0+08ac <[^>]*> 7c37ff99        lwle    s7,-1\(at\)
+0+08b0 <[^>]*> 24010400        li      at,1024
+0+08b4 <[^>]*> 7c39ff99        lwle    t9,-1\(at\)
+0+08b8 <[^>]*> 2401f800        li      at,-2048
+0+08bc <[^>]*> 003b0821        addu    at,at,k1
+0+08c0 <[^>]*> 7c3a0019        lwle    k0,0\(at\)
+0+08c4 <[^>]*> 2401f800        li      at,-2048
+0+08c8 <[^>]*> 7c3c0019        lwle    gp,0\(at\)
+0+08cc <[^>]*> 24010800        li      at,2048
+0+08d0 <[^>]*> 003e0821        addu    at,at,s8
+0+08d4 <[^>]*> 7c3dff99        lwle    sp,-1\(at\)
+0+08d8 <[^>]*> 24010800        li      at,2048
+0+08dc <[^>]*> 7c3fff99        lwle    ra,-1\(at\)
+0+08e0 <[^>]*> 2401f000        li      at,-4096
+0+08e4 <[^>]*> 00220821        addu    at,at,v0
+0+08e8 <[^>]*> 7c200019        lwle    zero,0\(at\)
+0+08ec <[^>]*> 2401f000        li      at,-4096
+0+08f0 <[^>]*> 7c230019        lwle    v1,0\(at\)
+0+08f4 <[^>]*> 24011000        li      at,4096
+0+08f8 <[^>]*> 00250821        addu    at,at,a1
+0+08fc <[^>]*> 7c24ff99        lwle    a0,-1\(at\)
+0+0900 <[^>]*> 24011000        li      at,4096
+0+0904 <[^>]*> 7c26ff99        lwle    a2,-1\(at\)
+0+0908 <[^>]*> 24018000        li      at,-32768
+0+090c <[^>]*> 00280821        addu    at,at,t0
+0+0910 <[^>]*> 7c270019        lwle    a3,0\(at\)
+0+0914 <[^>]*> 24018000        li      at,-32768
+0+0918 <[^>]*> 7c290019        lwle    t1,0\(at\)
+0+091c <[^>]*> 34018000        li      at,0x8000
+0+0920 <[^>]*> 002b0821        addu    at,at,t3
+0+0924 <[^>]*> 7c2aff99        lwle    t2,-1\(at\)
+0+0928 <[^>]*> 34018000        li      at,0x8000
+0+092c <[^>]*> 7c2cff99        lwle    t4,-1\(at\)
+0+0930 <[^>]*> 24018000        li      at,-32768
+0+0934 <[^>]*> 002e0821        addu    at,at,t6
+0+0938 <[^>]*> 7c2dff99        lwle    t5,-1\(at\)
+0+093c <[^>]*> 24018000        li      at,-32768
+0+0940 <[^>]*> 7c2fff99        lwle    t7,-1\(at\)
+0+0944 <[^>]*> 34018000        li      at,0x8000
+0+0948 <[^>]*> 00310821        addu    at,at,s1
+0+094c <[^>]*> 7c300019        lwle    s0,0\(at\)
+0+0950 <[^>]*> 34018000        li      at,0x8000
+0+0954 <[^>]*> 7c320019        lwle    s2,0\(at\)
+0+0958 <[^>]*> 3c018000        lui     at,0x8000
+0+095c <[^>]*> 00340821        addu    at,at,s4
+0+0960 <[^>]*> 7c330019        lwle    s3,0\(at\)
+0+0964 <[^>]*> 3c018000        lui     at,0x8000
+0+0968 <[^>]*> 7c350019        lwle    s5,0\(at\)
+0+096c <[^>]*> 3c018000        lui     at,0x8000
+0+0970 <[^>]*> 00370821        addu    at,at,s7
+0+0974 <[^>]*> 7c36ff99        lwle    s6,-1\(at\)
+0+0978 <[^>]*> 3c018000        lui     at,0x8000
+0+097c <[^>]*> 7c38ff99        lwle    t8,-1\(at\)
+0+0980 <[^>]*> 7f590019        lwle    t9,0\(k0\)
+0+0984 <[^>]*> 3c010000        lui     at,0x0
+                       984: R_MIPS_HI16        MYDATA
+0+0988 <[^>]*> 24210000        addiu   at,at,0
+                       988: R_MIPS_LO16        MYDATA
+0+098c <[^>]*> 7c3b0019        lwle    k1,0\(at\)
+0+0990 <[^>]*> 7fbc801a        lwre    gp,-256\(sp\)
+0+0994 <[^>]*> 7c1e801a        lwre    s8,-256\(zero\)
+0+0998 <[^>]*> 7c1f7f9a        lwre    ra,255\(zero\)
+0+099c <[^>]*> 7c027f9a        lwre    v0,255\(zero\)
+0+09a0 <[^>]*> 2401fe00        li      at,-512
+0+09a4 <[^>]*> 00240821        addu    at,at,a0
+0+09a8 <[^>]*> 7c237f9a        lwre    v1,255\(at\)
+0+09ac <[^>]*> 2401fe00        li      at,-512
+0+09b0 <[^>]*> 7c257f9a        lwre    a1,255\(at\)
+0+09b4 <[^>]*> 24010200        li      at,512
+0+09b8 <[^>]*> 00270821        addu    at,at,a3
+0+09bc <[^>]*> 7c26801a        lwre    a2,-256\(at\)
+0+09c0 <[^>]*> 24010200        li      at,512
+0+09c4 <[^>]*> 7c28801a        lwre    t0,-256\(at\)
+0+09c8 <[^>]*> 2401fe00        li      at,-512
+0+09cc <[^>]*> 002a0821        addu    at,at,t2
+0+09d0 <[^>]*> 7c29001a        lwre    t1,0\(at\)
+0+09d4 <[^>]*> 2401fe00        li      at,-512
+0+09d8 <[^>]*> 7c2b001a        lwre    t3,0\(at\)
+0+09dc <[^>]*> 24010200        li      at,512
+0+09e0 <[^>]*> 002d0821        addu    at,at,t5
+0+09e4 <[^>]*> 7c2cff9a        lwre    t4,-1\(at\)
+0+09e8 <[^>]*> 24010200        li      at,512
+0+09ec <[^>]*> 7c2eff9a        lwre    t6,-1\(at\)
+0+09f0 <[^>]*> 2401fc00        li      at,-1024
+0+09f4 <[^>]*> 00300821        addu    at,at,s0
+0+09f8 <[^>]*> 7c2f001a        lwre    t7,0\(at\)
+0+09fc <[^>]*> 2401fc00        li      at,-1024
+0+0a00 <[^>]*> 7c31001a        lwre    s1,0\(at\)
+0+0a04 <[^>]*> 24010400        li      at,1024
+0+0a08 <[^>]*> 00330821        addu    at,at,s3
+0+0a0c <[^>]*> 7c32ff9a        lwre    s2,-1\(at\)
+0+0a10 <[^>]*> 24010400        li      at,1024
+0+0a14 <[^>]*> 7c34ff9a        lwre    s4,-1\(at\)
+0+0a18 <[^>]*> 2401f800        li      at,-2048
+0+0a1c <[^>]*> 00360821        addu    at,at,s6
+0+0a20 <[^>]*> 7c35001a        lwre    s5,0\(at\)
+0+0a24 <[^>]*> 2401f800        li      at,-2048
+0+0a28 <[^>]*> 7c37001a        lwre    s7,0\(at\)
+0+0a2c <[^>]*> 24010800        li      at,2048
+0+0a30 <[^>]*> 00390821        addu    at,at,t9
+0+0a34 <[^>]*> 7c38ff9a        lwre    t8,-1\(at\)
+0+0a38 <[^>]*> 24010800        li      at,2048
+0+0a3c <[^>]*> 7c3aff9a        lwre    k0,-1\(at\)
+0+0a40 <[^>]*> 2401f000        li      at,-4096
+0+0a44 <[^>]*> 003c0821        addu    at,at,gp
+0+0a48 <[^>]*> 7c3b001a        lwre    k1,0\(at\)
+0+0a4c <[^>]*> 2401f000        li      at,-4096
+0+0a50 <[^>]*> 7c3d001a        lwre    sp,0\(at\)
+0+0a54 <[^>]*> 24011000        li      at,4096
+0+0a58 <[^>]*> 003f0821        addu    at,at,ra
+0+0a5c <[^>]*> 7c3eff9a        lwre    s8,-1\(at\)
+0+0a60 <[^>]*> 24011000        li      at,4096
+0+0a64 <[^>]*> 7c20ff9a        lwre    zero,-1\(at\)
+0+0a68 <[^>]*> 24018000        li      at,-32768
+0+0a6c <[^>]*> 00230821        addu    at,at,v1
+0+0a70 <[^>]*> 7c22001a        lwre    v0,0\(at\)
+0+0a74 <[^>]*> 24018000        li      at,-32768
+0+0a78 <[^>]*> 7c24001a        lwre    a0,0\(at\)
+0+0a7c <[^>]*> 34018000        li      at,0x8000
+0+0a80 <[^>]*> 00260821        addu    at,at,a2
+0+0a84 <[^>]*> 7c25ff9a        lwre    a1,-1\(at\)
+0+0a88 <[^>]*> 34018000        li      at,0x8000
+0+0a8c <[^>]*> 7c27ff9a        lwre    a3,-1\(at\)
+0+0a90 <[^>]*> 24018000        li      at,-32768
+0+0a94 <[^>]*> 00290821        addu    at,at,t1
+0+0a98 <[^>]*> 7c28ff9a        lwre    t0,-1\(at\)
+0+0a9c <[^>]*> 24018000        li      at,-32768
+0+0aa0 <[^>]*> 7c2aff9a        lwre    t2,-1\(at\)
+0+0aa4 <[^>]*> 34018000        li      at,0x8000
+0+0aa8 <[^>]*> 002c0821        addu    at,at,t4
+0+0aac <[^>]*> 7c2b001a        lwre    t3,0\(at\)
+0+0ab0 <[^>]*> 34018000        li      at,0x8000
+0+0ab4 <[^>]*> 7c2d001a        lwre    t5,0\(at\)
+0+0ab8 <[^>]*> 3c018000        lui     at,0x8000
+0+0abc <[^>]*> 002f0821        addu    at,at,t7
+0+0ac0 <[^>]*> 7c2e001a        lwre    t6,0\(at\)
+0+0ac4 <[^>]*> 3c018000        lui     at,0x8000
+0+0ac8 <[^>]*> 7c30001a        lwre    s0,0\(at\)
+0+0acc <[^>]*> 3c018000        lui     at,0x8000
+0+0ad0 <[^>]*> 00320821        addu    at,at,s2
+0+0ad4 <[^>]*> 7c31ff9a        lwre    s1,-1\(at\)
+0+0ad8 <[^>]*> 3c018000        lui     at,0x8000
+0+0adc <[^>]*> 7c33ff9a        lwre    s3,-1\(at\)
+0+0ae0 <[^>]*> 7eb4001a        lwre    s4,0\(s5\)
+0+0ae4 <[^>]*> 3c010000        lui     at,0x0
+                       ae4: R_MIPS_HI16        MYDATA
+0+0ae8 <[^>]*> 24210000        addiu   at,at,0
+                       ae8: R_MIPS_LO16        MYDATA
+0+0aec <[^>]*> 7c36001a        lwre    s6,0\(at\)
+0+0af0 <[^>]*> 7f17801c        sbe     s7,-256\(t8\)
+0+0af4 <[^>]*> 7c19801c        sbe     t9,-256\(zero\)
+0+0af8 <[^>]*> 7f7a7f9c        sbe     k0,255\(k1\)
+0+0afc <[^>]*> 7c1c7f9c        sbe     gp,255\(zero\)
+0+0b00 <[^>]*> 2401fe00        li      at,-512
+0+0b04 <[^>]*> 003e0821        addu    at,at,s8
+0+0b08 <[^>]*> 7c3d7f9c        sbe     sp,255\(at\)
+0+0b0c <[^>]*> 2401fe00        li      at,-512
+0+0b10 <[^>]*> 7c3f7f9c        sbe     ra,255\(at\)
+0+0b14 <[^>]*> 24010200        li      at,512
+0+0b18 <[^>]*> 00220821        addu    at,at,v0
+0+0b1c <[^>]*> 7c20801c        sbe     zero,-256\(at\)
+0+0b20 <[^>]*> 24010200        li      at,512
+0+0b24 <[^>]*> 7c23801c        sbe     v1,-256\(at\)
+0+0b28 <[^>]*> 2401fe00        li      at,-512
+0+0b2c <[^>]*> 00250821        addu    at,at,a1
+0+0b30 <[^>]*> 7c24001c        sbe     a0,0\(at\)
+0+0b34 <[^>]*> 2401fe00        li      at,-512
+0+0b38 <[^>]*> 7c26001c        sbe     a2,0\(at\)
+0+0b3c <[^>]*> 24010200        li      at,512
+0+0b40 <[^>]*> 00280821        addu    at,at,t0
+0+0b44 <[^>]*> 7c27ff9c        sbe     a3,-1\(at\)
+0+0b48 <[^>]*> 24010200        li      at,512
+0+0b4c <[^>]*> 7c29ff9c        sbe     t1,-1\(at\)
+0+0b50 <[^>]*> 2401fc00        li      at,-1024
+0+0b54 <[^>]*> 002b0821        addu    at,at,t3
+0+0b58 <[^>]*> 7c2a001c        sbe     t2,0\(at\)
+0+0b5c <[^>]*> 2401fc00        li      at,-1024
+0+0b60 <[^>]*> 7c2c001c        sbe     t4,0\(at\)
+0+0b64 <[^>]*> 24010400        li      at,1024
+0+0b68 <[^>]*> 002e0821        addu    at,at,t6
+0+0b6c <[^>]*> 7c2dff9c        sbe     t5,-1\(at\)
+0+0b70 <[^>]*> 24010400        li      at,1024
+0+0b74 <[^>]*> 7c2fff9c        sbe     t7,-1\(at\)
+0+0b78 <[^>]*> 2401f800        li      at,-2048
+0+0b7c <[^>]*> 00310821        addu    at,at,s1
+0+0b80 <[^>]*> 7c30001c        sbe     s0,0\(at\)
+0+0b84 <[^>]*> 2401f800        li      at,-2048
+0+0b88 <[^>]*> 7c32001c        sbe     s2,0\(at\)
+0+0b8c <[^>]*> 24010800        li      at,2048
+0+0b90 <[^>]*> 00340821        addu    at,at,s4
+0+0b94 <[^>]*> 7c33ff9c        sbe     s3,-1\(at\)
+0+0b98 <[^>]*> 24010800        li      at,2048
+0+0b9c <[^>]*> 7c35ff9c        sbe     s5,-1\(at\)
+0+0ba0 <[^>]*> 2401f000        li      at,-4096
+0+0ba4 <[^>]*> 00370821        addu    at,at,s7
+0+0ba8 <[^>]*> 7c36001c        sbe     s6,0\(at\)
+0+0bac <[^>]*> 2401f000        li      at,-4096
+0+0bb0 <[^>]*> 7c38001c        sbe     t8,0\(at\)
+0+0bb4 <[^>]*> 24011000        li      at,4096
+0+0bb8 <[^>]*> 003a0821        addu    at,at,k0
+0+0bbc <[^>]*> 7c39ff9c        sbe     t9,-1\(at\)
+0+0bc0 <[^>]*> 24011000        li      at,4096
+0+0bc4 <[^>]*> 7c3bff9c        sbe     k1,-1\(at\)
+0+0bc8 <[^>]*> 24018000        li      at,-32768
+0+0bcc <[^>]*> 003d0821        addu    at,at,sp
+0+0bd0 <[^>]*> 7c3c001c        sbe     gp,0\(at\)
+0+0bd4 <[^>]*> 24018000        li      at,-32768
+0+0bd8 <[^>]*> 7c3e001c        sbe     s8,0\(at\)
+0+0bdc <[^>]*> 34018000        li      at,0x8000
+0+0be0 <[^>]*> 7c3fff9c        sbe     ra,-1\(at\)
+0+0be4 <[^>]*> 34018000        li      at,0x8000
+0+0be8 <[^>]*> 7c22ff9c        sbe     v0,-1\(at\)
+0+0bec <[^>]*> 24018000        li      at,-32768
+0+0bf0 <[^>]*> 00240821        addu    at,at,a0
+0+0bf4 <[^>]*> 7c23ff9c        sbe     v1,-1\(at\)
+0+0bf8 <[^>]*> 24018000        li      at,-32768
+0+0bfc <[^>]*> 7c25ff9c        sbe     a1,-1\(at\)
+0+0c00 <[^>]*> 34018000        li      at,0x8000
+0+0c04 <[^>]*> 00270821        addu    at,at,a3
+0+0c08 <[^>]*> 7c26001c        sbe     a2,0\(at\)
+0+0c0c <[^>]*> 34018000        li      at,0x8000
+0+0c10 <[^>]*> 7c28001c        sbe     t0,0\(at\)
+0+0c14 <[^>]*> 3c018000        lui     at,0x8000
+0+0c18 <[^>]*> 002a0821        addu    at,at,t2
+0+0c1c <[^>]*> 7c29001c        sbe     t1,0\(at\)
+0+0c20 <[^>]*> 3c018000        lui     at,0x8000
+0+0c24 <[^>]*> 7c2b001c        sbe     t3,0\(at\)
+0+0c28 <[^>]*> 3c018000        lui     at,0x8000
+0+0c2c <[^>]*> 002d0821        addu    at,at,t5
+0+0c30 <[^>]*> 7c2cff9c        sbe     t4,-1\(at\)
+0+0c34 <[^>]*> 3c018000        lui     at,0x8000
+0+0c38 <[^>]*> 7c2eff9c        sbe     t6,-1\(at\)
+0+0c3c <[^>]*> 7e0f001c        sbe     t7,0\(s0\)
+0+0c40 <[^>]*> 3c010000        lui     at,0x0
+                       c40: R_MIPS_HI16        MYDATA
+0+0c44 <[^>]*> 24210000        addiu   at,at,0
+                       c44: R_MIPS_LO16        MYDATA
+0+0c48 <[^>]*> 7c31001c        sbe     s1,0\(at\)
+0+0c4c <[^>]*> 7e72801e        sce     s2,-256\(s3\)
+0+0c50 <[^>]*> 7c14801e        sce     s4,-256\(zero\)
+0+0c54 <[^>]*> 7ed57f9e        sce     s5,255\(s6\)
+0+0c58 <[^>]*> 7c177f9e        sce     s7,255\(zero\)
+0+0c5c <[^>]*> 2401fe00        li      at,-512
+0+0c60 <[^>]*> 00390821        addu    at,at,t9
+0+0c64 <[^>]*> 7c387f9e        sce     t8,255\(at\)
+0+0c68 <[^>]*> 2401fe00        li      at,-512
+0+0c6c <[^>]*> 7c3a7f9e        sce     k0,255\(at\)
+0+0c70 <[^>]*> 24010200        li      at,512
+0+0c74 <[^>]*> 003c0821        addu    at,at,gp
+0+0c78 <[^>]*> 7c3b801e        sce     k1,-256\(at\)
+0+0c7c <[^>]*> 24010200        li      at,512
+0+0c80 <[^>]*> 7c3d801e        sce     sp,-256\(at\)
+0+0c84 <[^>]*> 2401fe00        li      at,-512
+0+0c88 <[^>]*> 003f0821        addu    at,at,ra
+0+0c8c <[^>]*> 7c3e001e        sce     s8,0\(at\)
+0+0c90 <[^>]*> 2401fe00        li      at,-512
+0+0c94 <[^>]*> 7c20001e        sce     zero,0\(at\)
+0+0c98 <[^>]*> 24010200        li      at,512
+0+0c9c <[^>]*> 00230821        addu    at,at,v1
+0+0ca0 <[^>]*> 7c22ff9e        sce     v0,-1\(at\)
+0+0ca4 <[^>]*> 24010200        li      at,512
+0+0ca8 <[^>]*> 7c24ff9e        sce     a0,-1\(at\)
+0+0cac <[^>]*> 2401fc00        li      at,-1024
+0+0cb0 <[^>]*> 00260821        addu    at,at,a2
+0+0cb4 <[^>]*> 7c25001e        sce     a1,0\(at\)
+0+0cb8 <[^>]*> 2401fc00        li      at,-1024
+0+0cbc <[^>]*> 7c27001e        sce     a3,0\(at\)
+0+0cc0 <[^>]*> 24010400        li      at,1024
+0+0cc4 <[^>]*> 00290821        addu    at,at,t1
+0+0cc8 <[^>]*> 7c28ff9e        sce     t0,-1\(at\)
+0+0ccc <[^>]*> 24010400        li      at,1024
+0+0cd0 <[^>]*> 7c2aff9e        sce     t2,-1\(at\)
+0+0cd4 <[^>]*> 2401f800        li      at,-2048
+0+0cd8 <[^>]*> 002c0821        addu    at,at,t4
+0+0cdc <[^>]*> 7c2b001e        sce     t3,0\(at\)
+0+0ce0 <[^>]*> 2401f800        li      at,-2048
+0+0ce4 <[^>]*> 7c2d001e        sce     t5,0\(at\)
+0+0ce8 <[^>]*> 24010800        li      at,2048
+0+0cec <[^>]*> 002f0821        addu    at,at,t7
+0+0cf0 <[^>]*> 7c2eff9e        sce     t6,-1\(at\)
+0+0cf4 <[^>]*> 24010800        li      at,2048
+0+0cf8 <[^>]*> 7c30ff9e        sce     s0,-1\(at\)
+0+0cfc <[^>]*> 2401f000        li      at,-4096
+0+0d00 <[^>]*> 00320821        addu    at,at,s2
+0+0d04 <[^>]*> 7c31001e        sce     s1,0\(at\)
+0+0d08 <[^>]*> 2401f000        li      at,-4096
+0+0d0c <[^>]*> 7c33001e        sce     s3,0\(at\)
+0+0d10 <[^>]*> 24011000        li      at,4096
+0+0d14 <[^>]*> 00350821        addu    at,at,s5
+0+0d18 <[^>]*> 7c34ff9e        sce     s4,-1\(at\)
+0+0d1c <[^>]*> 24011000        li      at,4096
+0+0d20 <[^>]*> 7c36ff9e        sce     s6,-1\(at\)
+0+0d24 <[^>]*> 24018000        li      at,-32768
+0+0d28 <[^>]*> 00380821        addu    at,at,t8
+0+0d2c <[^>]*> 7c37001e        sce     s7,0\(at\)
+0+0d30 <[^>]*> 24018000        li      at,-32768
+0+0d34 <[^>]*> 7c39001e        sce     t9,0\(at\)
+0+0d38 <[^>]*> 34018000        li      at,0x8000
+0+0d3c <[^>]*> 003b0821        addu    at,at,k1
+0+0d40 <[^>]*> 7c3aff9e        sce     k0,-1\(at\)
+0+0d44 <[^>]*> 34018000        li      at,0x8000
+0+0d48 <[^>]*> 7c3cff9e        sce     gp,-1\(at\)
+0+0d4c <[^>]*> 24018000        li      at,-32768
+0+0d50 <[^>]*> 003e0821        addu    at,at,s8
+0+0d54 <[^>]*> 7c3dff9e        sce     sp,-1\(at\)
+0+0d58 <[^>]*> 24018000        li      at,-32768
+0+0d5c <[^>]*> 7c3fff9e        sce     ra,-1\(at\)
+0+0d60 <[^>]*> 34018000        li      at,0x8000
+0+0d64 <[^>]*> 00220821        addu    at,at,v0
+0+0d68 <[^>]*> 7c20001e        sce     zero,0\(at\)
+0+0d6c <[^>]*> 34018000        li      at,0x8000
+0+0d70 <[^>]*> 7c23001e        sce     v1,0\(at\)
+0+0d74 <[^>]*> 3c018000        lui     at,0x8000
+0+0d78 <[^>]*> 00250821        addu    at,at,a1
+0+0d7c <[^>]*> 7c24001e        sce     a0,0\(at\)
+0+0d80 <[^>]*> 3c018000        lui     at,0x8000
+0+0d84 <[^>]*> 7c26001e        sce     a2,0\(at\)
+0+0d88 <[^>]*> 3c018000        lui     at,0x8000
+0+0d8c <[^>]*> 00280821        addu    at,at,t0
+0+0d90 <[^>]*> 7c27ff9e        sce     a3,-1\(at\)
+0+0d94 <[^>]*> 3c018000        lui     at,0x8000
+0+0d98 <[^>]*> 7c29ff9e        sce     t1,-1\(at\)
+0+0d9c <[^>]*> 7d6a001e        sce     t2,0\(t3\)
+0+0da0 <[^>]*> 3c010000        lui     at,0x0
+                       da0: R_MIPS_HI16        MYDATA
+0+0da4 <[^>]*> 24210000        addiu   at,at,0
+                       da4: R_MIPS_LO16        MYDATA
+0+0da8 <[^>]*> 7c2c001e        sce     t4,0\(at\)
+0+0dac <[^>]*> 7dcd801d        she     t5,-256\(t6\)
+0+0db0 <[^>]*> 7c0f801d        she     t7,-256\(zero\)
+0+0db4 <[^>]*> 7e307f9d        she     s0,255\(s1\)
+0+0db8 <[^>]*> 7c127f9d        she     s2,255\(zero\)
+0+0dbc <[^>]*> 2401fe00        li      at,-512
+0+0dc0 <[^>]*> 00340821        addu    at,at,s4
+0+0dc4 <[^>]*> 7c337f9d        she     s3,255\(at\)
+0+0dc8 <[^>]*> 2401fe00        li      at,-512
+0+0dcc <[^>]*> 7c357f9d        she     s5,255\(at\)
+0+0dd0 <[^>]*> 24010200        li      at,512
+0+0dd4 <[^>]*> 00370821        addu    at,at,s7
+0+0dd8 <[^>]*> 7c36801d        she     s6,-256\(at\)
+0+0ddc <[^>]*> 24010200        li      at,512
+0+0de0 <[^>]*> 7c38801d        she     t8,-256\(at\)
+0+0de4 <[^>]*> 2401fe00        li      at,-512
+0+0de8 <[^>]*> 003a0821        addu    at,at,k0
+0+0dec <[^>]*> 7c39001d        she     t9,0\(at\)
+0+0df0 <[^>]*> 2401fe00        li      at,-512
+0+0df4 <[^>]*> 7c3b001d        she     k1,0\(at\)
+0+0df8 <[^>]*> 24010200        li      at,512
+0+0dfc <[^>]*> 003d0821        addu    at,at,sp
+0+0e00 <[^>]*> 7c3cff9d        she     gp,-1\(at\)
+0+0e04 <[^>]*> 24010200        li      at,512
+0+0e08 <[^>]*> 7c3eff9d        she     s8,-1\(at\)
+0+0e0c <[^>]*> 2401fc00        li      at,-1024
+0+0e10 <[^>]*> 7c3f001d        she     ra,0\(at\)
+0+0e14 <[^>]*> 2401fc00        li      at,-1024
+0+0e18 <[^>]*> 7c22001d        she     v0,0\(at\)
+0+0e1c <[^>]*> 24010400        li      at,1024
+0+0e20 <[^>]*> 00240821        addu    at,at,a0
+0+0e24 <[^>]*> 7c23ff9d        she     v1,-1\(at\)
+0+0e28 <[^>]*> 24010400        li      at,1024
+0+0e2c <[^>]*> 7c25ff9d        she     a1,-1\(at\)
+0+0e30 <[^>]*> 2401f800        li      at,-2048
+0+0e34 <[^>]*> 00270821        addu    at,at,a3
+0+0e38 <[^>]*> 7c26001d        she     a2,0\(at\)
+0+0e3c <[^>]*> 2401f800        li      at,-2048
+0+0e40 <[^>]*> 7c28001d        she     t0,0\(at\)
+0+0e44 <[^>]*> 24010800        li      at,2048
+0+0e48 <[^>]*> 002a0821        addu    at,at,t2
+0+0e4c <[^>]*> 7c29ff9d        she     t1,-1\(at\)
+0+0e50 <[^>]*> 24010800        li      at,2048
+0+0e54 <[^>]*> 7c2bff9d        she     t3,-1\(at\)
+0+0e58 <[^>]*> 2401f000        li      at,-4096
+0+0e5c <[^>]*> 002d0821        addu    at,at,t5
+0+0e60 <[^>]*> 7c2c001d        she     t4,0\(at\)
+0+0e64 <[^>]*> 2401f000        li      at,-4096
+0+0e68 <[^>]*> 7c2e001d        she     t6,0\(at\)
+0+0e6c <[^>]*> 24011000        li      at,4096
+0+0e70 <[^>]*> 00300821        addu    at,at,s0
+0+0e74 <[^>]*> 7c2fff9d        she     t7,-1\(at\)
+0+0e78 <[^>]*> 24011000        li      at,4096
+0+0e7c <[^>]*> 7c31ff9d        she     s1,-1\(at\)
+0+0e80 <[^>]*> 24018000        li      at,-32768
+0+0e84 <[^>]*> 00330821        addu    at,at,s3
+0+0e88 <[^>]*> 7c32001d        she     s2,0\(at\)
+0+0e8c <[^>]*> 24018000        li      at,-32768
+0+0e90 <[^>]*> 7c34001d        she     s4,0\(at\)
+0+0e94 <[^>]*> 34018000        li      at,0x8000
+0+0e98 <[^>]*> 00360821        addu    at,at,s6
+0+0e9c <[^>]*> 7c35ff9d        she     s5,-1\(at\)
+0+0ea0 <[^>]*> 34018000        li      at,0x8000
+0+0ea4 <[^>]*> 7c37ff9d        she     s7,-1\(at\)
+0+0ea8 <[^>]*> 24018000        li      at,-32768
+0+0eac <[^>]*> 00390821        addu    at,at,t9
+0+0eb0 <[^>]*> 7c38ff9d        she     t8,-1\(at\)
+0+0eb4 <[^>]*> 24018000        li      at,-32768
+0+0eb8 <[^>]*> 7c3aff9d        she     k0,-1\(at\)
+0+0ebc <[^>]*> 34018000        li      at,0x8000
+0+0ec0 <[^>]*> 003c0821        addu    at,at,gp
+0+0ec4 <[^>]*> 7c3b001d        she     k1,0\(at\)
+0+0ec8 <[^>]*> 34018000        li      at,0x8000
+0+0ecc <[^>]*> 7c3d001d        she     sp,0\(at\)
+0+0ed0 <[^>]*> 3c018000        lui     at,0x8000
+0+0ed4 <[^>]*> 003f0821        addu    at,at,ra
+0+0ed8 <[^>]*> 7c3e001d        she     s8,0\(at\)
+0+0edc <[^>]*> 3c018000        lui     at,0x8000
+0+0ee0 <[^>]*> 7c20001d        she     zero,0\(at\)
+0+0ee4 <[^>]*> 3c018000        lui     at,0x8000
+0+0ee8 <[^>]*> 00230821        addu    at,at,v1
+0+0eec <[^>]*> 7c22ff9d        she     v0,-1\(at\)
+0+0ef0 <[^>]*> 3c018000        lui     at,0x8000
+0+0ef4 <[^>]*> 7c24ff9d        she     a0,-1\(at\)
+0+0ef8 <[^>]*> 7cc5001d        she     a1,0\(a2\)
+0+0efc <[^>]*> 3c010000        lui     at,0x0
+                       efc: R_MIPS_HI16        MYDATA
+0+0f00 <[^>]*> 24210000        addiu   at,at,0
+                       f00: R_MIPS_LO16        MYDATA
+0+0f04 <[^>]*> 7c27001d        she     a3,0\(at\)
+0+0f08 <[^>]*> 7d28801f        swe     t0,-256\(t1\)
+0+0f0c <[^>]*> 7c0a801f        swe     t2,-256\(zero\)
+0+0f10 <[^>]*> 7d8b7f9f        swe     t3,255\(t4\)
+0+0f14 <[^>]*> 7c0d7f9f        swe     t5,255\(zero\)
+0+0f18 <[^>]*> 2401fe00        li      at,-512
+0+0f1c <[^>]*> 002f0821        addu    at,at,t7
+0+0f20 <[^>]*> 7c2e7f9f        swe     t6,255\(at\)
+0+0f24 <[^>]*> 2401fe00        li      at,-512
+0+0f28 <[^>]*> 7c307f9f        swe     s0,255\(at\)
+0+0f2c <[^>]*> 24010200        li      at,512
+0+0f30 <[^>]*> 00320821        addu    at,at,s2
+0+0f34 <[^>]*> 7c31801f        swe     s1,-256\(at\)
+0+0f38 <[^>]*> 24010200        li      at,512
+0+0f3c <[^>]*> 7c33801f        swe     s3,-256\(at\)
+0+0f40 <[^>]*> 2401fe00        li      at,-512
+0+0f44 <[^>]*> 00350821        addu    at,at,s5
+0+0f48 <[^>]*> 7c34001f        swe     s4,0\(at\)
+0+0f4c <[^>]*> 2401fe00        li      at,-512
+0+0f50 <[^>]*> 7c36001f        swe     s6,0\(at\)
+0+0f54 <[^>]*> 24010200        li      at,512
+0+0f58 <[^>]*> 00380821        addu    at,at,t8
+0+0f5c <[^>]*> 7c37ff9f        swe     s7,-1\(at\)
+0+0f60 <[^>]*> 24010200        li      at,512
+0+0f64 <[^>]*> 7c39ff9f        swe     t9,-1\(at\)
+0+0f68 <[^>]*> 2401fc00        li      at,-1024
+0+0f6c <[^>]*> 003b0821        addu    at,at,k1
+0+0f70 <[^>]*> 7c3a001f        swe     k0,0\(at\)
+0+0f74 <[^>]*> 2401fc00        li      at,-1024
+0+0f78 <[^>]*> 7c3c001f        swe     gp,0\(at\)
+0+0f7c <[^>]*> 24010400        li      at,1024
+0+0f80 <[^>]*> 003e0821        addu    at,at,s8
+0+0f84 <[^>]*> 7c3dff9f        swe     sp,-1\(at\)
+0+0f88 <[^>]*> 24010400        li      at,1024
+0+0f8c <[^>]*> 7c3fff9f        swe     ra,-1\(at\)
+0+0f90 <[^>]*> 2401f800        li      at,-2048
+0+0f94 <[^>]*> 00220821        addu    at,at,v0
+0+0f98 <[^>]*> 7c20001f        swe     zero,0\(at\)
+0+0f9c <[^>]*> 2401f800        li      at,-2048
+0+0fa0 <[^>]*> 7c23001f        swe     v1,0\(at\)
+0+0fa4 <[^>]*> 24010800        li      at,2048
+0+0fa8 <[^>]*> 00250821        addu    at,at,a1
+0+0fac <[^>]*> 7c24ff9f        swe     a0,-1\(at\)
+0+0fb0 <[^>]*> 24010800        li      at,2048
+0+0fb4 <[^>]*> 7c26ff9f        swe     a2,-1\(at\)
+0+0fb8 <[^>]*> 2401f000        li      at,-4096
+0+0fbc <[^>]*> 00280821        addu    at,at,t0
+0+0fc0 <[^>]*> 7c27001f        swe     a3,0\(at\)
+0+0fc4 <[^>]*> 2401f000        li      at,-4096
+0+0fc8 <[^>]*> 7c29001f        swe     t1,0\(at\)
+0+0fcc <[^>]*> 24011000        li      at,4096
+0+0fd0 <[^>]*> 002b0821        addu    at,at,t3
+0+0fd4 <[^>]*> 7c2aff9f        swe     t2,-1\(at\)
+0+0fd8 <[^>]*> 24011000        li      at,4096
+0+0fdc <[^>]*> 7c2cff9f        swe     t4,-1\(at\)
+0+0fe0 <[^>]*> 24018000        li      at,-32768
+0+0fe4 <[^>]*> 002e0821        addu    at,at,t6
+0+0fe8 <[^>]*> 7c2d001f        swe     t5,0\(at\)
+0+0fec <[^>]*> 24018000        li      at,-32768
+0+0ff0 <[^>]*> 7c2f001f        swe     t7,0\(at\)
+0+0ff4 <[^>]*> 34018000        li      at,0x8000
+0+0ff8 <[^>]*> 00310821        addu    at,at,s1
+0+0ffc <[^>]*> 7c30ff9f        swe     s0,-1\(at\)
+0+1000 <[^>]*> 34018000        li      at,0x8000
+0+1004 <[^>]*> 7c32ff9f        swe     s2,-1\(at\)
+0+1008 <[^>]*> 24018000        li      at,-32768
+0+100c <[^>]*> 00340821        addu    at,at,s4
+0+1010 <[^>]*> 7c33ff9f        swe     s3,-1\(at\)
+0+1014 <[^>]*> 24018000        li      at,-32768
+0+1018 <[^>]*> 7c35ff9f        swe     s5,-1\(at\)
+0+101c <[^>]*> 34018000        li      at,0x8000
+0+1020 <[^>]*> 00370821        addu    at,at,s7
+0+1024 <[^>]*> 7c36001f        swe     s6,0\(at\)
+0+1028 <[^>]*> 34018000        li      at,0x8000
+0+102c <[^>]*> 7c38001f        swe     t8,0\(at\)
+0+1030 <[^>]*> 3c018000        lui     at,0x8000
+0+1034 <[^>]*> 003a0821        addu    at,at,k0
+0+1038 <[^>]*> 7c39001f        swe     t9,0\(at\)
+0+103c <[^>]*> 3c018000        lui     at,0x8000
+0+1040 <[^>]*> 7c3b001f        swe     k1,0\(at\)
+0+1044 <[^>]*> 3c018000        lui     at,0x8000
+0+1048 <[^>]*> 003d0821        addu    at,at,sp
+0+104c <[^>]*> 7c3cff9f        swe     gp,-1\(at\)
+0+1050 <[^>]*> 3c018000        lui     at,0x8000
+0+1054 <[^>]*> 7c3eff9f        swe     s8,-1\(at\)
+0+1058 <[^>]*> 7c1f001f        swe     ra,0\(zero\)
+0+105c <[^>]*> 3c010000        lui     at,0x0
+                       105c: R_MIPS_HI16       MYDATA
+0+1060 <[^>]*> 24210000        addiu   at,at,0
+                       1060: R_MIPS_LO16       MYDATA
+0+1064 <[^>]*> 7c22001f        swe     v0,0\(at\)
+0+1068 <[^>]*> 7c838021        swle    v1,-256\(a0\)
+0+106c <[^>]*> 7c058021        swle    a1,-256\(zero\)
+0+1070 <[^>]*> 7ce67fa1        swle    a2,255\(a3\)
+0+1074 <[^>]*> 7c087fa1        swle    t0,255\(zero\)
+0+1078 <[^>]*> 2401fe00        li      at,-512
+0+107c <[^>]*> 002a0821        addu    at,at,t2
+0+1080 <[^>]*> 7c297fa1        swle    t1,255\(at\)
+0+1084 <[^>]*> 2401fe00        li      at,-512
+0+1088 <[^>]*> 7c2b7fa1        swle    t3,255\(at\)
+0+108c <[^>]*> 24010200        li      at,512
+0+1090 <[^>]*> 002d0821        addu    at,at,t5
+0+1094 <[^>]*> 7c2c8021        swle    t4,-256\(at\)
+0+1098 <[^>]*> 24010200        li      at,512
+0+109c <[^>]*> 7c2e8021        swle    t6,-256\(at\)
+0+10a0 <[^>]*> 2401fe00        li      at,-512
+0+10a4 <[^>]*> 00300821        addu    at,at,s0
+0+10a8 <[^>]*> 7c2f0021        swle    t7,0\(at\)
+0+10ac <[^>]*> 2401fe00        li      at,-512
+0+10b0 <[^>]*> 7c310021        swle    s1,0\(at\)
+0+10b4 <[^>]*> 24010200        li      at,512
+0+10b8 <[^>]*> 00330821        addu    at,at,s3
+0+10bc <[^>]*> 7c32ffa1        swle    s2,-1\(at\)
+0+10c0 <[^>]*> 24010200        li      at,512
+0+10c4 <[^>]*> 7c34ffa1        swle    s4,-1\(at\)
+0+10c8 <[^>]*> 2401fc00        li      at,-1024
+0+10cc <[^>]*> 00360821        addu    at,at,s6
+0+10d0 <[^>]*> 7c350021        swle    s5,0\(at\)
+0+10d4 <[^>]*> 2401fc00        li      at,-1024
+0+10d8 <[^>]*> 7c370021        swle    s7,0\(at\)
+0+10dc <[^>]*> 24010400        li      at,1024
+0+10e0 <[^>]*> 00390821        addu    at,at,t9
+0+10e4 <[^>]*> 7c38ffa1        swle    t8,-1\(at\)
+0+10e8 <[^>]*> 24010400        li      at,1024
+0+10ec <[^>]*> 7c3affa1        swle    k0,-1\(at\)
+0+10f0 <[^>]*> 2401f800        li      at,-2048
+0+10f4 <[^>]*> 003c0821        addu    at,at,gp
+0+10f8 <[^>]*> 7c3b0021        swle    k1,0\(at\)
+0+10fc <[^>]*> 2401f800        li      at,-2048
+0+1100 <[^>]*> 7c3d0021        swle    sp,0\(at\)
+0+1104 <[^>]*> 24010800        li      at,2048
+0+1108 <[^>]*> 003f0821        addu    at,at,ra
+0+110c <[^>]*> 7c3effa1        swle    s8,-1\(at\)
+0+1110 <[^>]*> 24010800        li      at,2048
+0+1114 <[^>]*> 7c20ffa1        swle    zero,-1\(at\)
+0+1118 <[^>]*> 2401f000        li      at,-4096
+0+111c <[^>]*> 00230821        addu    at,at,v1
+0+1120 <[^>]*> 7c220021        swle    v0,0\(at\)
+0+1124 <[^>]*> 2401f000        li      at,-4096
+0+1128 <[^>]*> 7c240021        swle    a0,0\(at\)
+0+112c <[^>]*> 24011000        li      at,4096
+0+1130 <[^>]*> 00260821        addu    at,at,a2
+0+1134 <[^>]*> 7c25ffa1        swle    a1,-1\(at\)
+0+1138 <[^>]*> 24011000        li      at,4096
+0+113c <[^>]*> 7c27ffa1        swle    a3,-1\(at\)
+0+1140 <[^>]*> 24018000        li      at,-32768
+0+1144 <[^>]*> 00290821        addu    at,at,t1
+0+1148 <[^>]*> 7c280021        swle    t0,0\(at\)
+0+114c <[^>]*> 24018000        li      at,-32768
+0+1150 <[^>]*> 7c2a0021        swle    t2,0\(at\)
+0+1154 <[^>]*> 34018000        li      at,0x8000
+0+1158 <[^>]*> 002c0821        addu    at,at,t4
+0+115c <[^>]*> 7c2bffa1        swle    t3,-1\(at\)
+0+1160 <[^>]*> 34018000        li      at,0x8000
+0+1164 <[^>]*> 7c2dffa1        swle    t5,-1\(at\)
+0+1168 <[^>]*> 24018000        li      at,-32768
+0+116c <[^>]*> 002f0821        addu    at,at,t7
+0+1170 <[^>]*> 7c2effa1        swle    t6,-1\(at\)
+0+1174 <[^>]*> 24018000        li      at,-32768
+0+1178 <[^>]*> 7c30ffa1        swle    s0,-1\(at\)
+0+117c <[^>]*> 34018000        li      at,0x8000
+0+1180 <[^>]*> 00320821        addu    at,at,s2
+0+1184 <[^>]*> 7c310021        swle    s1,0\(at\)
+0+1188 <[^>]*> 34018000        li      at,0x8000
+0+118c <[^>]*> 7c330021        swle    s3,0\(at\)
+0+1190 <[^>]*> 3c018000        lui     at,0x8000
+0+1194 <[^>]*> 00350821        addu    at,at,s5
+0+1198 <[^>]*> 7c340021        swle    s4,0\(at\)
+0+119c <[^>]*> 3c018000        lui     at,0x8000
+0+11a0 <[^>]*> 7c360021        swle    s6,0\(at\)
+0+11a4 <[^>]*> 3c018000        lui     at,0x8000
+0+11a8 <[^>]*> 00380821        addu    at,at,t8
+0+11ac <[^>]*> 7c37ffa1        swle    s7,-1\(at\)
+0+11b0 <[^>]*> 3c018000        lui     at,0x8000
+0+11b4 <[^>]*> 7c39ffa1        swle    t9,-1\(at\)
+0+11b8 <[^>]*> 7f7a0021        swle    k0,0\(k1\)
+0+11bc <[^>]*> 3c010000        lui     at,0x0
+                       11bc: R_MIPS_HI16       MYDATA
+0+11c0 <[^>]*> 24210000        addiu   at,at,0
+                       11c0: R_MIPS_LO16       MYDATA
+0+11c4 <[^>]*> 7c3c0021        swle    gp,0\(at\)
+0+11c8 <[^>]*> 7fdd8022        swre    sp,-256\(s8\)
+0+11cc <[^>]*> 7c1f8022        swre    ra,-256\(zero\)
+0+11d0 <[^>]*> 7c407fa2        swre    zero,255\(v0\)
+0+11d4 <[^>]*> 7c037fa2        swre    v1,255\(zero\)
+0+11d8 <[^>]*> 2401fe00        li      at,-512
+0+11dc <[^>]*> 00250821        addu    at,at,a1
+0+11e0 <[^>]*> 7c247fa2        swre    a0,255\(at\)
+0+11e4 <[^>]*> 2401fe00        li      at,-512
+0+11e8 <[^>]*> 7c267fa2        swre    a2,255\(at\)
+0+11ec <[^>]*> 24010200        li      at,512
+0+11f0 <[^>]*> 00280821        addu    at,at,t0
+0+11f4 <[^>]*> 7c278022        swre    a3,-256\(at\)
+0+11f8 <[^>]*> 24010200        li      at,512
+0+11fc <[^>]*> 7c298022        swre    t1,-256\(at\)
+0+1200 <[^>]*> 2401fe00        li      at,-512
+0+1204 <[^>]*> 002b0821        addu    at,at,t3
+0+1208 <[^>]*> 7c2a0022        swre    t2,0\(at\)
+0+120c <[^>]*> 2401fe00        li      at,-512
+0+1210 <[^>]*> 7c2c0022        swre    t4,0\(at\)
+0+1214 <[^>]*> 24010200        li      at,512
+0+1218 <[^>]*> 002e0821        addu    at,at,t6
+0+121c <[^>]*> 7c2dffa2        swre    t5,-1\(at\)
+0+1220 <[^>]*> 24010200        li      at,512
+0+1224 <[^>]*> 7c2fffa2        swre    t7,-1\(at\)
+0+1228 <[^>]*> 2401fc00        li      at,-1024
+0+122c <[^>]*> 00310821        addu    at,at,s1
+0+1230 <[^>]*> 7c300022        swre    s0,0\(at\)
+0+1234 <[^>]*> 2401fc00        li      at,-1024
+0+1238 <[^>]*> 7c320022        swre    s2,0\(at\)
+0+123c <[^>]*> 24010400        li      at,1024
+0+1240 <[^>]*> 00340821        addu    at,at,s4
+0+1244 <[^>]*> 7c33ffa2        swre    s3,-1\(at\)
+0+1248 <[^>]*> 24010400        li      at,1024
+0+124c <[^>]*> 7c35ffa2        swre    s5,-1\(at\)
+0+1250 <[^>]*> 2401f800        li      at,-2048
+0+1254 <[^>]*> 00370821        addu    at,at,s7
+0+1258 <[^>]*> 7c360022        swre    s6,0\(at\)
+0+125c <[^>]*> 2401f800        li      at,-2048
+0+1260 <[^>]*> 7c380022        swre    t8,0\(at\)
+0+1264 <[^>]*> 24010800        li      at,2048
+0+1268 <[^>]*> 003a0821        addu    at,at,k0
+0+126c <[^>]*> 7c39ffa2        swre    t9,-1\(at\)
+0+1270 <[^>]*> 24010800        li      at,2048
+0+1274 <[^>]*> 7c3bffa2        swre    k1,-1\(at\)
+0+1278 <[^>]*> 2401f000        li      at,-4096
+0+127c <[^>]*> 003d0821        addu    at,at,sp
+0+1280 <[^>]*> 7c3c0022        swre    gp,0\(at\)
+0+1284 <[^>]*> 2401f000        li      at,-4096
+0+1288 <[^>]*> 7c3e0022        swre    s8,0\(at\)
+0+128c <[^>]*> 24011000        li      at,4096
+0+1290 <[^>]*> 7c3fffa2        swre    ra,-1\(at\)
+0+1294 <[^>]*> 24011000        li      at,4096
+0+1298 <[^>]*> 7c22ffa2        swre    v0,-1\(at\)
+0+129c <[^>]*> 24018000        li      at,-32768
+0+12a0 <[^>]*> 00240821        addu    at,at,a0
+0+12a4 <[^>]*> 7c230022        swre    v1,0\(at\)
+0+12a8 <[^>]*> 24018000        li      at,-32768
+0+12ac <[^>]*> 7c250022        swre    a1,0\(at\)
+0+12b0 <[^>]*> 34018000        li      at,0x8000
+0+12b4 <[^>]*> 00270821        addu    at,at,a3
+0+12b8 <[^>]*> 7c26ffa2        swre    a2,-1\(at\)
+0+12bc <[^>]*> 34018000        li      at,0x8000
+0+12c0 <[^>]*> 7c28ffa2        swre    t0,-1\(at\)
+0+12c4 <[^>]*> 24018000        li      at,-32768
+0+12c8 <[^>]*> 002a0821        addu    at,at,t2
+0+12cc <[^>]*> 7c29ffa2        swre    t1,-1\(at\)
+0+12d0 <[^>]*> 24018000        li      at,-32768
+0+12d4 <[^>]*> 7c2bffa2        swre    t3,-1\(at\)
+0+12d8 <[^>]*> 34018000        li      at,0x8000
+0+12dc <[^>]*> 002d0821        addu    at,at,t5
+0+12e0 <[^>]*> 7c2c0022        swre    t4,0\(at\)
+0+12e4 <[^>]*> 34018000        li      at,0x8000
+0+12e8 <[^>]*> 7c2e0022        swre    t6,0\(at\)
+0+12ec <[^>]*> 3c018000        lui     at,0x8000
+0+12f0 <[^>]*> 00300821        addu    at,at,s0
+0+12f4 <[^>]*> 7c2f0022        swre    t7,0\(at\)
+0+12f8 <[^>]*> 3c018000        lui     at,0x8000
+0+12fc <[^>]*> 7c310022        swre    s1,0\(at\)
+0+1300 <[^>]*> 3c018000        lui     at,0x8000
+0+1304 <[^>]*> 00330821        addu    at,at,s3
+0+1308 <[^>]*> 7c32ffa2        swre    s2,-1\(at\)
+0+130c <[^>]*> 3c018000        lui     at,0x8000
+0+1310 <[^>]*> 7c34ffa2        swre    s4,-1\(at\)
+0+1314 <[^>]*> 7ed50022        swre    s5,0\(s6\)
+0+1318 <[^>]*> 3c010000        lui     at,0x0
+                       1318: R_MIPS_HI16       MYDATA
+0+131c <[^>]*> 24210000        addiu   at,at,0
+                       131c: R_MIPS_LO16       MYDATA
+0+1320 <[^>]*> 7c370022        swre    s7,0\(at\)
+0+1324 <[^>]*> 7f38801b        cachee  0x18,-256\(t9\)
+0+1328 <[^>]*> 7c1a801b        cachee  0x1a,-256\(zero\)
+0+132c <[^>]*> 7f9b7f9b        cachee  0x1b,255\(gp\)
+0+1330 <[^>]*> 7c1d7f9b        cachee  0x1d,255\(zero\)
+0+1334 <[^>]*> 2401fe00        li      at,-512
+0+1338 <[^>]*> 003f0821        addu    at,at,ra
+0+133c <[^>]*> 7c3e7f9b        cachee  0x1e,255\(at\)
+0+1340 <[^>]*> 2401fe00        li      at,-512
+0+1344 <[^>]*> 7c207f9b        cachee  0x0,255\(at\)
+0+1348 <[^>]*> 24010200        li      at,512
+0+134c <[^>]*> 00230821        addu    at,at,v1
+0+1350 <[^>]*> 7c22801b        cachee  0x2,-256\(at\)
+0+1354 <[^>]*> 24010200        li      at,512
+0+1358 <[^>]*> 7c24801b        cachee  0x4,-256\(at\)
+0+135c <[^>]*> 2401fe00        li      at,-512
+0+1360 <[^>]*> 00260821        addu    at,at,a2
+0+1364 <[^>]*> 7c25001b        cachee  0x5,0\(at\)
+0+1368 <[^>]*> 2401fe00        li      at,-512
+0+136c <[^>]*> 7c27001b        cachee  0x7,0\(at\)
+0+1370 <[^>]*> 24010200        li      at,512
+0+1374 <[^>]*> 00290821        addu    at,at,t1
+0+1378 <[^>]*> 7c28ff9b        cachee  0x8,-1\(at\)
+0+137c <[^>]*> 24010200        li      at,512
+0+1380 <[^>]*> 7c2aff9b        cachee  0xa,-1\(at\)
+0+1384 <[^>]*> 2401fc00        li      at,-1024
+0+1388 <[^>]*> 002c0821        addu    at,at,t4
+0+138c <[^>]*> 7c2b001b        cachee  0xb,0\(at\)
+0+1390 <[^>]*> 2401fc00        li      at,-1024
+0+1394 <[^>]*> 7c2d001b        cachee  0xd,0\(at\)
+0+1398 <[^>]*> 24010400        li      at,1024
+0+139c <[^>]*> 002f0821        addu    at,at,t7
+0+13a0 <[^>]*> 7c2eff9b        cachee  0xe,-1\(at\)
+0+13a4 <[^>]*> 24010400        li      at,1024
+0+13a8 <[^>]*> 7c30ff9b        cachee  0x10,-1\(at\)
+0+13ac <[^>]*> 2401f800        li      at,-2048
+0+13b0 <[^>]*> 00320821        addu    at,at,s2
+0+13b4 <[^>]*> 7c31001b        cachee  0x11,0\(at\)
+0+13b8 <[^>]*> 2401f800        li      at,-2048
+0+13bc <[^>]*> 7c33001b        cachee  0x13,0\(at\)
+0+13c0 <[^>]*> 24010800        li      at,2048
+0+13c4 <[^>]*> 00350821        addu    at,at,s5
+0+13c8 <[^>]*> 7c34ff9b        cachee  0x14,-1\(at\)
+0+13cc <[^>]*> 24010800        li      at,2048
+0+13d0 <[^>]*> 7c36ff9b        cachee  0x16,-1\(at\)
+0+13d4 <[^>]*> 2401f000        li      at,-4096
+0+13d8 <[^>]*> 00380821        addu    at,at,t8
+0+13dc <[^>]*> 7c37001b        cachee  0x17,0\(at\)
+0+13e0 <[^>]*> 2401f000        li      at,-4096
+0+13e4 <[^>]*> 7c39001b        cachee  0x19,0\(at\)
+0+13e8 <[^>]*> 24011000        li      at,4096
+0+13ec <[^>]*> 003b0821        addu    at,at,k1
+0+13f0 <[^>]*> 7c3aff9b        cachee  0x1a,-1\(at\)
+0+13f4 <[^>]*> 24011000        li      at,4096
+0+13f8 <[^>]*> 7c3cff9b        cachee  0x1c,-1\(at\)
+0+13fc <[^>]*> 24018000        li      at,-32768
+0+1400 <[^>]*> 003e0821        addu    at,at,s8
+0+1404 <[^>]*> 7c3d001b        cachee  0x1d,0\(at\)
+0+1408 <[^>]*> 24018000        li      at,-32768
+0+140c <[^>]*> 7c3f001b        cachee  0x1f,0\(at\)
+0+1410 <[^>]*> 34018000        li      at,0x8000
+0+1414 <[^>]*> 00220821        addu    at,at,v0
+0+1418 <[^>]*> 7c20ff9b        cachee  0x0,-1\(at\)
+0+141c <[^>]*> 34018000        li      at,0x8000
+0+1420 <[^>]*> 7c23ff9b        cachee  0x3,-1\(at\)
+0+1424 <[^>]*> 24018000        li      at,-32768
+0+1428 <[^>]*> 00250821        addu    at,at,a1
+0+142c <[^>]*> 7c24ff9b        cachee  0x4,-1\(at\)
+0+1430 <[^>]*> 24018000        li      at,-32768
+0+1434 <[^>]*> 7c26ff9b        cachee  0x6,-1\(at\)
+0+1438 <[^>]*> 34018000        li      at,0x8000
+0+143c <[^>]*> 00280821        addu    at,at,t0
+0+1440 <[^>]*> 7c27001b        cachee  0x7,0\(at\)
+0+1444 <[^>]*> 34018000        li      at,0x8000
+0+1448 <[^>]*> 7c29001b        cachee  0x9,0\(at\)
+0+144c <[^>]*> 3c018000        lui     at,0x8000
+0+1450 <[^>]*> 002b0821        addu    at,at,t3
+0+1454 <[^>]*> 7c2a001b        cachee  0xa,0\(at\)
+0+1458 <[^>]*> 3c018000        lui     at,0x8000
+0+145c <[^>]*> 7c2c001b        cachee  0xc,0\(at\)
+0+1460 <[^>]*> 3c018000        lui     at,0x8000
+0+1464 <[^>]*> 002e0821        addu    at,at,t6
+0+1468 <[^>]*> 7c2dff9b        cachee  0xd,-1\(at\)
+0+146c <[^>]*> 3c018000        lui     at,0x8000
+0+1470 <[^>]*> 7c2fff9b        cachee  0xf,-1\(at\)
+0+1474 <[^>]*> 7e30001b        cachee  0x10,0\(s1\)
+0+1478 <[^>]*> 3c010000        lui     at,0x0
+                       1478: R_MIPS_HI16       MYDATA
+0+147c <[^>]*> 24210000        addiu   at,at,0
+                       147c: R_MIPS_LO16       MYDATA
+0+1480 <[^>]*> 7c32001b        cachee  0x12,0\(at\)
+0+1484 <[^>]*> 7e938023        prefe   0x13,-256\(s4\)
+0+1488 <[^>]*> 7c158023        prefe   0x15,-256\(zero\)
+0+148c <[^>]*> 7ef67fa3        prefe   0x16,255\(s7\)
+0+1490 <[^>]*> 7c187fa3        prefe   0x18,255\(zero\)
+0+1494 <[^>]*> 2401fe00        li      at,-512
+0+1498 <[^>]*> 003a0821        addu    at,at,k0
+0+149c <[^>]*> 7c397fa3        prefe   0x19,255\(at\)
+0+14a0 <[^>]*> 2401fe00        li      at,-512
+0+14a4 <[^>]*> 7c3b7fa3        prefe   0x1b,255\(at\)
+0+14a8 <[^>]*> 24010200        li      at,512
+0+14ac <[^>]*> 003d0821        addu    at,at,sp
+0+14b0 <[^>]*> 7c3c8023        prefe   0x1c,-256\(at\)
+0+14b4 <[^>]*> 24010200        li      at,512
+0+14b8 <[^>]*> 7c3e8023        prefe   0x1e,-256\(at\)
+0+14bc <[^>]*> 2401fe00        li      at,-512
+0+14c0 <[^>]*> 7c3f0023        prefe   0x1f,0\(at\)
+0+14c4 <[^>]*> 2401fe00        li      at,-512
+0+14c8 <[^>]*> 7c220023        prefe   0x2,0\(at\)
+0+14cc <[^>]*> 24010200        li      at,512
+0+14d0 <[^>]*> 00240821        addu    at,at,a0
+0+14d4 <[^>]*> 7c23ffa3        prefe   0x3,-1\(at\)
+0+14d8 <[^>]*> 24010200        li      at,512
+0+14dc <[^>]*> 7c25ffa3        prefe   0x5,-1\(at\)
+0+14e0 <[^>]*> 2401fc00        li      at,-1024
+0+14e4 <[^>]*> 00270821        addu    at,at,a3
+0+14e8 <[^>]*> 7c260023        prefe   0x6,0\(at\)
+0+14ec <[^>]*> 2401fc00        li      at,-1024
+0+14f0 <[^>]*> 7c280023        prefe   0x8,0\(at\)
+0+14f4 <[^>]*> 24010400        li      at,1024
+0+14f8 <[^>]*> 002a0821        addu    at,at,t2
+0+14fc <[^>]*> 7c29ffa3        prefe   0x9,-1\(at\)
+0+1500 <[^>]*> 24010400        li      at,1024
+0+1504 <[^>]*> 7c2bffa3        prefe   0xb,-1\(at\)
+0+1508 <[^>]*> 2401f800        li      at,-2048
+0+150c <[^>]*> 002d0821        addu    at,at,t5
+0+1510 <[^>]*> 7c2c0023        prefe   0xc,0\(at\)
+0+1514 <[^>]*> 2401f800        li      at,-2048
+0+1518 <[^>]*> 7c2e0023        prefe   0xe,0\(at\)
+0+151c <[^>]*> 24010800        li      at,2048
+0+1520 <[^>]*> 00300821        addu    at,at,s0
+0+1524 <[^>]*> 7c2fffa3        prefe   0xf,-1\(at\)
+0+1528 <[^>]*> 24010800        li      at,2048
+0+152c <[^>]*> 7c31ffa3        prefe   0x11,-1\(at\)
+0+1530 <[^>]*> 2401f000        li      at,-4096
+0+1534 <[^>]*> 00330821        addu    at,at,s3
+0+1538 <[^>]*> 7c320023        prefe   0x12,0\(at\)
+0+153c <[^>]*> 2401f000        li      at,-4096
+0+1540 <[^>]*> 7c340023        prefe   0x14,0\(at\)
+0+1544 <[^>]*> 24011000        li      at,4096
+0+1548 <[^>]*> 00360821        addu    at,at,s6
+0+154c <[^>]*> 7c35ffa3        prefe   0x15,-1\(at\)
+0+1550 <[^>]*> 24011000        li      at,4096
+0+1554 <[^>]*> 7c37ffa3        prefe   0x17,-1\(at\)
+0+1558 <[^>]*> 24018000        li      at,-32768
+0+155c <[^>]*> 00390821        addu    at,at,t9
+0+1560 <[^>]*> 7c380023        prefe   0x18,0\(at\)
+0+1564 <[^>]*> 24018000        li      at,-32768
+0+1568 <[^>]*> 7c3a0023        prefe   0x1a,0\(at\)
+0+156c <[^>]*> 34018000        li      at,0x8000
+0+1570 <[^>]*> 003c0821        addu    at,at,gp
+0+1574 <[^>]*> 7c3bffa3        prefe   0x1b,-1\(at\)
+0+1578 <[^>]*> 34018000        li      at,0x8000
+0+157c <[^>]*> 7c3dffa3        prefe   0x1d,-1\(at\)
+0+1580 <[^>]*> 24018000        li      at,-32768
+0+1584 <[^>]*> 003f0821        addu    at,at,ra
+0+1588 <[^>]*> 7c3effa3        prefe   0x1e,-1\(at\)
+0+158c <[^>]*> 24018000        li      at,-32768
+0+1590 <[^>]*> 7c20ffa3        prefe   0x0,-1\(at\)
+0+1594 <[^>]*> 34018000        li      at,0x8000
+0+1598 <[^>]*> 00230821        addu    at,at,v1
+0+159c <[^>]*> 7c220023        prefe   0x2,0\(at\)
+0+15a0 <[^>]*> 34018000        li      at,0x8000
+0+15a4 <[^>]*> 7c240023        prefe   0x4,0\(at\)
+0+15a8 <[^>]*> 3c018000        lui     at,0x8000
+0+15ac <[^>]*> 00260821        addu    at,at,a2
+0+15b0 <[^>]*> 7c250023        prefe   0x5,0\(at\)
+0+15b4 <[^>]*> 3c018000        lui     at,0x8000
+0+15b8 <[^>]*> 7c270023        prefe   0x7,0\(at\)
+0+15bc <[^>]*> 3c018000        lui     at,0x8000
+0+15c0 <[^>]*> 00290821        addu    at,at,t1
+0+15c4 <[^>]*> 7c28ffa3        prefe   0x8,-1\(at\)
+0+15c8 <[^>]*> 3c018000        lui     at,0x8000
+0+15cc <[^>]*> 7c2affa3        prefe   0xa,-1\(at\)
+0+15d0 <[^>]*> 7d8b0023        prefe   0xb,0\(t4\)
+0+15d4 <[^>]*> 3c010000        lui     at,0x0
+                       15d4: R_MIPS_HI16       MYDATA
+0+15d8 <[^>]*> 24210000        addiu   at,at,0
+                       15d8: R_MIPS_LO16       MYDATA
+0+15dc <[^>]*> 7c2d0023        prefe   0xd,0\(at\)

diff --git a/gas/testsuite/gas/mips/eva.s b/gas/testsuite/gas/mips/eva.s
new file mode 100644 (file)
index 0000000..f002e35
--- /dev/null
+++ b/gas/testsuite/gas/mips/eva.s
@@ -0,0 +1,612 @@
+       .text
+       .set    nomips16
+       .set    noreorder
+test_eva:
+       lbue    $0,-256($2)
+       lbue    $3,-256
+       lbue    $4,255($5)
+       lbue    $6,255
+       lbue    $7,-257($8)
+       lbue    $9,-257
+       lbue    $10,256($11)
+       lbue    $12,256
+       lbue    $13,-512($14)
+       lbue    $15,-512
+       lbue    $16,511($17)
+       lbue    $18,511
+       lbue    $19,-1024($20)
+       lbue    $21,-1024
+       lbue    $22,1023($23)
+       lbue    $24,1023
+       lbue    $25,-2048($26)
+       lbue    $27,-2048
+       lbue    $28,2047($29)
+       lbue    $30,2047
+       lbue    $31,-4096($0)
+       lbue    $2,-4096
+       lbue    $3,4095($4)
+       lbue    $5,4095
+       lbue    $6,-32768($7)
+       lbue    $8,-32768
+       lbue    $9,32767($10)
+       lbue    $11,32767
+       lbue    $12,-32769($13)
+       lbue    $14,-32769
+       lbue    $15,32768($16)
+       lbue    $17,32768
+       lbue    $18,-2147483648($19)
+       lbue    $20,-2147483648
+       lbue    $21,2147483647($22)
+       lbue    $23,2147483647
+       lbue    $24,($25)
+       lbue    $26,MYDATA
+       lhue    $27,-256($28)
+       lhue    $29,-256
+       lhue    $30,255($31)
+       lhue    $0,255
+       lhue    $2,-257($3)
+       lhue    $4,-257
+       lhue    $5,256($6)
+       lhue    $7,256
+       lhue    $8,-512($9)
+       lhue    $10,-512
+       lhue    $11,511($12)
+       lhue    $13,511
+       lhue    $14,-1024($15)
+       lhue    $16,-1024
+       lhue    $17,1023($18)
+       lhue    $19,1023
+       lhue    $20,-2048($21)
+       lhue    $22,-2048
+       lhue    $23,2047($24)
+       lhue    $25,2047
+       lhue    $26,-4096($27)
+       lhue    $28,-4096
+       lhue    $29,4095($30)
+       lhue    $31,4095
+       lhue    $0,-32768($2)
+       lhue    $3,-32768
+       lhue    $4,32767($5)
+       lhue    $6,32767
+       lhue    $7,-32769($8)
+       lhue    $9,-32769
+       lhue    $10,32768($11)
+       lhue    $12,32768
+       lhue    $13,-2147483648($14)
+       lhue    $15,-2147483648
+       lhue    $16,2147483647($17)
+       lhue    $18,2147483647
+       lhue    $19,($20)
+       lhue    $21,MYDATA
+       lbe     $22,-256($23)
+       lbe     $24,-256
+       lbe     $25,255($26)
+       lbe     $27,255
+       lbe     $28,-257($29)
+       lbe     $30,-257
+       lbe     $31,256($0)
+       lbe     $2,256
+       lbe     $3,-512($4)
+       lbe     $5,-512
+       lbe     $6,511($7)
+       lbe     $8,511
+       lbe     $9,-1024($10)
+       lbe     $11,-1024
+       lbe     $12,1023($13)
+       lbe     $14,1023
+       lbe     $15,-2048($16)
+       lbe     $17,-2048
+       lbe     $18,2047($19)
+       lbe     $20,2047
+       lbe     $21,-4096($22)
+       lbe     $23,-4096
+       lbe     $24,4095($25)
+       lbe     $26,4095
+       lbe     $27,-32768($28)
+       lbe     $29,-32768
+       lbe     $30,32767($31)
+       lbe     $0,32767
+       lbe     $2,-32769($3)
+       lbe     $4,-32769
+       lbe     $5,32768($6)
+       lbe     $7,32768
+       lbe     $8,-2147483648($9)
+       lbe     $10,-2147483648
+       lbe     $11,2147483647($12)
+       lbe     $13,2147483647
+       lbe     $14,($15)
+       lbe     $16,MYDATA
+       lhe     $17,-256($18)
+       lhe     $19,-256
+       lhe     $20,255($21)
+       lhe     $22,255
+       lhe     $23,-257($24)
+       lhe     $25,-257
+       lhe     $26,256($27)
+       lhe     $28,256
+       lhe     $29,-512($30)
+       lhe     $31,-512
+       lhe     $0,511($2)
+       lhe     $3,511
+       lhe     $4,-1024($5)
+       lhe     $6,-1024
+       lhe     $7,1023($8)
+       lhe     $9,1023
+       lhe     $10,-2048($11)
+       lhe     $12,-2048
+       lhe     $13,2047($14)
+       lhe     $15,2047
+       lhe     $16,-4096($17)
+       lhe     $18,-4096
+       lhe     $19,4095($20)
+       lhe     $21,4095
+       lhe     $22,-32768($23)
+       lhe     $24,-32768
+       lhe     $25,32767($26)
+       lhe     $27,32767
+       lhe     $28,-32769($29)
+       lhe     $30,-32769
+       lhe     $31,32768($0)
+       lhe     $2,32768
+       lhe     $3,-2147483648($4)
+       lhe     $5,-2147483648
+       lhe     $6,2147483647($7)
+       lhe     $8,2147483647
+       lhe     $9,($10)
+       lhe     $11,MYDATA
+       lle     $12,-256($13)
+       lle     $14,-256
+       lle     $15,255($16)
+       lle     $17,255
+       lle     $18,-257($19)
+       lle     $20,-257
+       lle     $21,256($22)
+       lle     $23,256
+       lle     $24,-512($25)
+       lle     $26,-512
+       lle     $27,511($28)
+       lle     $29,511
+       lle     $30,-1024($31)
+       lle     $0,-1024
+       lle     $2,1023($3)
+       lle     $4,1023
+       lle     $5,-2048($6)
+       lle     $7,-2048
+       lle     $8,2047($9)
+       lle     $10,2047
+       lle     $11,-4096($12)
+       lle     $13,-4096
+       lle     $14,4095($15)
+       lle     $16,4095
+       lle     $17,-32768($18)
+       lle     $19,-32768
+       lle     $20,32767($21)
+       lle     $22,32767
+       lle     $23,-32769($24)
+       lle     $25,-32769
+       lle     $26,32768($27)
+       lle     $28,32768
+       lle     $29,-2147483648($30)
+       lle     $31,-2147483648
+       lle     $0,2147483647($2)
+       lle     $3,2147483647
+       lle     $4,($5)
+       lle     $6,MYDATA
+       lwe     $7,-256($8)
+       lwe     $9,-256
+       lwe     $10,255($11)
+       lwe     $12,255
+       lwe     $13,-257($14)
+       lwe     $15,-257
+       lwe     $16,256($17)
+       lwe     $18,256
+       lwe     $19,-512($20)
+       lwe     $21,-512
+       lwe     $22,511($23)
+       lwe     $24,511
+       lwe     $25,-1024($26)
+       lwe     $27,-1024
+       lwe     $28,1023($29)
+       lwe     $30,1023
+       lwe     $31,-2048($0)
+       lwe     $2,-2048
+       lwe     $3,2047($4)
+       lwe     $5,2047
+       lwe     $6,-4096($7)
+       lwe     $8,-4096
+       lwe     $9,4095($10)
+       lwe     $11,4095
+       lwe     $12,-32768($13)
+       lwe     $14,-32768
+       lwe     $15,32767($16)
+       lwe     $17,32767
+       lwe     $18,-32769($19)
+       lwe     $20,-32769
+       lwe     $21,32768($22)
+       lwe     $23,32768
+       lwe     $24,-2147483648($25)
+       lwe     $26,-2147483648
+       lwe     $27,2147483647($28)
+       lwe     $29,2147483647
+       lwe     $30,($31)
+       lwe     $0,MYDATA
+       lwle    $2,-256($3)
+       lwle    $4,-256
+       lwle    $5,255($6)
+       lwle    $7,255
+       lwle    $8,-257($9)
+       lwle    $10,-257
+       lwle    $11,256($12)
+       lwle    $13,256
+       lwle    $14,-512($15)
+       lwle    $16,-512
+       lwle    $17,511($18)
+       lwle    $19,511
+       lwle    $20,-1024($21)
+       lwle    $22,-1024
+       lwle    $23,1023($24)
+       lwle    $25,1023
+       lwle    $26,-2048($27)
+       lwle    $28,-2048
+       lwle    $29,2047($30)
+       lwle    $31,2047
+       lwle    $0,-4096($2)
+       lwle    $3,-4096
+       lwle    $4,4095($5)
+       lwle    $6,4095
+       lwle    $7,-32768($8)
+       lwle    $9,-32768
+       lwle    $10,32767($11)
+       lwle    $12,32767
+       lwle    $13,-32769($14)
+       lwle    $15,-32769
+       lwle    $16,32768($17)
+       lwle    $18,32768
+       lwle    $19,-2147483648($20)
+       lwle    $21,-2147483648
+       lwle    $22,2147483647($23)
+       lwle    $24,2147483647
+       lwle    $25,($26)
+       lwle    $27,MYDATA
+       lwre    $28,-256($29)
+       lwre    $30,-256
+       lwre    $31,255($0)
+       lwre    $2,255
+       lwre    $3,-257($4)
+       lwre    $5,-257
+       lwre    $6,256($7)
+       lwre    $8,256
+       lwre    $9,-512($10)
+       lwre    $11,-512
+       lwre    $12,511($13)
+       lwre    $14,511
+       lwre    $15,-1024($16)
+       lwre    $17,-1024
+       lwre    $18,1023($19)
+       lwre    $20,1023
+       lwre    $21,-2048($22)
+       lwre    $23,-2048
+       lwre    $24,2047($25)
+       lwre    $26,2047
+       lwre    $27,-4096($28)
+       lwre    $29,-4096
+       lwre    $30,4095($31)
+       lwre    $0,4095
+       lwre    $2,-32768($3)
+       lwre    $4,-32768
+       lwre    $5,32767($6)
+       lwre    $7,32767
+       lwre    $8,-32769($9)
+       lwre    $10,-32769
+       lwre    $11,32768($12)
+       lwre    $13,32768
+       lwre    $14,-2147483648($15)
+       lwre    $16,-2147483648
+       lwre    $17,2147483647($18)
+       lwre    $19,2147483647
+       lwre    $20,($21)
+       lwre    $22,MYDATA
+       sbe     $23,-256($24)
+       sbe     $25,-256
+       sbe     $26,255($27)
+       sbe     $28,255
+       sbe     $29,-257($30)
+       sbe     $31,-257
+       sbe     $0,256($2)
+       sbe     $3,256
+       sbe     $4,-512($5)
+       sbe     $6,-512
+       sbe     $7,511($8)
+       sbe     $9,511
+       sbe     $10,-1024($11)
+       sbe     $12,-1024
+       sbe     $13,1023($14)
+       sbe     $15,1023
+       sbe     $16,-2048($17)
+       sbe     $18,-2048
+       sbe     $19,2047($20)
+       sbe     $21,2047
+       sbe     $22,-4096($23)
+       sbe     $24,-4096
+       sbe     $25,4095($26)
+       sbe     $27,4095
+       sbe     $28,-32768($29)
+       sbe     $30,-32768
+       sbe     $31,32767($0)
+       sbe     $2,32767
+       sbe     $3,-32769($4)
+       sbe     $5,-32769
+       sbe     $6,32768($7)
+       sbe     $8,32768
+       sbe     $9,-2147483648($10)
+       sbe     $11,-2147483648
+       sbe     $12,2147483647($13)
+       sbe     $14,2147483647
+       sbe     $15,($16)
+       sbe     $17,MYDATA
+       sce     $18,-256($19)
+       sce     $20,-256
+       sce     $21,255($22)
+       sce     $23,255
+       sce     $24,-257($25)
+       sce     $26,-257
+       sce     $27,256($28)
+       sce     $29,256
+       sce     $30,-512($31)
+       sce     $0,-512
+       sce     $2,511($3)
+       sce     $4,511
+       sce     $5,-1024($6)
+       sce     $7,-1024
+       sce     $8,1023($9)
+       sce     $10,1023
+       sce     $11,-2048($12)
+       sce     $13,-2048
+       sce     $14,2047($15)
+       sce     $16,2047
+       sce     $17,-4096($18)
+       sce     $19,-4096
+       sce     $20,4095($21)
+       sce     $22,4095
+       sce     $23,-32768($24)
+       sce     $25,-32768
+       sce     $26,32767($27)
+       sce     $28,32767
+       sce     $29,-32769($30)
+       sce     $31,-32769
+       sce     $0,32768($2)
+       sce     $3,32768
+       sce     $4,-2147483648($5)
+       sce     $6,-2147483648
+       sce     $7,2147483647($8)
+       sce     $9,2147483647
+       sce     $10,($11)
+       sce     $12,MYDATA
+       she     $13,-256($14)
+       she     $15,-256
+       she     $16,255($17)
+       she     $18,255
+       she     $19,-257($20)
+       she     $21,-257
+       she     $22,256($23)
+       she     $24,256
+       she     $25,-512($26)
+       she     $27,-512
+       she     $28,511($29)
+       she     $30,511
+       she     $31,-1024($0)
+       she     $2,-1024
+       she     $3,1023($4)
+       she     $5,1023
+       she     $6,-2048($7)
+       she     $8,-2048
+       she     $9,2047($10)
+       she     $11,2047
+       she     $12,-4096($13)
+       she     $14,-4096
+       she     $15,4095($16)
+       she     $17,4095
+       she     $18,-32768($19)
+       she     $20,-32768
+       she     $21,32767($22)
+       she     $23,32767
+       she     $24,-32769($25)
+       she     $26,-32769
+       she     $27,32768($28)
+       she     $29,32768
+       she     $30,-2147483648($31)
+       she     $0,-2147483648
+       she     $2,2147483647($3)
+       she     $4,2147483647
+       she     $5,($6)
+       she     $7,MYDATA
+       swe     $8,-256($9)
+       swe     $10,-256
+       swe     $11,255($12)
+       swe     $13,255
+       swe     $14,-257($15)
+       swe     $16,-257
+       swe     $17,256($18)
+       swe     $19,256
+       swe     $20,-512($21)
+       swe     $22,-512
+       swe     $23,511($24)
+       swe     $25,511
+       swe     $26,-1024($27)
+       swe     $28,-1024
+       swe     $29,1023($30)
+       swe     $31,1023
+       swe     $0,-2048($2)
+       swe     $3,-2048
+       swe     $4,2047($5)
+       swe     $6,2047
+       swe     $7,-4096($8)
+       swe     $9,-4096
+       swe     $10,4095($11)
+       swe     $12,4095
+       swe     $13,-32768($14)
+       swe     $15,-32768
+       swe     $16,32767($17)
+       swe     $18,32767
+       swe     $19,-32769($20)
+       swe     $21,-32769
+       swe     $22,32768($23)
+       swe     $24,32768
+       swe     $25,-2147483648($26)
+       swe     $27,-2147483648
+       swe     $28,2147483647($29)
+       swe     $30,2147483647
+       swe     $31,($0)
+       swe     $2,MYDATA
+       swle    $3,-256($4)
+       swle    $5,-256
+       swle    $6,255($7)
+       swle    $8,255
+       swle    $9,-257($10)
+       swle    $11,-257
+       swle    $12,256($13)
+       swle    $14,256
+       swle    $15,-512($16)
+       swle    $17,-512
+       swle    $18,511($19)
+       swle    $20,511
+       swle    $21,-1024($22)
+       swle    $23,-1024
+       swle    $24,1023($25)
+       swle    $26,1023
+       swle    $27,-2048($28)
+       swle    $29,-2048
+       swle    $30,2047($31)
+       swle    $0,2047
+       swle    $2,-4096($3)
+       swle    $4,-4096
+       swle    $5,4095($6)
+       swle    $7,4095
+       swle    $8,-32768($9)
+       swle    $10,-32768
+       swle    $11,32767($12)
+       swle    $13,32767
+       swle    $14,-32769($15)
+       swle    $16,-32769
+       swle    $17,32768($18)
+       swle    $19,32768
+       swle    $20,-2147483648($21)
+       swle    $22,-2147483648
+       swle    $23,2147483647($24)
+       swle    $25,2147483647
+       swle    $26,($27)
+       swle    $28,MYDATA
+       swre    $29,-256($30)
+       swre    $31,-256
+       swre    $0,255($2)
+       swre    $3,255
+       swre    $4,-257($5)
+       swre    $6,-257
+       swre    $7,256($8)
+       swre    $9,256
+       swre    $10,-512($11)
+       swre    $12,-512
+       swre    $13,511($14)
+       swre    $15,511
+       swre    $16,-1024($17)
+       swre    $18,-1024
+       swre    $19,1023($20)
+       swre    $21,1023
+       swre    $22,-2048($23)
+       swre    $24,-2048
+       swre    $25,2047($26)
+       swre    $27,2047
+       swre    $28,-4096($29)
+       swre    $30,-4096
+       swre    $31,4095($0)
+       swre    $2,4095
+       swre    $3,-32768($4)
+       swre    $5,-32768
+       swre    $6,32767($7)
+       swre    $8,32767
+       swre    $9,-32769($10)
+       swre    $11,-32769
+       swre    $12,32768($13)
+       swre    $14,32768
+       swre    $15,-2147483648($16)
+       swre    $17,-2147483648
+       swre    $18,2147483647($19)
+       swre    $20,2147483647
+       swre    $21,($22)
+       swre    $23,MYDATA
+       cachee  24,-256($25)
+       cachee  26,-256
+       cachee  27,255($28)
+       cachee  29,255
+       cachee  30,-257($31)
+       cachee  0,-257
+       cachee  2,256($3)
+       cachee  4,256
+       cachee  5,-512($6)
+       cachee  7,-512
+       cachee  8,511($9)
+       cachee  10,511
+       cachee  11,-1024($12)
+       cachee  13,-1024
+       cachee  14,1023($15)
+       cachee  16,1023
+       cachee  17,-2048($18)
+       cachee  19,-2048
+       cachee  20,2047($21)
+       cachee  22,2047
+       cachee  23,-4096($24)
+       cachee  25,-4096
+       cachee  26,4095($27)
+       cachee  28,4095
+       cachee  29,-32768($30)
+       cachee  31,-32768
+       cachee  0,32767($2)
+       cachee  3,32767
+       cachee  4,-32769($5)
+       cachee  6,-32769
+       cachee  7,32768($8)
+       cachee  9,32768
+       cachee  10,-2147483648($11)
+       cachee  12,-2147483648
+       cachee  13,2147483647($14)
+       cachee  15,2147483647
+       cachee  16,($17)
+       cachee  18,MYDATA
+       prefe   19,-256($20)
+       prefe   21,-256
+       prefe   22,255($23)
+       prefe   24,255
+       prefe   25,-257($26)
+       prefe   27,-257
+       prefe   28,256($29)
+       prefe   30,256
+       prefe   31,-512($0)
+       prefe   2,-512
+       prefe   3,511($4)
+       prefe   5,511
+       prefe   6,-1024($7)
+       prefe   8,-1024
+       prefe   9,1023($10)
+       prefe   11,1023
+       prefe   12,-2048($13)
+       prefe   14,-2048
+       prefe   15,2047($16)
+       prefe   17,2047
+       prefe   18,-4096($19)
+       prefe   20,-4096
+       prefe   21,4095($22)
+       prefe   23,4095
+       prefe   24,-32768($25)
+       prefe   26,-32768
+       prefe   27,32767($28)
+       prefe   29,32767
+       prefe   30,-32769($31)
+       prefe   0,-32769
+       prefe   2,32768($3)
+       prefe   4,32768
+       prefe   5,-2147483648($6)
+       prefe   7,-2147483648
+       prefe   8,2147483647($9)
+       prefe   10,2147483647
+       prefe   11,($12)
+       prefe   13,MYDATA

diff --git a/gas/testsuite/gas/mips/micromips@eva.d b/gas/testsuite/gas/mips/micromips@eva.d
new file mode 100644 (file)
index 0000000..4c34ec3
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips@eva.d
@@ -0,0 +1,1441 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: microMIPS EVA 
+#as: -meva -32
+#source: eva.s
+
+.*: +file format .*mips.*
+
+
+Disassembly of section .text:
+0+0000 <[^>]*> 6002 6100       lbue    zero,-256\(v0\)
+0+0004 <[^>]*> 6060 6100       lbue    v1,-256\(zero\)
+0+0008 <[^>]*> 6085 60ff       lbue    a0,255\(a1\)
+0+000c <[^>]*> 60c0 60ff       lbue    a2,255\(zero\)
+0+0010 <[^>]*> 3020 fe00       li      at,-512
+0+0014 <[^>]*> 0101 0950       addu    at,at,t0
+0+0018 <[^>]*> 60e1 60ff       lbue    a3,255\(at\)
+0+001c <[^>]*> 3020 fe00       li      at,-512
+0+0020 <[^>]*> 6121 60ff       lbue    t1,255\(at\)
+0+0024 <[^>]*> 3020 0200       li      at,512
+0+0028 <[^>]*> 0161 0950       addu    at,at,t3
+0+002c <[^>]*> 6141 6100       lbue    t2,-256\(at\)
+0+0030 <[^>]*> 3020 0200       li      at,512
+0+0034 <[^>]*> 6181 6100       lbue    t4,-256\(at\)
+0+0038 <[^>]*> 3020 fe00       li      at,-512
+0+003c <[^>]*> 01c1 0950       addu    at,at,t6
+0+0040 <[^>]*> 61a1 6000       lbue    t5,0\(at\)
+0+0044 <[^>]*> 3020 fe00       li      at,-512
+0+0048 <[^>]*> 61e1 6000       lbue    t7,0\(at\)
+0+004c <[^>]*> 3020 0200       li      at,512
+0+0050 <[^>]*> 0221 0950       addu    at,at,s1
+0+0054 <[^>]*> 6201 61ff       lbue    s0,-1\(at\)
+0+0058 <[^>]*> 3020 0200       li      at,512
+0+005c <[^>]*> 6241 61ff       lbue    s2,-1\(at\)
+0+0060 <[^>]*> 3020 fc00       li      at,-1024
+0+0064 <[^>]*> 0281 0950       addu    at,at,s4
+0+0068 <[^>]*> 6261 6000       lbue    s3,0\(at\)
+0+006c <[^>]*> 3020 fc00       li      at,-1024
+0+0070 <[^>]*> 62a1 6000       lbue    s5,0\(at\)
+0+0074 <[^>]*> 3020 0400       li      at,1024
+0+0078 <[^>]*> 02e1 0950       addu    at,at,s7
+0+007c <[^>]*> 62c1 61ff       lbue    s6,-1\(at\)
+0+0080 <[^>]*> 3020 0400       li      at,1024
+0+0084 <[^>]*> 6301 61ff       lbue    t8,-1\(at\)
+0+0088 <[^>]*> 3020 f800       li      at,-2048
+0+008c <[^>]*> 0341 0950       addu    at,at,k0
+0+0090 <[^>]*> 6321 6000       lbue    t9,0\(at\)
+0+0094 <[^>]*> 3020 f800       li      at,-2048
+0+0098 <[^>]*> 6361 6000       lbue    k1,0\(at\)
+0+009c <[^>]*> 3020 0800       li      at,2048
+0+00a0 <[^>]*> 03a1 0950       addu    at,at,sp
+0+00a4 <[^>]*> 6381 61ff       lbue    gp,-1\(at\)
+0+00a8 <[^>]*> 3020 0800       li      at,2048
+0+00ac <[^>]*> 63c1 61ff       lbue    s8,-1\(at\)
+0+00b0 <[^>]*> 3020 f000       li      at,-4096
+0+00b4 <[^>]*> 63e1 6000       lbue    ra,0\(at\)
+0+00b8 <[^>]*> 3020 f000       li      at,-4096
+0+00bc <[^>]*> 6041 6000       lbue    v0,0\(at\)
+0+00c0 <[^>]*> 3020 1000       li      at,4096
+0+00c4 <[^>]*> 0081 0950       addu    at,at,a0
+0+00c8 <[^>]*> 6061 61ff       lbue    v1,-1\(at\)
+0+00cc <[^>]*> 3020 1000       li      at,4096
+0+00d0 <[^>]*> 60a1 61ff       lbue    a1,-1\(at\)
+0+00d4 <[^>]*> 3020 8000       li      at,-32768
+0+00d8 <[^>]*> 00e1 0950       addu    at,at,a3
+0+00dc <[^>]*> 60c1 6000       lbue    a2,0\(at\)
+0+00e0 <[^>]*> 3020 8000       li      at,-32768
+0+00e4 <[^>]*> 6101 6000       lbue    t0,0\(at\)
+0+00e8 <[^>]*> 5020 8000       li      at,0x8000
+0+00ec <[^>]*> 0141 0950       addu    at,at,t2
+0+00f0 <[^>]*> 6121 61ff       lbue    t1,-1\(at\)
+0+00f4 <[^>]*> 5020 8000       li      at,0x8000
+0+00f8 <[^>]*> 6161 61ff       lbue    t3,-1\(at\)
+0+00fc <[^>]*> 3020 8000       li      at,-32768
+0+0100 <[^>]*> 01a1 0950       addu    at,at,t5
+0+0104 <[^>]*> 6181 61ff       lbue    t4,-1\(at\)
+0+0108 <[^>]*> 3020 8000       li      at,-32768
+0+010c <[^>]*> 61c1 61ff       lbue    t6,-1\(at\)
+0+0110 <[^>]*> 5020 8000       li      at,0x8000
+0+0114 <[^>]*> 0201 0950       addu    at,at,s0
+0+0118 <[^>]*> 61e1 6000       lbue    t7,0\(at\)
+0+011c <[^>]*> 5020 8000       li      at,0x8000
+0+0120 <[^>]*> 6221 6000       lbue    s1,0\(at\)
+0+0124 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0128 <[^>]*> 0261 0950       addu    at,at,s3
+0+012c <[^>]*> 6241 6000       lbue    s2,0\(at\)
+0+0130 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0134 <[^>]*> 6281 6000       lbue    s4,0\(at\)
+0+0138 <[^>]*> 41a1 8000       lui     at,0x8000
+0+013c <[^>]*> 02c1 0950       addu    at,at,s6
+0+0140 <[^>]*> 62a1 61ff       lbue    s5,-1\(at\)
+0+0144 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0148 <[^>]*> 62e1 61ff       lbue    s7,-1\(at\)
+0+014c <[^>]*> 6319 6000       lbue    t8,0\(t9\)
+0+0150 <[^>]*> 41a1 0000       lui     at,0x0
+                       150: R_MICROMIPS_HI16   MYDATA
+0+0154 <[^>]*> 3021 0000       addiu   at,at,0
+                       154: R_MICROMIPS_LO16   MYDATA
+0+0158 <[^>]*> 6341 6000       lbue    k0,0\(at\)
+0+015c <[^>]*> 637c 6300       lhue    k1,-256\(gp\)
+0+0160 <[^>]*> 63a0 6300       lhue    sp,-256\(zero\)
+0+0164 <[^>]*> 63df 62ff       lhue    s8,255\(ra\)
+0+0168 <[^>]*> 6000 62ff       lhue    zero,255\(zero\)
+0+016c <[^>]*> 3020 fe00       li      at,-512
+0+0170 <[^>]*> 0061 0950       addu    at,at,v1
+0+0174 <[^>]*> 6041 62ff       lhue    v0,255\(at\)
+0+0178 <[^>]*> 3020 fe00       li      at,-512
+0+017c <[^>]*> 6081 62ff       lhue    a0,255\(at\)
+0+0180 <[^>]*> 3020 0200       li      at,512
+0+0184 <[^>]*> 00c1 0950       addu    at,at,a2
+0+0188 <[^>]*> 60a1 6300       lhue    a1,-256\(at\)
+0+018c <[^>]*> 3020 0200       li      at,512
+0+0190 <[^>]*> 60e1 6300       lhue    a3,-256\(at\)
+0+0194 <[^>]*> 3020 fe00       li      at,-512
+0+0198 <[^>]*> 0121 0950       addu    at,at,t1
+0+019c <[^>]*> 6101 6200       lhue    t0,0\(at\)
+0+01a0 <[^>]*> 3020 fe00       li      at,-512
+0+01a4 <[^>]*> 6141 6200       lhue    t2,0\(at\)
+0+01a8 <[^>]*> 3020 0200       li      at,512
+0+01ac <[^>]*> 0181 0950       addu    at,at,t4
+0+01b0 <[^>]*> 6161 63ff       lhue    t3,-1\(at\)
+0+01b4 <[^>]*> 3020 0200       li      at,512
+0+01b8 <[^>]*> 61a1 63ff       lhue    t5,-1\(at\)
+0+01bc <[^>]*> 3020 fc00       li      at,-1024
+0+01c0 <[^>]*> 01e1 0950       addu    at,at,t7
+0+01c4 <[^>]*> 61c1 6200       lhue    t6,0\(at\)
+0+01c8 <[^>]*> 3020 fc00       li      at,-1024
+0+01cc <[^>]*> 6201 6200       lhue    s0,0\(at\)
+0+01d0 <[^>]*> 3020 0400       li      at,1024
+0+01d4 <[^>]*> 0241 0950       addu    at,at,s2
+0+01d8 <[^>]*> 6221 63ff       lhue    s1,-1\(at\)
+0+01dc <[^>]*> 3020 0400       li      at,1024
+0+01e0 <[^>]*> 6261 63ff       lhue    s3,-1\(at\)
+0+01e4 <[^>]*> 3020 f800       li      at,-2048
+0+01e8 <[^>]*> 02a1 0950       addu    at,at,s5
+0+01ec <[^>]*> 6281 6200       lhue    s4,0\(at\)
+0+01f0 <[^>]*> 3020 f800       li      at,-2048
+0+01f4 <[^>]*> 62c1 6200       lhue    s6,0\(at\)
+0+01f8 <[^>]*> 3020 0800       li      at,2048
+0+01fc <[^>]*> 0301 0950       addu    at,at,t8
+0+0200 <[^>]*> 62e1 63ff       lhue    s7,-1\(at\)
+0+0204 <[^>]*> 3020 0800       li      at,2048
+0+0208 <[^>]*> 6321 63ff       lhue    t9,-1\(at\)
+0+020c <[^>]*> 3020 f000       li      at,-4096
+0+0210 <[^>]*> 0361 0950       addu    at,at,k1
+0+0214 <[^>]*> 6341 6200       lhue    k0,0\(at\)
+0+0218 <[^>]*> 3020 f000       li      at,-4096
+0+021c <[^>]*> 6381 6200       lhue    gp,0\(at\)
+0+0220 <[^>]*> 3020 1000       li      at,4096
+0+0224 <[^>]*> 03c1 0950       addu    at,at,s8
+0+0228 <[^>]*> 63a1 63ff       lhue    sp,-1\(at\)
+0+022c <[^>]*> 3020 1000       li      at,4096
+0+0230 <[^>]*> 63e1 63ff       lhue    ra,-1\(at\)
+0+0234 <[^>]*> 3020 8000       li      at,-32768
+0+0238 <[^>]*> 0041 0950       addu    at,at,v0
+0+023c <[^>]*> 6001 6200       lhue    zero,0\(at\)
+0+0240 <[^>]*> 3020 8000       li      at,-32768
+0+0244 <[^>]*> 6061 6200       lhue    v1,0\(at\)
+0+0248 <[^>]*> 5020 8000       li      at,0x8000
+0+024c <[^>]*> 00a1 0950       addu    at,at,a1
+0+0250 <[^>]*> 6081 63ff       lhue    a0,-1\(at\)
+0+0254 <[^>]*> 5020 8000       li      at,0x8000
+0+0258 <[^>]*> 60c1 63ff       lhue    a2,-1\(at\)
+0+025c <[^>]*> 3020 8000       li      at,-32768
+0+0260 <[^>]*> 0101 0950       addu    at,at,t0
+0+0264 <[^>]*> 60e1 63ff       lhue    a3,-1\(at\)
+0+0268 <[^>]*> 3020 8000       li      at,-32768
+0+026c <[^>]*> 6121 63ff       lhue    t1,-1\(at\)
+0+0270 <[^>]*> 5020 8000       li      at,0x8000
+0+0274 <[^>]*> 0161 0950       addu    at,at,t3
+0+0278 <[^>]*> 6141 6200       lhue    t2,0\(at\)
+0+027c <[^>]*> 5020 8000       li      at,0x8000
+0+0280 <[^>]*> 6181 6200       lhue    t4,0\(at\)
+0+0284 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0288 <[^>]*> 01c1 0950       addu    at,at,t6
+0+028c <[^>]*> 61a1 6200       lhue    t5,0\(at\)
+0+0290 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0294 <[^>]*> 61e1 6200       lhue    t7,0\(at\)
+0+0298 <[^>]*> 41a1 8000       lui     at,0x8000
+0+029c <[^>]*> 0221 0950       addu    at,at,s1
+0+02a0 <[^>]*> 6201 63ff       lhue    s0,-1\(at\)
+0+02a4 <[^>]*> 41a1 8000       lui     at,0x8000
+0+02a8 <[^>]*> 6241 63ff       lhue    s2,-1\(at\)
+0+02ac <[^>]*> 6274 6200       lhue    s3,0\(s4\)
+0+02b0 <[^>]*> 41a1 0000       lui     at,0x0
+                       2b0: R_MICROMIPS_HI16   MYDATA
+0+02b4 <[^>]*> 3021 0000       addiu   at,at,0
+                       2b4: R_MICROMIPS_LO16   MYDATA
+0+02b8 <[^>]*> 62a1 6200       lhue    s5,0\(at\)
+0+02bc <[^>]*> 62d7 6900       lbe     s6,-256\(s7\)
+0+02c0 <[^>]*> 6300 6900       lbe     t8,-256\(zero\)
+0+02c4 <[^>]*> 633a 68ff       lbe     t9,255\(k0\)
+0+02c8 <[^>]*> 6360 68ff       lbe     k1,255\(zero\)
+0+02cc <[^>]*> 3020 fe00       li      at,-512
+0+02d0 <[^>]*> 03a1 0950       addu    at,at,sp
+0+02d4 <[^>]*> 6381 68ff       lbe     gp,255\(at\)
+0+02d8 <[^>]*> 3020 fe00       li      at,-512
+0+02dc <[^>]*> 63c1 68ff       lbe     s8,255\(at\)
+0+02e0 <[^>]*> 3020 0200       li      at,512
+0+02e4 <[^>]*> 63e1 6900       lbe     ra,-256\(at\)
+0+02e8 <[^>]*> 3020 0200       li      at,512
+0+02ec <[^>]*> 6041 6900       lbe     v0,-256\(at\)
+0+02f0 <[^>]*> 3020 fe00       li      at,-512
+0+02f4 <[^>]*> 0081 0950       addu    at,at,a0
+0+02f8 <[^>]*> 6061 6800       lbe     v1,0\(at\)
+0+02fc <[^>]*> 3020 fe00       li      at,-512
+0+0300 <[^>]*> 60a1 6800       lbe     a1,0\(at\)
+0+0304 <[^>]*> 3020 0200       li      at,512
+0+0308 <[^>]*> 00e1 0950       addu    at,at,a3
+0+030c <[^>]*> 60c1 69ff       lbe     a2,-1\(at\)
+0+0310 <[^>]*> 3020 0200       li      at,512
+0+0314 <[^>]*> 6101 69ff       lbe     t0,-1\(at\)
+0+0318 <[^>]*> 3020 fc00       li      at,-1024
+0+031c <[^>]*> 0141 0950       addu    at,at,t2
+0+0320 <[^>]*> 6121 6800       lbe     t1,0\(at\)
+0+0324 <[^>]*> 3020 fc00       li      at,-1024
+0+0328 <[^>]*> 6161 6800       lbe     t3,0\(at\)
+0+032c <[^>]*> 3020 0400       li      at,1024
+0+0330 <[^>]*> 01a1 0950       addu    at,at,t5
+0+0334 <[^>]*> 6181 69ff       lbe     t4,-1\(at\)
+0+0338 <[^>]*> 3020 0400       li      at,1024
+0+033c <[^>]*> 61c1 69ff       lbe     t6,-1\(at\)
+0+0340 <[^>]*> 3020 f800       li      at,-2048
+0+0344 <[^>]*> 0201 0950       addu    at,at,s0
+0+0348 <[^>]*> 61e1 6800       lbe     t7,0\(at\)
+0+034c <[^>]*> 3020 f800       li      at,-2048
+0+0350 <[^>]*> 6221 6800       lbe     s1,0\(at\)
+0+0354 <[^>]*> 3020 0800       li      at,2048
+0+0358 <[^>]*> 0261 0950       addu    at,at,s3
+0+035c <[^>]*> 6241 69ff       lbe     s2,-1\(at\)
+0+0360 <[^>]*> 3020 0800       li      at,2048
+0+0364 <[^>]*> 6281 69ff       lbe     s4,-1\(at\)
+0+0368 <[^>]*> 3020 f000       li      at,-4096
+0+036c <[^>]*> 02c1 0950       addu    at,at,s6
+0+0370 <[^>]*> 62a1 6800       lbe     s5,0\(at\)
+0+0374 <[^>]*> 3020 f000       li      at,-4096
+0+0378 <[^>]*> 62e1 6800       lbe     s7,0\(at\)
+0+037c <[^>]*> 3020 1000       li      at,4096
+0+0380 <[^>]*> 0321 0950       addu    at,at,t9
+0+0384 <[^>]*> 6301 69ff       lbe     t8,-1\(at\)
+0+0388 <[^>]*> 3020 1000       li      at,4096
+0+038c <[^>]*> 6341 69ff       lbe     k0,-1\(at\)
+0+0390 <[^>]*> 3020 8000       li      at,-32768
+0+0394 <[^>]*> 0381 0950       addu    at,at,gp
+0+0398 <[^>]*> 6361 6800       lbe     k1,0\(at\)
+0+039c <[^>]*> 3020 8000       li      at,-32768
+0+03a0 <[^>]*> 63a1 6800       lbe     sp,0\(at\)
+0+03a4 <[^>]*> 5020 8000       li      at,0x8000
+0+03a8 <[^>]*> 03e1 0950       addu    at,at,ra
+0+03ac <[^>]*> 63c1 69ff       lbe     s8,-1\(at\)
+0+03b0 <[^>]*> 5020 8000       li      at,0x8000
+0+03b4 <[^>]*> 6001 69ff       lbe     zero,-1\(at\)
+0+03b8 <[^>]*> 3020 8000       li      at,-32768
+0+03bc <[^>]*> 0061 0950       addu    at,at,v1
+0+03c0 <[^>]*> 6041 69ff       lbe     v0,-1\(at\)
+0+03c4 <[^>]*> 3020 8000       li      at,-32768
+0+03c8 <[^>]*> 6081 69ff       lbe     a0,-1\(at\)
+0+03cc <[^>]*> 5020 8000       li      at,0x8000
+0+03d0 <[^>]*> 00c1 0950       addu    at,at,a2
+0+03d4 <[^>]*> 60a1 6800       lbe     a1,0\(at\)
+0+03d8 <[^>]*> 5020 8000       li      at,0x8000
+0+03dc <[^>]*> 60e1 6800       lbe     a3,0\(at\)
+0+03e0 <[^>]*> 41a1 8000       lui     at,0x8000
+0+03e4 <[^>]*> 0121 0950       addu    at,at,t1
+0+03e8 <[^>]*> 6101 6800       lbe     t0,0\(at\)
+0+03ec <[^>]*> 41a1 8000       lui     at,0x8000
+0+03f0 <[^>]*> 6141 6800       lbe     t2,0\(at\)
+0+03f4 <[^>]*> 41a1 8000       lui     at,0x8000
+0+03f8 <[^>]*> 0181 0950       addu    at,at,t4
+0+03fc <[^>]*> 6161 69ff       lbe     t3,-1\(at\)
+0+0400 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0404 <[^>]*> 61a1 69ff       lbe     t5,-1\(at\)
+0+0408 <[^>]*> 61cf 6800       lbe     t6,0\(t7\)
+0+040c <[^>]*> 41a1 0000       lui     at,0x0
+                       40c: R_MICROMIPS_HI16   MYDATA
+0+0410 <[^>]*> 3021 0000       addiu   at,at,0
+                       410: R_MICROMIPS_LO16   MYDATA
+0+0414 <[^>]*> 6201 6800       lbe     s0,0\(at\)
+0+0418 <[^>]*> 6232 6b00       lhe     s1,-256\(s2\)
+0+041c <[^>]*> 6260 6b00       lhe     s3,-256\(zero\)
+0+0420 <[^>]*> 6295 6aff       lhe     s4,255\(s5\)
+0+0424 <[^>]*> 62c0 6aff       lhe     s6,255\(zero\)
+0+0428 <[^>]*> 3020 fe00       li      at,-512
+0+042c <[^>]*> 0301 0950       addu    at,at,t8
+0+0430 <[^>]*> 62e1 6aff       lhe     s7,255\(at\)
+0+0434 <[^>]*> 3020 fe00       li      at,-512
+0+0438 <[^>]*> 6321 6aff       lhe     t9,255\(at\)
+0+043c <[^>]*> 3020 0200       li      at,512
+0+0440 <[^>]*> 0361 0950       addu    at,at,k1
+0+0444 <[^>]*> 6341 6b00       lhe     k0,-256\(at\)
+0+0448 <[^>]*> 3020 0200       li      at,512
+0+044c <[^>]*> 6381 6b00       lhe     gp,-256\(at\)
+0+0450 <[^>]*> 3020 fe00       li      at,-512
+0+0454 <[^>]*> 03c1 0950       addu    at,at,s8
+0+0458 <[^>]*> 63a1 6a00       lhe     sp,0\(at\)
+0+045c <[^>]*> 3020 fe00       li      at,-512
+0+0460 <[^>]*> 63e1 6a00       lhe     ra,0\(at\)
+0+0464 <[^>]*> 3020 0200       li      at,512
+0+0468 <[^>]*> 0041 0950       addu    at,at,v0
+0+046c <[^>]*> 6001 6bff       lhe     zero,-1\(at\)
+0+0470 <[^>]*> 3020 0200       li      at,512
+0+0474 <[^>]*> 6061 6bff       lhe     v1,-1\(at\)
+0+0478 <[^>]*> 3020 fc00       li      at,-1024
+0+047c <[^>]*> 00a1 0950       addu    at,at,a1
+0+0480 <[^>]*> 6081 6a00       lhe     a0,0\(at\)
+0+0484 <[^>]*> 3020 fc00       li      at,-1024
+0+0488 <[^>]*> 60c1 6a00       lhe     a2,0\(at\)
+0+048c <[^>]*> 3020 0400       li      at,1024
+0+0490 <[^>]*> 0101 0950       addu    at,at,t0
+0+0494 <[^>]*> 60e1 6bff       lhe     a3,-1\(at\)
+0+0498 <[^>]*> 3020 0400       li      at,1024
+0+049c <[^>]*> 6121 6bff       lhe     t1,-1\(at\)
+0+04a0 <[^>]*> 3020 f800       li      at,-2048
+0+04a4 <[^>]*> 0161 0950       addu    at,at,t3
+0+04a8 <[^>]*> 6141 6a00       lhe     t2,0\(at\)
+0+04ac <[^>]*> 3020 f800       li      at,-2048
+0+04b0 <[^>]*> 6181 6a00       lhe     t4,0\(at\)
+0+04b4 <[^>]*> 3020 0800       li      at,2048
+0+04b8 <[^>]*> 01c1 0950       addu    at,at,t6
+0+04bc <[^>]*> 61a1 6bff       lhe     t5,-1\(at\)
+0+04c0 <[^>]*> 3020 0800       li      at,2048
+0+04c4 <[^>]*> 61e1 6bff       lhe     t7,-1\(at\)
+0+04c8 <[^>]*> 3020 f000       li      at,-4096
+0+04cc <[^>]*> 0221 0950       addu    at,at,s1
+0+04d0 <[^>]*> 6201 6a00       lhe     s0,0\(at\)
+0+04d4 <[^>]*> 3020 f000       li      at,-4096
+0+04d8 <[^>]*> 6241 6a00       lhe     s2,0\(at\)
+0+04dc <[^>]*> 3020 1000       li      at,4096
+0+04e0 <[^>]*> 0281 0950       addu    at,at,s4
+0+04e4 <[^>]*> 6261 6bff       lhe     s3,-1\(at\)
+0+04e8 <[^>]*> 3020 1000       li      at,4096
+0+04ec <[^>]*> 62a1 6bff       lhe     s5,-1\(at\)
+0+04f0 <[^>]*> 3020 8000       li      at,-32768
+0+04f4 <[^>]*> 02e1 0950       addu    at,at,s7
+0+04f8 <[^>]*> 62c1 6a00       lhe     s6,0\(at\)
+0+04fc <[^>]*> 3020 8000       li      at,-32768
+0+0500 <[^>]*> 6301 6a00       lhe     t8,0\(at\)
+0+0504 <[^>]*> 5020 8000       li      at,0x8000
+0+0508 <[^>]*> 0341 0950       addu    at,at,k0
+0+050c <[^>]*> 6321 6bff       lhe     t9,-1\(at\)
+0+0510 <[^>]*> 5020 8000       li      at,0x8000
+0+0514 <[^>]*> 6361 6bff       lhe     k1,-1\(at\)
+0+0518 <[^>]*> 3020 8000       li      at,-32768
+0+051c <[^>]*> 03a1 0950       addu    at,at,sp
+0+0520 <[^>]*> 6381 6bff       lhe     gp,-1\(at\)
+0+0524 <[^>]*> 3020 8000       li      at,-32768
+0+0528 <[^>]*> 63c1 6bff       lhe     s8,-1\(at\)
+0+052c <[^>]*> 5020 8000       li      at,0x8000
+0+0530 <[^>]*> 63e1 6a00       lhe     ra,0\(at\)
+0+0534 <[^>]*> 5020 8000       li      at,0x8000
+0+0538 <[^>]*> 6041 6a00       lhe     v0,0\(at\)
+0+053c <[^>]*> 41a1 8000       lui     at,0x8000
+0+0540 <[^>]*> 0081 0950       addu    at,at,a0
+0+0544 <[^>]*> 6061 6a00       lhe     v1,0\(at\)
+0+0548 <[^>]*> 41a1 8000       lui     at,0x8000
+0+054c <[^>]*> 60a1 6a00       lhe     a1,0\(at\)
+0+0550 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0554 <[^>]*> 00e1 0950       addu    at,at,a3
+0+0558 <[^>]*> 60c1 6bff       lhe     a2,-1\(at\)
+0+055c <[^>]*> 41a1 8000       lui     at,0x8000
+0+0560 <[^>]*> 6101 6bff       lhe     t0,-1\(at\)
+0+0564 <[^>]*> 612a 6a00       lhe     t1,0\(t2\)
+0+0568 <[^>]*> 41a1 0000       lui     at,0x0
+                       568: R_MICROMIPS_HI16   MYDATA
+0+056c <[^>]*> 3021 0000       addiu   at,at,0
+                       56c: R_MICROMIPS_LO16   MYDATA
+0+0570 <[^>]*> 6161 6a00       lhe     t3,0\(at\)
+0+0574 <[^>]*> 618d 6d00       lle     t4,-256\(t5\)
+0+0578 <[^>]*> 61c0 6d00       lle     t6,-256\(zero\)
+0+057c <[^>]*> 61f0 6cff       lle     t7,255\(s0\)
+0+0580 <[^>]*> 6220 6cff       lle     s1,255\(zero\)
+0+0584 <[^>]*> 3020 fe00       li      at,-512
+0+0588 <[^>]*> 0261 0950       addu    at,at,s3
+0+058c <[^>]*> 6241 6cff       lle     s2,255\(at\)
+0+0590 <[^>]*> 3020 fe00       li      at,-512
+0+0594 <[^>]*> 6281 6cff       lle     s4,255\(at\)
+0+0598 <[^>]*> 3020 0200       li      at,512
+0+059c <[^>]*> 02c1 0950       addu    at,at,s6
+0+05a0 <[^>]*> 62a1 6d00       lle     s5,-256\(at\)
+0+05a4 <[^>]*> 3020 0200       li      at,512
+0+05a8 <[^>]*> 62e1 6d00       lle     s7,-256\(at\)
+0+05ac <[^>]*> 3020 fe00       li      at,-512
+0+05b0 <[^>]*> 0321 0950       addu    at,at,t9
+0+05b4 <[^>]*> 6301 6c00       lle     t8,0\(at\)
+0+05b8 <[^>]*> 3020 fe00       li      at,-512
+0+05bc <[^>]*> 6341 6c00       lle     k0,0\(at\)
+0+05c0 <[^>]*> 3020 0200       li      at,512
+0+05c4 <[^>]*> 0381 0950       addu    at,at,gp
+0+05c8 <[^>]*> 6361 6dff       lle     k1,-1\(at\)
+0+05cc <[^>]*> 3020 0200       li      at,512
+0+05d0 <[^>]*> 63a1 6dff       lle     sp,-1\(at\)
+0+05d4 <[^>]*> 3020 fc00       li      at,-1024
+0+05d8 <[^>]*> 03e1 0950       addu    at,at,ra
+0+05dc <[^>]*> 63c1 6c00       lle     s8,0\(at\)
+0+05e0 <[^>]*> 3020 fc00       li      at,-1024
+0+05e4 <[^>]*> 6001 6c00       lle     zero,0\(at\)
+0+05e8 <[^>]*> 3020 0400       li      at,1024
+0+05ec <[^>]*> 0061 0950       addu    at,at,v1
+0+05f0 <[^>]*> 6041 6dff       lle     v0,-1\(at\)
+0+05f4 <[^>]*> 3020 0400       li      at,1024
+0+05f8 <[^>]*> 6081 6dff       lle     a0,-1\(at\)
+0+05fc <[^>]*> 3020 f800       li      at,-2048
+0+0600 <[^>]*> 00c1 0950       addu    at,at,a2
+0+0604 <[^>]*> 60a1 6c00       lle     a1,0\(at\)
+0+0608 <[^>]*> 3020 f800       li      at,-2048
+0+060c <[^>]*> 60e1 6c00       lle     a3,0\(at\)
+0+0610 <[^>]*> 3020 0800       li      at,2048
+0+0614 <[^>]*> 0121 0950       addu    at,at,t1
+0+0618 <[^>]*> 6101 6dff       lle     t0,-1\(at\)
+0+061c <[^>]*> 3020 0800       li      at,2048
+0+0620 <[^>]*> 6141 6dff       lle     t2,-1\(at\)
+0+0624 <[^>]*> 3020 f000       li      at,-4096
+0+0628 <[^>]*> 0181 0950       addu    at,at,t4
+0+062c <[^>]*> 6161 6c00       lle     t3,0\(at\)
+0+0630 <[^>]*> 3020 f000       li      at,-4096
+0+0634 <[^>]*> 61a1 6c00       lle     t5,0\(at\)
+0+0638 <[^>]*> 3020 1000       li      at,4096
+0+063c <[^>]*> 01e1 0950       addu    at,at,t7
+0+0640 <[^>]*> 61c1 6dff       lle     t6,-1\(at\)
+0+0644 <[^>]*> 3020 1000       li      at,4096
+0+0648 <[^>]*> 6201 6dff       lle     s0,-1\(at\)
+0+064c <[^>]*> 3020 8000       li      at,-32768
+0+0650 <[^>]*> 0241 0950       addu    at,at,s2
+0+0654 <[^>]*> 6221 6c00       lle     s1,0\(at\)
+0+0658 <[^>]*> 3020 8000       li      at,-32768
+0+065c <[^>]*> 6261 6c00       lle     s3,0\(at\)
+0+0660 <[^>]*> 5020 8000       li      at,0x8000
+0+0664 <[^>]*> 02a1 0950       addu    at,at,s5
+0+0668 <[^>]*> 6281 6dff       lle     s4,-1\(at\)
+0+066c <[^>]*> 5020 8000       li      at,0x8000
+0+0670 <[^>]*> 62c1 6dff       lle     s6,-1\(at\)
+0+0674 <[^>]*> 3020 8000       li      at,-32768
+0+0678 <[^>]*> 0301 0950       addu    at,at,t8
+0+067c <[^>]*> 62e1 6dff       lle     s7,-1\(at\)
+0+0680 <[^>]*> 3020 8000       li      at,-32768
+0+0684 <[^>]*> 6321 6dff       lle     t9,-1\(at\)
+0+0688 <[^>]*> 5020 8000       li      at,0x8000
+0+068c <[^>]*> 0361 0950       addu    at,at,k1
+0+0690 <[^>]*> 6341 6c00       lle     k0,0\(at\)
+0+0694 <[^>]*> 5020 8000       li      at,0x8000
+0+0698 <[^>]*> 6381 6c00       lle     gp,0\(at\)
+0+069c <[^>]*> 41a1 8000       lui     at,0x8000
+0+06a0 <[^>]*> 03c1 0950       addu    at,at,s8
+0+06a4 <[^>]*> 63a1 6c00       lle     sp,0\(at\)
+0+06a8 <[^>]*> 41a1 8000       lui     at,0x8000
+0+06ac <[^>]*> 63e1 6c00       lle     ra,0\(at\)
+0+06b0 <[^>]*> 41a1 8000       lui     at,0x8000
+0+06b4 <[^>]*> 0041 0950       addu    at,at,v0
+0+06b8 <[^>]*> 6001 6dff       lle     zero,-1\(at\)
+0+06bc <[^>]*> 41a1 8000       lui     at,0x8000
+0+06c0 <[^>]*> 6061 6dff       lle     v1,-1\(at\)
+0+06c4 <[^>]*> 6085 6c00       lle     a0,0\(a1\)
+0+06c8 <[^>]*> 41a1 0000       lui     at,0x0
+                       6c8: R_MICROMIPS_HI16   MYDATA
+0+06cc <[^>]*> 3021 0000       addiu   at,at,0
+                       6cc: R_MICROMIPS_LO16   MYDATA
+0+06d0 <[^>]*> 60c1 6c00       lle     a2,0\(at\)
+0+06d4 <[^>]*> 60e8 6f00       lwe     a3,-256\(t0\)
+0+06d8 <[^>]*> 6120 6f00       lwe     t1,-256\(zero\)
+0+06dc <[^>]*> 614b 6eff       lwe     t2,255\(t3\)
+0+06e0 <[^>]*> 6180 6eff       lwe     t4,255\(zero\)
+0+06e4 <[^>]*> 3020 fe00       li      at,-512
+0+06e8 <[^>]*> 01c1 0950       addu    at,at,t6
+0+06ec <[^>]*> 61a1 6eff       lwe     t5,255\(at\)
+0+06f0 <[^>]*> 3020 fe00       li      at,-512
+0+06f4 <[^>]*> 61e1 6eff       lwe     t7,255\(at\)
+0+06f8 <[^>]*> 3020 0200       li      at,512
+0+06fc <[^>]*> 0221 0950       addu    at,at,s1
+0+0700 <[^>]*> 6201 6f00       lwe     s0,-256\(at\)
+0+0704 <[^>]*> 3020 0200       li      at,512
+0+0708 <[^>]*> 6241 6f00       lwe     s2,-256\(at\)
+0+070c <[^>]*> 3020 fe00       li      at,-512
+0+0710 <[^>]*> 0281 0950       addu    at,at,s4
+0+0714 <[^>]*> 6261 6e00       lwe     s3,0\(at\)
+0+0718 <[^>]*> 3020 fe00       li      at,-512
+0+071c <[^>]*> 62a1 6e00       lwe     s5,0\(at\)
+0+0720 <[^>]*> 3020 0200       li      at,512
+0+0724 <[^>]*> 02e1 0950       addu    at,at,s7
+0+0728 <[^>]*> 62c1 6fff       lwe     s6,-1\(at\)
+0+072c <[^>]*> 3020 0200       li      at,512
+0+0730 <[^>]*> 6301 6fff       lwe     t8,-1\(at\)
+0+0734 <[^>]*> 3020 fc00       li      at,-1024
+0+0738 <[^>]*> 0341 0950       addu    at,at,k0
+0+073c <[^>]*> 6321 6e00       lwe     t9,0\(at\)
+0+0740 <[^>]*> 3020 fc00       li      at,-1024
+0+0744 <[^>]*> 6361 6e00       lwe     k1,0\(at\)
+0+0748 <[^>]*> 3020 0400       li      at,1024
+0+074c <[^>]*> 03a1 0950       addu    at,at,sp
+0+0750 <[^>]*> 6381 6fff       lwe     gp,-1\(at\)
+0+0754 <[^>]*> 3020 0400       li      at,1024
+0+0758 <[^>]*> 63c1 6fff       lwe     s8,-1\(at\)
+0+075c <[^>]*> 3020 f800       li      at,-2048
+0+0760 <[^>]*> 63e1 6e00       lwe     ra,0\(at\)
+0+0764 <[^>]*> 3020 f800       li      at,-2048
+0+0768 <[^>]*> 6041 6e00       lwe     v0,0\(at\)
+0+076c <[^>]*> 3020 0800       li      at,2048
+0+0770 <[^>]*> 0081 0950       addu    at,at,a0
+0+0774 <[^>]*> 6061 6fff       lwe     v1,-1\(at\)
+0+0778 <[^>]*> 3020 0800       li      at,2048
+0+077c <[^>]*> 60a1 6fff       lwe     a1,-1\(at\)
+0+0780 <[^>]*> 3020 f000       li      at,-4096
+0+0784 <[^>]*> 00e1 0950       addu    at,at,a3
+0+0788 <[^>]*> 60c1 6e00       lwe     a2,0\(at\)
+0+078c <[^>]*> 3020 f000       li      at,-4096
+0+0790 <[^>]*> 6101 6e00       lwe     t0,0\(at\)
+0+0794 <[^>]*> 3020 1000       li      at,4096
+0+0798 <[^>]*> 0141 0950       addu    at,at,t2
+0+079c <[^>]*> 6121 6fff       lwe     t1,-1\(at\)
+0+07a0 <[^>]*> 3020 1000       li      at,4096
+0+07a4 <[^>]*> 6161 6fff       lwe     t3,-1\(at\)
+0+07a8 <[^>]*> 3020 8000       li      at,-32768
+0+07ac <[^>]*> 01a1 0950       addu    at,at,t5
+0+07b0 <[^>]*> 6181 6e00       lwe     t4,0\(at\)
+0+07b4 <[^>]*> 3020 8000       li      at,-32768
+0+07b8 <[^>]*> 61c1 6e00       lwe     t6,0\(at\)
+0+07bc <[^>]*> 5020 8000       li      at,0x8000
+0+07c0 <[^>]*> 0201 0950       addu    at,at,s0
+0+07c4 <[^>]*> 61e1 6fff       lwe     t7,-1\(at\)
+0+07c8 <[^>]*> 5020 8000       li      at,0x8000
+0+07cc <[^>]*> 6221 6fff       lwe     s1,-1\(at\)
+0+07d0 <[^>]*> 3020 8000       li      at,-32768
+0+07d4 <[^>]*> 0261 0950       addu    at,at,s3
+0+07d8 <[^>]*> 6241 6fff       lwe     s2,-1\(at\)
+0+07dc <[^>]*> 3020 8000       li      at,-32768
+0+07e0 <[^>]*> 6281 6fff       lwe     s4,-1\(at\)
+0+07e4 <[^>]*> 5020 8000       li      at,0x8000
+0+07e8 <[^>]*> 02c1 0950       addu    at,at,s6
+0+07ec <[^>]*> 62a1 6e00       lwe     s5,0\(at\)
+0+07f0 <[^>]*> 5020 8000       li      at,0x8000
+0+07f4 <[^>]*> 62e1 6e00       lwe     s7,0\(at\)
+0+07f8 <[^>]*> 41a1 8000       lui     at,0x8000
+0+07fc <[^>]*> 0321 0950       addu    at,at,t9
+0+0800 <[^>]*> 6301 6e00       lwe     t8,0\(at\)
+0+0804 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0808 <[^>]*> 6341 6e00       lwe     k0,0\(at\)
+0+080c <[^>]*> 41a1 8000       lui     at,0x8000
+0+0810 <[^>]*> 0381 0950       addu    at,at,gp
+0+0814 <[^>]*> 6361 6fff       lwe     k1,-1\(at\)
+0+0818 <[^>]*> 41a1 8000       lui     at,0x8000
+0+081c <[^>]*> 63a1 6fff       lwe     sp,-1\(at\)
+0+0820 <[^>]*> 63df 6e00       lwe     s8,0\(ra\)
+0+0824 <[^>]*> 41a1 0000       lui     at,0x0
+                       824: R_MICROMIPS_HI16   MYDATA
+0+0828 <[^>]*> 3021 0000       addiu   at,at,0
+                       828: R_MICROMIPS_LO16   MYDATA
+0+082c <[^>]*> 6001 6e00       lwe     zero,0\(at\)
+0+0830 <[^>]*> 6043 6500       lwle    v0,-256\(v1\)
+0+0834 <[^>]*> 6080 6500       lwle    a0,-256\(zero\)
+0+0838 <[^>]*> 60a6 64ff       lwle    a1,255\(a2\)
+0+083c <[^>]*> 60e0 64ff       lwle    a3,255\(zero\)
+0+0840 <[^>]*> 3020 fe00       li      at,-512
+0+0844 <[^>]*> 0121 0950       addu    at,at,t1
+0+0848 <[^>]*> 6101 64ff       lwle    t0,255\(at\)
+0+084c <[^>]*> 3020 fe00       li      at,-512
+0+0850 <[^>]*> 6141 64ff       lwle    t2,255\(at\)
+0+0854 <[^>]*> 3020 0200       li      at,512
+0+0858 <[^>]*> 0181 0950       addu    at,at,t4
+0+085c <[^>]*> 6161 6500       lwle    t3,-256\(at\)
+0+0860 <[^>]*> 3020 0200       li      at,512
+0+0864 <[^>]*> 61a1 6500       lwle    t5,-256\(at\)
+0+0868 <[^>]*> 3020 fe00       li      at,-512
+0+086c <[^>]*> 01e1 0950       addu    at,at,t7
+0+0870 <[^>]*> 61c1 6400       lwle    t6,0\(at\)
+0+0874 <[^>]*> 3020 fe00       li      at,-512
+0+0878 <[^>]*> 6201 6400       lwle    s0,0\(at\)
+0+087c <[^>]*> 3020 0200       li      at,512
+0+0880 <[^>]*> 0241 0950       addu    at,at,s2
+0+0884 <[^>]*> 6221 65ff       lwle    s1,-1\(at\)
+0+0888 <[^>]*> 3020 0200       li      at,512
+0+088c <[^>]*> 6261 65ff       lwle    s3,-1\(at\)
+0+0890 <[^>]*> 3020 fc00       li      at,-1024
+0+0894 <[^>]*> 02a1 0950       addu    at,at,s5
+0+0898 <[^>]*> 6281 6400       lwle    s4,0\(at\)
+0+089c <[^>]*> 3020 fc00       li      at,-1024
+0+08a0 <[^>]*> 62c1 6400       lwle    s6,0\(at\)
+0+08a4 <[^>]*> 3020 0400       li      at,1024
+0+08a8 <[^>]*> 0301 0950       addu    at,at,t8
+0+08ac <[^>]*> 62e1 65ff       lwle    s7,-1\(at\)
+0+08b0 <[^>]*> 3020 0400       li      at,1024
+0+08b4 <[^>]*> 6321 65ff       lwle    t9,-1\(at\)
+0+08b8 <[^>]*> 3020 f800       li      at,-2048
+0+08bc <[^>]*> 0361 0950       addu    at,at,k1
+0+08c0 <[^>]*> 6341 6400       lwle    k0,0\(at\)
+0+08c4 <[^>]*> 3020 f800       li      at,-2048
+0+08c8 <[^>]*> 6381 6400       lwle    gp,0\(at\)
+0+08cc <[^>]*> 3020 0800       li      at,2048
+0+08d0 <[^>]*> 03c1 0950       addu    at,at,s8
+0+08d4 <[^>]*> 63a1 65ff       lwle    sp,-1\(at\)
+0+08d8 <[^>]*> 3020 0800       li      at,2048
+0+08dc <[^>]*> 63e1 65ff       lwle    ra,-1\(at\)
+0+08e0 <[^>]*> 3020 f000       li      at,-4096
+0+08e4 <[^>]*> 0041 0950       addu    at,at,v0
+0+08e8 <[^>]*> 6001 6400       lwle    zero,0\(at\)
+0+08ec <[^>]*> 3020 f000       li      at,-4096
+0+08f0 <[^>]*> 6061 6400       lwle    v1,0\(at\)
+0+08f4 <[^>]*> 3020 1000       li      at,4096
+0+08f8 <[^>]*> 00a1 0950       addu    at,at,a1
+0+08fc <[^>]*> 6081 65ff       lwle    a0,-1\(at\)
+0+0900 <[^>]*> 3020 1000       li      at,4096
+0+0904 <[^>]*> 60c1 65ff       lwle    a2,-1\(at\)
+0+0908 <[^>]*> 3020 8000       li      at,-32768
+0+090c <[^>]*> 0101 0950       addu    at,at,t0
+0+0910 <[^>]*> 60e1 6400       lwle    a3,0\(at\)
+0+0914 <[^>]*> 3020 8000       li      at,-32768
+0+0918 <[^>]*> 6121 6400       lwle    t1,0\(at\)
+0+091c <[^>]*> 5020 8000       li      at,0x8000
+0+0920 <[^>]*> 0161 0950       addu    at,at,t3
+0+0924 <[^>]*> 6141 65ff       lwle    t2,-1\(at\)
+0+0928 <[^>]*> 5020 8000       li      at,0x8000
+0+092c <[^>]*> 6181 65ff       lwle    t4,-1\(at\)
+0+0930 <[^>]*> 3020 8000       li      at,-32768
+0+0934 <[^>]*> 01c1 0950       addu    at,at,t6
+0+0938 <[^>]*> 61a1 65ff       lwle    t5,-1\(at\)
+0+093c <[^>]*> 3020 8000       li      at,-32768
+0+0940 <[^>]*> 61e1 65ff       lwle    t7,-1\(at\)
+0+0944 <[^>]*> 5020 8000       li      at,0x8000
+0+0948 <[^>]*> 0221 0950       addu    at,at,s1
+0+094c <[^>]*> 6201 6400       lwle    s0,0\(at\)
+0+0950 <[^>]*> 5020 8000       li      at,0x8000
+0+0954 <[^>]*> 6241 6400       lwle    s2,0\(at\)
+0+0958 <[^>]*> 41a1 8000       lui     at,0x8000
+0+095c <[^>]*> 0281 0950       addu    at,at,s4
+0+0960 <[^>]*> 6261 6400       lwle    s3,0\(at\)
+0+0964 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0968 <[^>]*> 62a1 6400       lwle    s5,0\(at\)
+0+096c <[^>]*> 41a1 8000       lui     at,0x8000
+0+0970 <[^>]*> 02e1 0950       addu    at,at,s7
+0+0974 <[^>]*> 62c1 65ff       lwle    s6,-1\(at\)
+0+0978 <[^>]*> 41a1 8000       lui     at,0x8000
+0+097c <[^>]*> 6301 65ff       lwle    t8,-1\(at\)
+0+0980 <[^>]*> 633a 6400       lwle    t9,0\(k0\)
+0+0984 <[^>]*> 41a1 0000       lui     at,0x0
+                       984: R_MICROMIPS_HI16   MYDATA
+0+0988 <[^>]*> 3021 0000       addiu   at,at,0
+                       988: R_MICROMIPS_LO16   MYDATA
+0+098c <[^>]*> 6361 6400       lwle    k1,0\(at\)
+0+0990 <[^>]*> 639d 6700       lwre    gp,-256\(sp\)
+0+0994 <[^>]*> 63c0 6700       lwre    s8,-256\(zero\)
+0+0998 <[^>]*> 63e0 66ff       lwre    ra,255\(zero\)
+0+099c <[^>]*> 6040 66ff       lwre    v0,255\(zero\)
+0+09a0 <[^>]*> 3020 fe00       li      at,-512
+0+09a4 <[^>]*> 0081 0950       addu    at,at,a0
+0+09a8 <[^>]*> 6061 66ff       lwre    v1,255\(at\)
+0+09ac <[^>]*> 3020 fe00       li      at,-512
+0+09b0 <[^>]*> 60a1 66ff       lwre    a1,255\(at\)
+0+09b4 <[^>]*> 3020 0200       li      at,512
+0+09b8 <[^>]*> 00e1 0950       addu    at,at,a3
+0+09bc <[^>]*> 60c1 6700       lwre    a2,-256\(at\)
+0+09c0 <[^>]*> 3020 0200       li      at,512
+0+09c4 <[^>]*> 6101 6700       lwre    t0,-256\(at\)
+0+09c8 <[^>]*> 3020 fe00       li      at,-512
+0+09cc <[^>]*> 0141 0950       addu    at,at,t2
+0+09d0 <[^>]*> 6121 6600       lwre    t1,0\(at\)
+0+09d4 <[^>]*> 3020 fe00       li      at,-512
+0+09d8 <[^>]*> 6161 6600       lwre    t3,0\(at\)
+0+09dc <[^>]*> 3020 0200       li      at,512
+0+09e0 <[^>]*> 01a1 0950       addu    at,at,t5
+0+09e4 <[^>]*> 6181 67ff       lwre    t4,-1\(at\)
+0+09e8 <[^>]*> 3020 0200       li      at,512
+0+09ec <[^>]*> 61c1 67ff       lwre    t6,-1\(at\)
+0+09f0 <[^>]*> 3020 fc00       li      at,-1024
+0+09f4 <[^>]*> 0201 0950       addu    at,at,s0
+0+09f8 <[^>]*> 61e1 6600       lwre    t7,0\(at\)
+0+09fc <[^>]*> 3020 fc00       li      at,-1024
+0+0a00 <[^>]*> 6221 6600       lwre    s1,0\(at\)
+0+0a04 <[^>]*> 3020 0400       li      at,1024
+0+0a08 <[^>]*> 0261 0950       addu    at,at,s3
+0+0a0c <[^>]*> 6241 67ff       lwre    s2,-1\(at\)
+0+0a10 <[^>]*> 3020 0400       li      at,1024
+0+0a14 <[^>]*> 6281 67ff       lwre    s4,-1\(at\)
+0+0a18 <[^>]*> 3020 f800       li      at,-2048
+0+0a1c <[^>]*> 02c1 0950       addu    at,at,s6
+0+0a20 <[^>]*> 62a1 6600       lwre    s5,0\(at\)
+0+0a24 <[^>]*> 3020 f800       li      at,-2048
+0+0a28 <[^>]*> 62e1 6600       lwre    s7,0\(at\)
+0+0a2c <[^>]*> 3020 0800       li      at,2048
+0+0a30 <[^>]*> 0321 0950       addu    at,at,t9
+0+0a34 <[^>]*> 6301 67ff       lwre    t8,-1\(at\)
+0+0a38 <[^>]*> 3020 0800       li      at,2048
+0+0a3c <[^>]*> 6341 67ff       lwre    k0,-1\(at\)
+0+0a40 <[^>]*> 3020 f000       li      at,-4096
+0+0a44 <[^>]*> 0381 0950       addu    at,at,gp
+0+0a48 <[^>]*> 6361 6600       lwre    k1,0\(at\)
+0+0a4c <[^>]*> 3020 f000       li      at,-4096
+0+0a50 <[^>]*> 63a1 6600       lwre    sp,0\(at\)
+0+0a54 <[^>]*> 3020 1000       li      at,4096
+0+0a58 <[^>]*> 03e1 0950       addu    at,at,ra
+0+0a5c <[^>]*> 63c1 67ff       lwre    s8,-1\(at\)
+0+0a60 <[^>]*> 3020 1000       li      at,4096
+0+0a64 <[^>]*> 6001 67ff       lwre    zero,-1\(at\)
+0+0a68 <[^>]*> 3020 8000       li      at,-32768
+0+0a6c <[^>]*> 0061 0950       addu    at,at,v1
+0+0a70 <[^>]*> 6041 6600       lwre    v0,0\(at\)
+0+0a74 <[^>]*> 3020 8000       li      at,-32768
+0+0a78 <[^>]*> 6081 6600       lwre    a0,0\(at\)
+0+0a7c <[^>]*> 5020 8000       li      at,0x8000
+0+0a80 <[^>]*> 00c1 0950       addu    at,at,a2
+0+0a84 <[^>]*> 60a1 67ff       lwre    a1,-1\(at\)
+0+0a88 <[^>]*> 5020 8000       li      at,0x8000
+0+0a8c <[^>]*> 60e1 67ff       lwre    a3,-1\(at\)
+0+0a90 <[^>]*> 3020 8000       li      at,-32768
+0+0a94 <[^>]*> 0121 0950       addu    at,at,t1
+0+0a98 <[^>]*> 6101 67ff       lwre    t0,-1\(at\)
+0+0a9c <[^>]*> 3020 8000       li      at,-32768
+0+0aa0 <[^>]*> 6141 67ff       lwre    t2,-1\(at\)
+0+0aa4 <[^>]*> 5020 8000       li      at,0x8000
+0+0aa8 <[^>]*> 0181 0950       addu    at,at,t4
+0+0aac <[^>]*> 6161 6600       lwre    t3,0\(at\)
+0+0ab0 <[^>]*> 5020 8000       li      at,0x8000
+0+0ab4 <[^>]*> 61a1 6600       lwre    t5,0\(at\)
+0+0ab8 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0abc <[^>]*> 01e1 0950       addu    at,at,t7
+0+0ac0 <[^>]*> 61c1 6600       lwre    t6,0\(at\)
+0+0ac4 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0ac8 <[^>]*> 6201 6600       lwre    s0,0\(at\)
+0+0acc <[^>]*> 41a1 8000       lui     at,0x8000
+0+0ad0 <[^>]*> 0241 0950       addu    at,at,s2
+0+0ad4 <[^>]*> 6221 67ff       lwre    s1,-1\(at\)
+0+0ad8 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0adc <[^>]*> 6261 67ff       lwre    s3,-1\(at\)
+0+0ae0 <[^>]*> 6295 6600       lwre    s4,0\(s5\)
+0+0ae4 <[^>]*> 41a1 0000       lui     at,0x0
+                       ae4: R_MICROMIPS_HI16   MYDATA
+0+0ae8 <[^>]*> 3021 0000       addiu   at,at,0
+                       ae8: R_MICROMIPS_LO16   MYDATA
+0+0aec <[^>]*> 62c1 6600       lwre    s6,0\(at\)
+0+0af0 <[^>]*> 62f8 a900       sbe     s7,-256\(t8\)
+0+0af4 <[^>]*> 6320 a900       sbe     t9,-256\(zero\)
+0+0af8 <[^>]*> 635b a8ff       sbe     k0,255\(k1\)
+0+0afc <[^>]*> 6380 a8ff       sbe     gp,255\(zero\)
+0+0b00 <[^>]*> 3020 fe00       li      at,-512
+0+0b04 <[^>]*> 03c1 0950       addu    at,at,s8
+0+0b08 <[^>]*> 63a1 a8ff       sbe     sp,255\(at\)
+0+0b0c <[^>]*> 3020 fe00       li      at,-512
+0+0b10 <[^>]*> 63e1 a8ff       sbe     ra,255\(at\)
+0+0b14 <[^>]*> 3020 0200       li      at,512
+0+0b18 <[^>]*> 0041 0950       addu    at,at,v0
+0+0b1c <[^>]*> 6001 a900       sbe     zero,-256\(at\)
+0+0b20 <[^>]*> 3020 0200       li      at,512
+0+0b24 <[^>]*> 6061 a900       sbe     v1,-256\(at\)
+0+0b28 <[^>]*> 3020 fe00       li      at,-512
+0+0b2c <[^>]*> 00a1 0950       addu    at,at,a1
+0+0b30 <[^>]*> 6081 a800       sbe     a0,0\(at\)
+0+0b34 <[^>]*> 3020 fe00       li      at,-512
+0+0b38 <[^>]*> 60c1 a800       sbe     a2,0\(at\)
+0+0b3c <[^>]*> 3020 0200       li      at,512
+0+0b40 <[^>]*> 0101 0950       addu    at,at,t0
+0+0b44 <[^>]*> 60e1 a9ff       sbe     a3,-1\(at\)
+0+0b48 <[^>]*> 3020 0200       li      at,512
+0+0b4c <[^>]*> 6121 a9ff       sbe     t1,-1\(at\)
+0+0b50 <[^>]*> 3020 fc00       li      at,-1024
+0+0b54 <[^>]*> 0161 0950       addu    at,at,t3
+0+0b58 <[^>]*> 6141 a800       sbe     t2,0\(at\)
+0+0b5c <[^>]*> 3020 fc00       li      at,-1024
+0+0b60 <[^>]*> 6181 a800       sbe     t4,0\(at\)
+0+0b64 <[^>]*> 3020 0400       li      at,1024
+0+0b68 <[^>]*> 01c1 0950       addu    at,at,t6
+0+0b6c <[^>]*> 61a1 a9ff       sbe     t5,-1\(at\)
+0+0b70 <[^>]*> 3020 0400       li      at,1024
+0+0b74 <[^>]*> 61e1 a9ff       sbe     t7,-1\(at\)
+0+0b78 <[^>]*> 3020 f800       li      at,-2048
+0+0b7c <[^>]*> 0221 0950       addu    at,at,s1
+0+0b80 <[^>]*> 6201 a800       sbe     s0,0\(at\)
+0+0b84 <[^>]*> 3020 f800       li      at,-2048
+0+0b88 <[^>]*> 6241 a800       sbe     s2,0\(at\)
+0+0b8c <[^>]*> 3020 0800       li      at,2048
+0+0b90 <[^>]*> 0281 0950       addu    at,at,s4
+0+0b94 <[^>]*> 6261 a9ff       sbe     s3,-1\(at\)
+0+0b98 <[^>]*> 3020 0800       li      at,2048
+0+0b9c <[^>]*> 62a1 a9ff       sbe     s5,-1\(at\)
+0+0ba0 <[^>]*> 3020 f000       li      at,-4096
+0+0ba4 <[^>]*> 02e1 0950       addu    at,at,s7
+0+0ba8 <[^>]*> 62c1 a800       sbe     s6,0\(at\)
+0+0bac <[^>]*> 3020 f000       li      at,-4096
+0+0bb0 <[^>]*> 6301 a800       sbe     t8,0\(at\)
+0+0bb4 <[^>]*> 3020 1000       li      at,4096
+0+0bb8 <[^>]*> 0341 0950       addu    at,at,k0
+0+0bbc <[^>]*> 6321 a9ff       sbe     t9,-1\(at\)
+0+0bc0 <[^>]*> 3020 1000       li      at,4096
+0+0bc4 <[^>]*> 6361 a9ff       sbe     k1,-1\(at\)
+0+0bc8 <[^>]*> 3020 8000       li      at,-32768
+0+0bcc <[^>]*> 03a1 0950       addu    at,at,sp
+0+0bd0 <[^>]*> 6381 a800       sbe     gp,0\(at\)
+0+0bd4 <[^>]*> 3020 8000       li      at,-32768
+0+0bd8 <[^>]*> 63c1 a800       sbe     s8,0\(at\)
+0+0bdc <[^>]*> 5020 8000       li      at,0x8000
+0+0be0 <[^>]*> 63e1 a9ff       sbe     ra,-1\(at\)
+0+0be4 <[^>]*> 5020 8000       li      at,0x8000
+0+0be8 <[^>]*> 6041 a9ff       sbe     v0,-1\(at\)
+0+0bec <[^>]*> 3020 8000       li      at,-32768
+0+0bf0 <[^>]*> 0081 0950       addu    at,at,a0
+0+0bf4 <[^>]*> 6061 a9ff       sbe     v1,-1\(at\)
+0+0bf8 <[^>]*> 3020 8000       li      at,-32768
+0+0bfc <[^>]*> 60a1 a9ff       sbe     a1,-1\(at\)
+0+0c00 <[^>]*> 5020 8000       li      at,0x8000
+0+0c04 <[^>]*> 00e1 0950       addu    at,at,a3
+0+0c08 <[^>]*> 60c1 a800       sbe     a2,0\(at\)
+0+0c0c <[^>]*> 5020 8000       li      at,0x8000
+0+0c10 <[^>]*> 6101 a800       sbe     t0,0\(at\)
+0+0c14 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0c18 <[^>]*> 0141 0950       addu    at,at,t2
+0+0c1c <[^>]*> 6121 a800       sbe     t1,0\(at\)
+0+0c20 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0c24 <[^>]*> 6161 a800       sbe     t3,0\(at\)
+0+0c28 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0c2c <[^>]*> 01a1 0950       addu    at,at,t5
+0+0c30 <[^>]*> 6181 a9ff       sbe     t4,-1\(at\)
+0+0c34 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0c38 <[^>]*> 61c1 a9ff       sbe     t6,-1\(at\)
+0+0c3c <[^>]*> 61f0 a800       sbe     t7,0\(s0\)
+0+0c40 <[^>]*> 41a1 0000       lui     at,0x0
+                       c40: R_MICROMIPS_HI16   MYDATA
+0+0c44 <[^>]*> 3021 0000       addiu   at,at,0
+                       c44: R_MICROMIPS_LO16   MYDATA
+0+0c48 <[^>]*> 6221 a800       sbe     s1,0\(at\)
+0+0c4c <[^>]*> 6253 ad00       sce     s2,-256\(s3\)
+0+0c50 <[^>]*> 6280 ad00       sce     s4,-256\(zero\)
+0+0c54 <[^>]*> 62b6 acff       sce     s5,255\(s6\)
+0+0c58 <[^>]*> 62e0 acff       sce     s7,255\(zero\)
+0+0c5c <[^>]*> 3020 fe00       li      at,-512
+0+0c60 <[^>]*> 0321 0950       addu    at,at,t9
+0+0c64 <[^>]*> 6301 acff       sce     t8,255\(at\)
+0+0c68 <[^>]*> 3020 fe00       li      at,-512
+0+0c6c <[^>]*> 6341 acff       sce     k0,255\(at\)
+0+0c70 <[^>]*> 3020 0200       li      at,512
+0+0c74 <[^>]*> 0381 0950       addu    at,at,gp
+0+0c78 <[^>]*> 6361 ad00       sce     k1,-256\(at\)
+0+0c7c <[^>]*> 3020 0200       li      at,512
+0+0c80 <[^>]*> 63a1 ad00       sce     sp,-256\(at\)
+0+0c84 <[^>]*> 3020 fe00       li      at,-512
+0+0c88 <[^>]*> 03e1 0950       addu    at,at,ra
+0+0c8c <[^>]*> 63c1 ac00       sce     s8,0\(at\)
+0+0c90 <[^>]*> 3020 fe00       li      at,-512
+0+0c94 <[^>]*> 6001 ac00       sce     zero,0\(at\)
+0+0c98 <[^>]*> 3020 0200       li      at,512
+0+0c9c <[^>]*> 0061 0950       addu    at,at,v1
+0+0ca0 <[^>]*> 6041 adff       sce     v0,-1\(at\)
+0+0ca4 <[^>]*> 3020 0200       li      at,512
+0+0ca8 <[^>]*> 6081 adff       sce     a0,-1\(at\)
+0+0cac <[^>]*> 3020 fc00       li      at,-1024
+0+0cb0 <[^>]*> 00c1 0950       addu    at,at,a2
+0+0cb4 <[^>]*> 60a1 ac00       sce     a1,0\(at\)
+0+0cb8 <[^>]*> 3020 fc00       li      at,-1024
+0+0cbc <[^>]*> 60e1 ac00       sce     a3,0\(at\)
+0+0cc0 <[^>]*> 3020 0400       li      at,1024
+0+0cc4 <[^>]*> 0121 0950       addu    at,at,t1
+0+0cc8 <[^>]*> 6101 adff       sce     t0,-1\(at\)
+0+0ccc <[^>]*> 3020 0400       li      at,1024
+0+0cd0 <[^>]*> 6141 adff       sce     t2,-1\(at\)
+0+0cd4 <[^>]*> 3020 f800       li      at,-2048
+0+0cd8 <[^>]*> 0181 0950       addu    at,at,t4
+0+0cdc <[^>]*> 6161 ac00       sce     t3,0\(at\)
+0+0ce0 <[^>]*> 3020 f800       li      at,-2048
+0+0ce4 <[^>]*> 61a1 ac00       sce     t5,0\(at\)
+0+0ce8 <[^>]*> 3020 0800       li      at,2048
+0+0cec <[^>]*> 01e1 0950       addu    at,at,t7
+0+0cf0 <[^>]*> 61c1 adff       sce     t6,-1\(at\)
+0+0cf4 <[^>]*> 3020 0800       li      at,2048
+0+0cf8 <[^>]*> 6201 adff       sce     s0,-1\(at\)
+0+0cfc <[^>]*> 3020 f000       li      at,-4096
+0+0d00 <[^>]*> 0241 0950       addu    at,at,s2
+0+0d04 <[^>]*> 6221 ac00       sce     s1,0\(at\)
+0+0d08 <[^>]*> 3020 f000       li      at,-4096
+0+0d0c <[^>]*> 6261 ac00       sce     s3,0\(at\)
+0+0d10 <[^>]*> 3020 1000       li      at,4096
+0+0d14 <[^>]*> 02a1 0950       addu    at,at,s5
+0+0d18 <[^>]*> 6281 adff       sce     s4,-1\(at\)
+0+0d1c <[^>]*> 3020 1000       li      at,4096
+0+0d20 <[^>]*> 62c1 adff       sce     s6,-1\(at\)
+0+0d24 <[^>]*> 3020 8000       li      at,-32768
+0+0d28 <[^>]*> 0301 0950       addu    at,at,t8
+0+0d2c <[^>]*> 62e1 ac00       sce     s7,0\(at\)
+0+0d30 <[^>]*> 3020 8000       li      at,-32768
+0+0d34 <[^>]*> 6321 ac00       sce     t9,0\(at\)
+0+0d38 <[^>]*> 5020 8000       li      at,0x8000
+0+0d3c <[^>]*> 0361 0950       addu    at,at,k1
+0+0d40 <[^>]*> 6341 adff       sce     k0,-1\(at\)
+0+0d44 <[^>]*> 5020 8000       li      at,0x8000
+0+0d48 <[^>]*> 6381 adff       sce     gp,-1\(at\)
+0+0d4c <[^>]*> 3020 8000       li      at,-32768
+0+0d50 <[^>]*> 03c1 0950       addu    at,at,s8
+0+0d54 <[^>]*> 63a1 adff       sce     sp,-1\(at\)
+0+0d58 <[^>]*> 3020 8000       li      at,-32768
+0+0d5c <[^>]*> 63e1 adff       sce     ra,-1\(at\)
+0+0d60 <[^>]*> 5020 8000       li      at,0x8000
+0+0d64 <[^>]*> 0041 0950       addu    at,at,v0
+0+0d68 <[^>]*> 6001 ac00       sce     zero,0\(at\)
+0+0d6c <[^>]*> 5020 8000       li      at,0x8000
+0+0d70 <[^>]*> 6061 ac00       sce     v1,0\(at\)
+0+0d74 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0d78 <[^>]*> 00a1 0950       addu    at,at,a1
+0+0d7c <[^>]*> 6081 ac00       sce     a0,0\(at\)
+0+0d80 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0d84 <[^>]*> 60c1 ac00       sce     a2,0\(at\)
+0+0d88 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0d8c <[^>]*> 0101 0950       addu    at,at,t0
+0+0d90 <[^>]*> 60e1 adff       sce     a3,-1\(at\)
+0+0d94 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0d98 <[^>]*> 6121 adff       sce     t1,-1\(at\)
+0+0d9c <[^>]*> 614b ac00       sce     t2,0\(t3\)
+0+0da0 <[^>]*> 41a1 0000       lui     at,0x0
+                       da0: R_MICROMIPS_HI16   MYDATA
+0+0da4 <[^>]*> 3021 0000       addiu   at,at,0
+                       da4: R_MICROMIPS_LO16   MYDATA
+0+0da8 <[^>]*> 6181 ac00       sce     t4,0\(at\)
+0+0dac <[^>]*> 61ae ab00       she     t5,-256\(t6\)
+0+0db0 <[^>]*> 61e0 ab00       she     t7,-256\(zero\)
+0+0db4 <[^>]*> 6211 aaff       she     s0,255\(s1\)
+0+0db8 <[^>]*> 6240 aaff       she     s2,255\(zero\)
+0+0dbc <[^>]*> 3020 fe00       li      at,-512
+0+0dc0 <[^>]*> 0281 0950       addu    at,at,s4
+0+0dc4 <[^>]*> 6261 aaff       she     s3,255\(at\)
+0+0dc8 <[^>]*> 3020 fe00       li      at,-512
+0+0dcc <[^>]*> 62a1 aaff       she     s5,255\(at\)
+0+0dd0 <[^>]*> 3020 0200       li      at,512
+0+0dd4 <[^>]*> 02e1 0950       addu    at,at,s7
+0+0dd8 <[^>]*> 62c1 ab00       she     s6,-256\(at\)
+0+0ddc <[^>]*> 3020 0200       li      at,512
+0+0de0 <[^>]*> 6301 ab00       she     t8,-256\(at\)
+0+0de4 <[^>]*> 3020 fe00       li      at,-512
+0+0de8 <[^>]*> 0341 0950       addu    at,at,k0
+0+0dec <[^>]*> 6321 aa00       she     t9,0\(at\)
+0+0df0 <[^>]*> 3020 fe00       li      at,-512
+0+0df4 <[^>]*> 6361 aa00       she     k1,0\(at\)
+0+0df8 <[^>]*> 3020 0200       li      at,512
+0+0dfc <[^>]*> 03a1 0950       addu    at,at,sp
+0+0e00 <[^>]*> 6381 abff       she     gp,-1\(at\)
+0+0e04 <[^>]*> 3020 0200       li      at,512
+0+0e08 <[^>]*> 63c1 abff       she     s8,-1\(at\)
+0+0e0c <[^>]*> 3020 fc00       li      at,-1024
+0+0e10 <[^>]*> 63e1 aa00       she     ra,0\(at\)
+0+0e14 <[^>]*> 3020 fc00       li      at,-1024
+0+0e18 <[^>]*> 6041 aa00       she     v0,0\(at\)
+0+0e1c <[^>]*> 3020 0400       li      at,1024
+0+0e20 <[^>]*> 0081 0950       addu    at,at,a0
+0+0e24 <[^>]*> 6061 abff       she     v1,-1\(at\)
+0+0e28 <[^>]*> 3020 0400       li      at,1024
+0+0e2c <[^>]*> 60a1 abff       she     a1,-1\(at\)
+0+0e30 <[^>]*> 3020 f800       li      at,-2048
+0+0e34 <[^>]*> 00e1 0950       addu    at,at,a3
+0+0e38 <[^>]*> 60c1 aa00       she     a2,0\(at\)
+0+0e3c <[^>]*> 3020 f800       li      at,-2048
+0+0e40 <[^>]*> 6101 aa00       she     t0,0\(at\)
+0+0e44 <[^>]*> 3020 0800       li      at,2048
+0+0e48 <[^>]*> 0141 0950       addu    at,at,t2
+0+0e4c <[^>]*> 6121 abff       she     t1,-1\(at\)
+0+0e50 <[^>]*> 3020 0800       li      at,2048
+0+0e54 <[^>]*> 6161 abff       she     t3,-1\(at\)
+0+0e58 <[^>]*> 3020 f000       li      at,-4096
+0+0e5c <[^>]*> 01a1 0950       addu    at,at,t5
+0+0e60 <[^>]*> 6181 aa00       she     t4,0\(at\)
+0+0e64 <[^>]*> 3020 f000       li      at,-4096
+0+0e68 <[^>]*> 61c1 aa00       she     t6,0\(at\)
+0+0e6c <[^>]*> 3020 1000       li      at,4096
+0+0e70 <[^>]*> 0201 0950       addu    at,at,s0
+0+0e74 <[^>]*> 61e1 abff       she     t7,-1\(at\)
+0+0e78 <[^>]*> 3020 1000       li      at,4096
+0+0e7c <[^>]*> 6221 abff       she     s1,-1\(at\)
+0+0e80 <[^>]*> 3020 8000       li      at,-32768
+0+0e84 <[^>]*> 0261 0950       addu    at,at,s3
+0+0e88 <[^>]*> 6241 aa00       she     s2,0\(at\)
+0+0e8c <[^>]*> 3020 8000       li      at,-32768
+0+0e90 <[^>]*> 6281 aa00       she     s4,0\(at\)
+0+0e94 <[^>]*> 5020 8000       li      at,0x8000
+0+0e98 <[^>]*> 02c1 0950       addu    at,at,s6
+0+0e9c <[^>]*> 62a1 abff       she     s5,-1\(at\)
+0+0ea0 <[^>]*> 5020 8000       li      at,0x8000
+0+0ea4 <[^>]*> 62e1 abff       she     s7,-1\(at\)
+0+0ea8 <[^>]*> 3020 8000       li      at,-32768
+0+0eac <[^>]*> 0321 0950       addu    at,at,t9
+0+0eb0 <[^>]*> 6301 abff       she     t8,-1\(at\)
+0+0eb4 <[^>]*> 3020 8000       li      at,-32768
+0+0eb8 <[^>]*> 6341 abff       she     k0,-1\(at\)
+0+0ebc <[^>]*> 5020 8000       li      at,0x8000
+0+0ec0 <[^>]*> 0381 0950       addu    at,at,gp
+0+0ec4 <[^>]*> 6361 aa00       she     k1,0\(at\)
+0+0ec8 <[^>]*> 5020 8000       li      at,0x8000
+0+0ecc <[^>]*> 63a1 aa00       she     sp,0\(at\)
+0+0ed0 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0ed4 <[^>]*> 03e1 0950       addu    at,at,ra
+0+0ed8 <[^>]*> 63c1 aa00       she     s8,0\(at\)
+0+0edc <[^>]*> 41a1 8000       lui     at,0x8000
+0+0ee0 <[^>]*> 6001 aa00       she     zero,0\(at\)
+0+0ee4 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0ee8 <[^>]*> 0061 0950       addu    at,at,v1
+0+0eec <[^>]*> 6041 abff       she     v0,-1\(at\)
+0+0ef0 <[^>]*> 41a1 8000       lui     at,0x8000
+0+0ef4 <[^>]*> 6081 abff       she     a0,-1\(at\)
+0+0ef8 <[^>]*> 60a6 aa00       she     a1,0\(a2\)
+0+0efc <[^>]*> 41a1 0000       lui     at,0x0
+                       efc: R_MICROMIPS_HI16   MYDATA
+0+0f00 <[^>]*> 3021 0000       addiu   at,at,0
+                       f00: R_MICROMIPS_LO16   MYDATA
+0+0f04 <[^>]*> 60e1 aa00       she     a3,0\(at\)
+0+0f08 <[^>]*> 6109 af00       swe     t0,-256\(t1\)
+0+0f0c <[^>]*> 6140 af00       swe     t2,-256\(zero\)
+0+0f10 <[^>]*> 616c aeff       swe     t3,255\(t4\)
+0+0f14 <[^>]*> 61a0 aeff       swe     t5,255\(zero\)
+0+0f18 <[^>]*> 3020 fe00       li      at,-512
+0+0f1c <[^>]*> 01e1 0950       addu    at,at,t7
+0+0f20 <[^>]*> 61c1 aeff       swe     t6,255\(at\)
+0+0f24 <[^>]*> 3020 fe00       li      at,-512
+0+0f28 <[^>]*> 6201 aeff       swe     s0,255\(at\)
+0+0f2c <[^>]*> 3020 0200       li      at,512
+0+0f30 <[^>]*> 0241 0950       addu    at,at,s2
+0+0f34 <[^>]*> 6221 af00       swe     s1,-256\(at\)
+0+0f38 <[^>]*> 3020 0200       li      at,512
+0+0f3c <[^>]*> 6261 af00       swe     s3,-256\(at\)
+0+0f40 <[^>]*> 3020 fe00       li      at,-512
+0+0f44 <[^>]*> 02a1 0950       addu    at,at,s5
+0+0f48 <[^>]*> 6281 ae00       swe     s4,0\(at\)
+0+0f4c <[^>]*> 3020 fe00       li      at,-512
+0+0f50 <[^>]*> 62c1 ae00       swe     s6,0\(at\)
+0+0f54 <[^>]*> 3020 0200       li      at,512
+0+0f58 <[^>]*> 0301 0950       addu    at,at,t8
+0+0f5c <[^>]*> 62e1 afff       swe     s7,-1\(at\)
+0+0f60 <[^>]*> 3020 0200       li      at,512
+0+0f64 <[^>]*> 6321 afff       swe     t9,-1\(at\)
+0+0f68 <[^>]*> 3020 fc00       li      at,-1024
+0+0f6c <[^>]*> 0361 0950       addu    at,at,k1
+0+0f70 <[^>]*> 6341 ae00       swe     k0,0\(at\)
+0+0f74 <[^>]*> 3020 fc00       li      at,-1024
+0+0f78 <[^>]*> 6381 ae00       swe     gp,0\(at\)
+0+0f7c <[^>]*> 3020 0400       li      at,1024
+0+0f80 <[^>]*> 03c1 0950       addu    at,at,s8
+0+0f84 <[^>]*> 63a1 afff       swe     sp,-1\(at\)
+0+0f88 <[^>]*> 3020 0400       li      at,1024
+0+0f8c <[^>]*> 63e1 afff       swe     ra,-1\(at\)
+0+0f90 <[^>]*> 3020 f800       li      at,-2048
+0+0f94 <[^>]*> 0041 0950       addu    at,at,v0
+0+0f98 <[^>]*> 6001 ae00       swe     zero,0\(at\)
+0+0f9c <[^>]*> 3020 f800       li      at,-2048
+0+0fa0 <[^>]*> 6061 ae00       swe     v1,0\(at\)
+0+0fa4 <[^>]*> 3020 0800       li      at,2048
+0+0fa8 <[^>]*> 00a1 0950       addu    at,at,a1
+0+0fac <[^>]*> 6081 afff       swe     a0,-1\(at\)
+0+0fb0 <[^>]*> 3020 0800       li      at,2048
+0+0fb4 <[^>]*> 60c1 afff       swe     a2,-1\(at\)
+0+0fb8 <[^>]*> 3020 f000       li      at,-4096
+0+0fbc <[^>]*> 0101 0950       addu    at,at,t0
+0+0fc0 <[^>]*> 60e1 ae00       swe     a3,0\(at\)
+0+0fc4 <[^>]*> 3020 f000       li      at,-4096
+0+0fc8 <[^>]*> 6121 ae00       swe     t1,0\(at\)
+0+0fcc <[^>]*> 3020 1000       li      at,4096
+0+0fd0 <[^>]*> 0161 0950       addu    at,at,t3
+0+0fd4 <[^>]*> 6141 afff       swe     t2,-1\(at\)
+0+0fd8 <[^>]*> 3020 1000       li      at,4096
+0+0fdc <[^>]*> 6181 afff       swe     t4,-1\(at\)
+0+0fe0 <[^>]*> 3020 8000       li      at,-32768
+0+0fe4 <[^>]*> 01c1 0950       addu    at,at,t6
+0+0fe8 <[^>]*> 61a1 ae00       swe     t5,0\(at\)
+0+0fec <[^>]*> 3020 8000       li      at,-32768
+0+0ff0 <[^>]*> 61e1 ae00       swe     t7,0\(at\)
+0+0ff4 <[^>]*> 5020 8000       li      at,0x8000
+0+0ff8 <[^>]*> 0221 0950       addu    at,at,s1
+0+0ffc <[^>]*> 6201 afff       swe     s0,-1\(at\)
+0+1000 <[^>]*> 5020 8000       li      at,0x8000
+0+1004 <[^>]*> 6241 afff       swe     s2,-1\(at\)
+0+1008 <[^>]*> 3020 8000       li      at,-32768
+0+100c <[^>]*> 0281 0950       addu    at,at,s4
+0+1010 <[^>]*> 6261 afff       swe     s3,-1\(at\)
+0+1014 <[^>]*> 3020 8000       li      at,-32768
+0+1018 <[^>]*> 62a1 afff       swe     s5,-1\(at\)
+0+101c <[^>]*> 5020 8000       li      at,0x8000
+0+1020 <[^>]*> 02e1 0950       addu    at,at,s7
+0+1024 <[^>]*> 62c1 ae00       swe     s6,0\(at\)
+0+1028 <[^>]*> 5020 8000       li      at,0x8000
+0+102c <[^>]*> 6301 ae00       swe     t8,0\(at\)
+0+1030 <[^>]*> 41a1 8000       lui     at,0x8000
+0+1034 <[^>]*> 0341 0950       addu    at,at,k0
+0+1038 <[^>]*> 6321 ae00       swe     t9,0\(at\)
+0+103c <[^>]*> 41a1 8000       lui     at,0x8000
+0+1040 <[^>]*> 6361 ae00       swe     k1,0\(at\)
+0+1044 <[^>]*> 41a1 8000       lui     at,0x8000
+0+1048 <[^>]*> 03a1 0950       addu    at,at,sp
+0+104c <[^>]*> 6381 afff       swe     gp,-1\(at\)
+0+1050 <[^>]*> 41a1 8000       lui     at,0x8000
+0+1054 <[^>]*> 63c1 afff       swe     s8,-1\(at\)
+0+1058 <[^>]*> 63e0 ae00       swe     ra,0\(zero\)
+0+105c <[^>]*> 41a1 0000       lui     at,0x0
+                       105c: R_MICROMIPS_HI16  MYDATA
+0+1060 <[^>]*> 3021 0000       addiu   at,at,0
+                       1060: R_MICROMIPS_LO16  MYDATA
+0+1064 <[^>]*> 6041 ae00       swe     v0,0\(at\)
+0+1068 <[^>]*> 6064 a100       swle    v1,-256\(a0\)
+0+106c <[^>]*> 60a0 a100       swle    a1,-256\(zero\)
+0+1070 <[^>]*> 60c7 a0ff       swle    a2,255\(a3\)
+0+1074 <[^>]*> 6100 a0ff       swle    t0,255\(zero\)
+0+1078 <[^>]*> 3020 fe00       li      at,-512
+0+107c <[^>]*> 0141 0950       addu    at,at,t2
+0+1080 <[^>]*> 6121 a0ff       swle    t1,255\(at\)
+0+1084 <[^>]*> 3020 fe00       li      at,-512
+0+1088 <[^>]*> 6161 a0ff       swle    t3,255\(at\)
+0+108c <[^>]*> 3020 0200       li      at,512
+0+1090 <[^>]*> 01a1 0950       addu    at,at,t5
+0+1094 <[^>]*> 6181 a100       swle    t4,-256\(at\)
+0+1098 <[^>]*> 3020 0200       li      at,512
+0+109c <[^>]*> 61c1 a100       swle    t6,-256\(at\)
+0+10a0 <[^>]*> 3020 fe00       li      at,-512
+0+10a4 <[^>]*> 0201 0950       addu    at,at,s0
+0+10a8 <[^>]*> 61e1 a000       swle    t7,0\(at\)
+0+10ac <[^>]*> 3020 fe00       li      at,-512
+0+10b0 <[^>]*> 6221 a000       swle    s1,0\(at\)
+0+10b4 <[^>]*> 3020 0200       li      at,512
+0+10b8 <[^>]*> 0261 0950       addu    at,at,s3
+0+10bc <[^>]*> 6241 a1ff       swle    s2,-1\(at\)
+0+10c0 <[^>]*> 3020 0200       li      at,512
+0+10c4 <[^>]*> 6281 a1ff       swle    s4,-1\(at\)
+0+10c8 <[^>]*> 3020 fc00       li      at,-1024
+0+10cc <[^>]*> 02c1 0950       addu    at,at,s6
+0+10d0 <[^>]*> 62a1 a000       swle    s5,0\(at\)
+0+10d4 <[^>]*> 3020 fc00       li      at,-1024
+0+10d8 <[^>]*> 62e1 a000       swle    s7,0\(at\)
+0+10dc <[^>]*> 3020 0400       li      at,1024
+0+10e0 <[^>]*> 0321 0950       addu    at,at,t9
+0+10e4 <[^>]*> 6301 a1ff       swle    t8,-1\(at\)
+0+10e8 <[^>]*> 3020 0400       li      at,1024
+0+10ec <[^>]*> 6341 a1ff       swle    k0,-1\(at\)
+0+10f0 <[^>]*> 3020 f800       li      at,-2048
+0+10f4 <[^>]*> 0381 0950       addu    at,at,gp
+0+10f8 <[^>]*> 6361 a000       swle    k1,0\(at\)
+0+10fc <[^>]*> 3020 f800       li      at,-2048
+0+1100 <[^>]*> 63a1 a000       swle    sp,0\(at\)
+0+1104 <[^>]*> 3020 0800       li      at,2048
+0+1108 <[^>]*> 03e1 0950       addu    at,at,ra
+0+110c <[^>]*> 63c1 a1ff       swle    s8,-1\(at\)
+0+1110 <[^>]*> 3020 0800       li      at,2048
+0+1114 <[^>]*> 6001 a1ff       swle    zero,-1\(at\)
+0+1118 <[^>]*> 3020 f000       li      at,-4096
+0+111c <[^>]*> 0061 0950       addu    at,at,v1
+0+1120 <[^>]*> 6041 a000       swle    v0,0\(at\)
+0+1124 <[^>]*> 3020 f000       li      at,-4096
+0+1128 <[^>]*> 6081 a000       swle    a0,0\(at\)
+0+112c <[^>]*> 3020 1000       li      at,4096
+0+1130 <[^>]*> 00c1 0950       addu    at,at,a2
+0+1134 <[^>]*> 60a1 a1ff       swle    a1,-1\(at\)
+0+1138 <[^>]*> 3020 1000       li      at,4096
+0+113c <[^>]*> 60e1 a1ff       swle    a3,-1\(at\)
+0+1140 <[^>]*> 3020 8000       li      at,-32768
+0+1144 <[^>]*> 0121 0950       addu    at,at,t1
+0+1148 <[^>]*> 6101 a000       swle    t0,0\(at\)
+0+114c <[^>]*> 3020 8000       li      at,-32768
+0+1150 <[^>]*> 6141 a000       swle    t2,0\(at\)
+0+1154 <[^>]*> 5020 8000       li      at,0x8000
+0+1158 <[^>]*> 0181 0950       addu    at,at,t4
+0+115c <[^>]*> 6161 a1ff       swle    t3,-1\(at\)
+0+1160 <[^>]*> 5020 8000       li      at,0x8000
+0+1164 <[^>]*> 61a1 a1ff       swle    t5,-1\(at\)
+0+1168 <[^>]*> 3020 8000       li      at,-32768
+0+116c <[^>]*> 01e1 0950       addu    at,at,t7
+0+1170 <[^>]*> 61c1 a1ff       swle    t6,-1\(at\)
+0+1174 <[^>]*> 3020 8000       li      at,-32768
+0+1178 <[^>]*> 6201 a1ff       swle    s0,-1\(at\)
+0+117c <[^>]*> 5020 8000       li      at,0x8000
+0+1180 <[^>]*> 0241 0950       addu    at,at,s2
+0+1184 <[^>]*> 6221 a000       swle    s1,0\(at\)
+0+1188 <[^>]*> 5020 8000       li      at,0x8000
+0+118c <[^>]*> 6261 a000       swle    s3,0\(at\)
+0+1190 <[^>]*> 41a1 8000       lui     at,0x8000
+0+1194 <[^>]*> 02a1 0950       addu    at,at,s5
+0+1198 <[^>]*> 6281 a000       swle    s4,0\(at\)
+0+119c <[^>]*> 41a1 8000       lui     at,0x8000
+0+11a0 <[^>]*> 62c1 a000       swle    s6,0\(at\)
+0+11a4 <[^>]*> 41a1 8000       lui     at,0x8000
+0+11a8 <[^>]*> 0301 0950       addu    at,at,t8
+0+11ac <[^>]*> 62e1 a1ff       swle    s7,-1\(at\)
+0+11b0 <[^>]*> 41a1 8000       lui     at,0x8000
+0+11b4 <[^>]*> 6321 a1ff       swle    t9,-1\(at\)
+0+11b8 <[^>]*> 635b a000       swle    k0,0\(k1\)
+0+11bc <[^>]*> 41a1 0000       lui     at,0x0
+                       11bc: R_MICROMIPS_HI16  MYDATA
+0+11c0 <[^>]*> 3021 0000       addiu   at,at,0
+                       11c0: R_MICROMIPS_LO16  MYDATA
+0+11c4 <[^>]*> 6381 a000       swle    gp,0\(at\)
+0+11c8 <[^>]*> 63be a300       swre    sp,-256\(s8\)
+0+11cc <[^>]*> 63e0 a300       swre    ra,-256\(zero\)
+0+11d0 <[^>]*> 6002 a2ff       swre    zero,255\(v0\)
+0+11d4 <[^>]*> 6060 a2ff       swre    v1,255\(zero\)
+0+11d8 <[^>]*> 3020 fe00       li      at,-512
+0+11dc <[^>]*> 00a1 0950       addu    at,at,a1
+0+11e0 <[^>]*> 6081 a2ff       swre    a0,255\(at\)
+0+11e4 <[^>]*> 3020 fe00       li      at,-512
+0+11e8 <[^>]*> 60c1 a2ff       swre    a2,255\(at\)
+0+11ec <[^>]*> 3020 0200       li      at,512
+0+11f0 <[^>]*> 0101 0950       addu    at,at,t0
+0+11f4 <[^>]*> 60e1 a300       swre    a3,-256\(at\)
+0+11f8 <[^>]*> 3020 0200       li      at,512
+0+11fc <[^>]*> 6121 a300       swre    t1,-256\(at\)
+0+1200 <[^>]*> 3020 fe00       li      at,-512
+0+1204 <[^>]*> 0161 0950       addu    at,at,t3
+0+1208 <[^>]*> 6141 a200       swre    t2,0\(at\)
+0+120c <[^>]*> 3020 fe00       li      at,-512
+0+1210 <[^>]*> 6181 a200       swre    t4,0\(at\)
+0+1214 <[^>]*> 3020 0200       li      at,512
+0+1218 <[^>]*> 01c1 0950       addu    at,at,t6
+0+121c <[^>]*> 61a1 a3ff       swre    t5,-1\(at\)
+0+1220 <[^>]*> 3020 0200       li      at,512
+0+1224 <[^>]*> 61e1 a3ff       swre    t7,-1\(at\)
+0+1228 <[^>]*> 3020 fc00       li      at,-1024
+0+122c <[^>]*> 0221 0950       addu    at,at,s1
+0+1230 <[^>]*> 6201 a200       swre    s0,0\(at\)
+0+1234 <[^>]*> 3020 fc00       li      at,-1024
+0+1238 <[^>]*> 6241 a200       swre    s2,0\(at\)
+0+123c <[^>]*> 3020 0400       li      at,1024
+0+1240 <[^>]*> 0281 0950       addu    at,at,s4
+0+1244 <[^>]*> 6261 a3ff       swre    s3,-1\(at\)
+0+1248 <[^>]*> 3020 0400       li      at,1024
+0+124c <[^>]*> 62a1 a3ff       swre    s5,-1\(at\)
+0+1250 <[^>]*> 3020 f800       li      at,-2048
+0+1254 <[^>]*> 02e1 0950       addu    at,at,s7
+0+1258 <[^>]*> 62c1 a200       swre    s6,0\(at\)
+0+125c <[^>]*> 3020 f800       li      at,-2048
+0+1260 <[^>]*> 6301 a200       swre    t8,0\(at\)
+0+1264 <[^>]*> 3020 0800       li      at,2048
+0+1268 <[^>]*> 0341 0950       addu    at,at,k0
+0+126c <[^>]*> 6321 a3ff       swre    t9,-1\(at\)
+0+1270 <[^>]*> 3020 0800       li      at,2048
+0+1274 <[^>]*> 6361 a3ff       swre    k1,-1\(at\)
+0+1278 <[^>]*> 3020 f000       li      at,-4096
+0+127c <[^>]*> 03a1 0950       addu    at,at,sp
+0+1280 <[^>]*> 6381 a200       swre    gp,0\(at\)
+0+1284 <[^>]*> 3020 f000       li      at,-4096
+0+1288 <[^>]*> 63c1 a200       swre    s8,0\(at\)
+0+128c <[^>]*> 3020 1000       li      at,4096
+0+1290 <[^>]*> 63e1 a3ff       swre    ra,-1\(at\)
+0+1294 <[^>]*> 3020 1000       li      at,4096
+0+1298 <[^>]*> 6041 a3ff       swre    v0,-1\(at\)
+0+129c <[^>]*> 3020 8000       li      at,-32768
+0+12a0 <[^>]*> 0081 0950       addu    at,at,a0
+0+12a4 <[^>]*> 6061 a200       swre    v1,0\(at\)
+0+12a8 <[^>]*> 3020 8000       li      at,-32768
+0+12ac <[^>]*> 60a1 a200       swre    a1,0\(at\)
+0+12b0 <[^>]*> 5020 8000       li      at,0x8000
+0+12b4 <[^>]*> 00e1 0950       addu    at,at,a3
+0+12b8 <[^>]*> 60c1 a3ff       swre    a2,-1\(at\)
+0+12bc <[^>]*> 5020 8000       li      at,0x8000
+0+12c0 <[^>]*> 6101 a3ff       swre    t0,-1\(at\)
+0+12c4 <[^>]*> 3020 8000       li      at,-32768
+0+12c8 <[^>]*> 0141 0950       addu    at,at,t2
+0+12cc <[^>]*> 6121 a3ff       swre    t1,-1\(at\)
+0+12d0 <[^>]*> 3020 8000       li      at,-32768
+0+12d4 <[^>]*> 6161 a3ff       swre    t3,-1\(at\)
+0+12d8 <[^>]*> 5020 8000       li      at,0x8000
+0+12dc <[^>]*> 01a1 0950       addu    at,at,t5
+0+12e0 <[^>]*> 6181 a200       swre    t4,0\(at\)
+0+12e4 <[^>]*> 5020 8000       li      at,0x8000
+0+12e8 <[^>]*> 61c1 a200       swre    t6,0\(at\)
+0+12ec <[^>]*> 41a1 8000       lui     at,0x8000
+0+12f0 <[^>]*> 0201 0950       addu    at,at,s0
+0+12f4 <[^>]*> 61e1 a200       swre    t7,0\(at\)
+0+12f8 <[^>]*> 41a1 8000       lui     at,0x8000
+0+12fc <[^>]*> 6221 a200       swre    s1,0\(at\)
+0+1300 <[^>]*> 41a1 8000       lui     at,0x8000
+0+1304 <[^>]*> 0261 0950       addu    at,at,s3
+0+1308 <[^>]*> 6241 a3ff       swre    s2,-1\(at\)
+0+130c <[^>]*> 41a1 8000       lui     at,0x8000
+0+1310 <[^>]*> 6281 a3ff       swre    s4,-1\(at\)
+0+1314 <[^>]*> 62b6 a200       swre    s5,0\(s6\)
+0+1318 <[^>]*> 41a1 0000       lui     at,0x0
+                       1318: R_MICROMIPS_HI16  MYDATA
+0+131c <[^>]*> 3021 0000       addiu   at,at,0
+                       131c: R_MICROMIPS_LO16  MYDATA
+0+1320 <[^>]*> 62e1 a200       swre    s7,0\(at\)
+0+1324 <[^>]*> 6319 a700       cachee  0x18,-256\(t9\)
+0+1328 <[^>]*> 6340 a700       cachee  0x1a,-256\(zero\)
+0+132c <[^>]*> 637c a6ff       cachee  0x1b,255\(gp\)
+0+1330 <[^>]*> 63a0 a6ff       cachee  0x1d,255\(zero\)
+0+1334 <[^>]*> 3020 fe00       li      at,-512
+0+1338 <[^>]*> 03e1 0950       addu    at,at,ra
+0+133c <[^>]*> 63c1 a6ff       cachee  0x1e,255\(at\)
+0+1340 <[^>]*> 3020 fe00       li      at,-512
+0+1344 <[^>]*> 6001 a6ff       cachee  0x0,255\(at\)
+0+1348 <[^>]*> 3020 0200       li      at,512
+0+134c <[^>]*> 0061 0950       addu    at,at,v1
+0+1350 <[^>]*> 6041 a700       cachee  0x2,-256\(at\)
+0+1354 <[^>]*> 3020 0200       li      at,512
+0+1358 <[^>]*> 6081 a700       cachee  0x4,-256\(at\)
+0+135c <[^>]*> 3020 fe00       li      at,-512
+0+1360 <[^>]*> 00c1 0950       addu    at,at,a2
+0+1364 <[^>]*> 60a1 a600       cachee  0x5,0\(at\)
+0+1368 <[^>]*> 3020 fe00       li      at,-512
+0+136c <[^>]*> 60e1 a600       cachee  0x7,0\(at\)
+0+1370 <[^>]*> 3020 0200       li      at,512
+0+1374 <[^>]*> 0121 0950       addu    at,at,t1
+0+1378 <[^>]*> 6101 a7ff       cachee  0x8,-1\(at\)
+0+137c <[^>]*> 3020 0200       li      at,512
+0+1380 <[^>]*> 6141 a7ff       cachee  0xa,-1\(at\)
+0+1384 <[^>]*> 3020 fc00       li      at,-1024
+0+1388 <[^>]*> 0181 0950       addu    at,at,t4
+0+138c <[^>]*> 6161 a600       cachee  0xb,0\(at\)
+0+1390 <[^>]*> 3020 fc00       li      at,-1024
+0+1394 <[^>]*> 61a1 a600       cachee  0xd,0\(at\)
+0+1398 <[^>]*> 3020 0400       li      at,1024
+0+139c <[^>]*> 01e1 0950       addu    at,at,t7
+0+13a0 <[^>]*> 61c1 a7ff       cachee  0xe,-1\(at\)
+0+13a4 <[^>]*> 3020 0400       li      at,1024
+0+13a8 <[^>]*> 6201 a7ff       cachee  0x10,-1\(at\)
+0+13ac <[^>]*> 3020 f800       li      at,-2048
+0+13b0 <[^>]*> 0241 0950       addu    at,at,s2
+0+13b4 <[^>]*> 6221 a600       cachee  0x11,0\(at\)
+0+13b8 <[^>]*> 3020 f800       li      at,-2048
+0+13bc <[^>]*> 6261 a600       cachee  0x13,0\(at\)
+0+13c0 <[^>]*> 3020 0800       li      at,2048
+0+13c4 <[^>]*> 02a1 0950       addu    at,at,s5
+0+13c8 <[^>]*> 6281 a7ff       cachee  0x14,-1\(at\)
+0+13cc <[^>]*> 3020 0800       li      at,2048
+0+13d0 <[^>]*> 62c1 a7ff       cachee  0x16,-1\(at\)
+0+13d4 <[^>]*> 3020 f000       li      at,-4096
+0+13d8 <[^>]*> 0301 0950       addu    at,at,t8
+0+13dc <[^>]*> 62e1 a600       cachee  0x17,0\(at\)
+0+13e0 <[^>]*> 3020 f000       li      at,-4096
+0+13e4 <[^>]*> 6321 a600       cachee  0x19,0\(at\)
+0+13e8 <[^>]*> 3020 1000       li      at,4096
+0+13ec <[^>]*> 0361 0950       addu    at,at,k1
+0+13f0 <[^>]*> 6341 a7ff       cachee  0x1a,-1\(at\)
+0+13f4 <[^>]*> 3020 1000       li      at,4096
+0+13f8 <[^>]*> 6381 a7ff       cachee  0x1c,-1\(at\)
+0+13fc <[^>]*> 3020 8000       li      at,-32768
+0+1400 <[^>]*> 03c1 0950       addu    at,at,s8
+0+1404 <[^>]*> 63a1 a600       cachee  0x1d,0\(at\)
+0+1408 <[^>]*> 3020 8000       li      at,-32768
+0+140c <[^>]*> 63e1 a600       cachee  0x1f,0\(at\)
+0+1410 <[^>]*> 5020 8000       li      at,0x8000
+0+1414 <[^>]*> 0041 0950       addu    at,at,v0
+0+1418 <[^>]*> 6001 a7ff       cachee  0x0,-1\(at\)
+0+141c <[^>]*> 5020 8000       li      at,0x8000
+0+1420 <[^>]*> 6061 a7ff       cachee  0x3,-1\(at\)
+0+1424 <[^>]*> 3020 8000       li      at,-32768
+0+1428 <[^>]*> 00a1 0950       addu    at,at,a1
+0+142c <[^>]*> 6081 a7ff       cachee  0x4,-1\(at\)
+0+1430 <[^>]*> 3020 8000       li      at,-32768
+0+1434 <[^>]*> 60c1 a7ff       cachee  0x6,-1\(at\)
+0+1438 <[^>]*> 5020 8000       li      at,0x8000
+0+143c <[^>]*> 0101 0950       addu    at,at,t0
+0+1440 <[^>]*> 60e1 a600       cachee  0x7,0\(at\)
+0+1444 <[^>]*> 5020 8000       li      at,0x8000
+0+1448 <[^>]*> 6121 a600       cachee  0x9,0\(at\)
+0+144c <[^>]*> 41a1 8000       lui     at,0x8000
+0+1450 <[^>]*> 0161 0950       addu    at,at,t3
+0+1454 <[^>]*> 6141 a600       cachee  0xa,0\(at\)
+0+1458 <[^>]*> 41a1 8000       lui     at,0x8000
+0+145c <[^>]*> 6181 a600       cachee  0xc,0\(at\)
+0+1460 <[^>]*> 41a1 8000       lui     at,0x8000
+0+1464 <[^>]*> 01c1 0950       addu    at,at,t6
+0+1468 <[^>]*> 61a1 a7ff       cachee  0xd,-1\(at\)
+0+146c <[^>]*> 41a1 8000       lui     at,0x8000
+0+1470 <[^>]*> 61e1 a7ff       cachee  0xf,-1\(at\)
+0+1474 <[^>]*> 6211 a600       cachee  0x10,0\(s1\)
+0+1478 <[^>]*> 41a1 0000       lui     at,0x0
+                       1478: R_MICROMIPS_HI16  MYDATA
+0+147c <[^>]*> 3021 0000       addiu   at,at,0
+                       147c: R_MICROMIPS_LO16  MYDATA
+0+1480 <[^>]*> 6241 a600       cachee  0x12,0\(at\)
+0+1484 <[^>]*> 6274 a500       prefe   0x13,-256\(s4\)
+0+1488 <[^>]*> 62a0 a500       prefe   0x15,-256\(zero\)
+0+148c <[^>]*> 62d7 a4ff       prefe   0x16,255\(s7\)
+0+1490 <[^>]*> 6300 a4ff       prefe   0x18,255\(zero\)
+0+1494 <[^>]*> 3020 fe00       li      at,-512
+0+1498 <[^>]*> 0341 0950       addu    at,at,k0
+0+149c <[^>]*> 6321 a4ff       prefe   0x19,255\(at\)
+0+14a0 <[^>]*> 3020 fe00       li      at,-512
+0+14a4 <[^>]*> 6361 a4ff       prefe   0x1b,255\(at\)
+0+14a8 <[^>]*> 3020 0200       li      at,512
+0+14ac <[^>]*> 03a1 0950       addu    at,at,sp
+0+14b0 <[^>]*> 6381 a500       prefe   0x1c,-256\(at\)
+0+14b4 <[^>]*> 3020 0200       li      at,512
+0+14b8 <[^>]*> 63c1 a500       prefe   0x1e,-256\(at\)
+0+14bc <[^>]*> 3020 fe00       li      at,-512
+0+14c0 <[^>]*> 63e1 a400       prefe   0x1f,0\(at\)
+0+14c4 <[^>]*> 3020 fe00       li      at,-512
+0+14c8 <[^>]*> 6041 a400       prefe   0x2,0\(at\)
+0+14cc <[^>]*> 3020 0200       li      at,512
+0+14d0 <[^>]*> 0081 0950       addu    at,at,a0
+0+14d4 <[^>]*> 6061 a5ff       prefe   0x3,-1\(at\)
+0+14d8 <[^>]*> 3020 0200       li      at,512
+0+14dc <[^>]*> 60a1 a5ff       prefe   0x5,-1\(at\)
+0+14e0 <[^>]*> 3020 fc00       li      at,-1024
+0+14e4 <[^>]*> 00e1 0950       addu    at,at,a3
+0+14e8 <[^>]*> 60c1 a400       prefe   0x6,0\(at\)
+0+14ec <[^>]*> 3020 fc00       li      at,-1024
+0+14f0 <[^>]*> 6101 a400       prefe   0x8,0\(at\)
+0+14f4 <[^>]*> 3020 0400       li      at,1024
+0+14f8 <[^>]*> 0141 0950       addu    at,at,t2
+0+14fc <[^>]*> 6121 a5ff       prefe   0x9,-1\(at\)
+0+1500 <[^>]*> 3020 0400       li      at,1024
+0+1504 <[^>]*> 6161 a5ff       prefe   0xb,-1\(at\)
+0+1508 <[^>]*> 3020 f800       li      at,-2048
+0+150c <[^>]*> 01a1 0950       addu    at,at,t5
+0+1510 <[^>]*> 6181 a400       prefe   0xc,0\(at\)
+0+1514 <[^>]*> 3020 f800       li      at,-2048
+0+1518 <[^>]*> 61c1 a400       prefe   0xe,0\(at\)
+0+151c <[^>]*> 3020 0800       li      at,2048
+0+1520 <[^>]*> 0201 0950       addu    at,at,s0
+0+1524 <[^>]*> 61e1 a5ff       prefe   0xf,-1\(at\)
+0+1528 <[^>]*> 3020 0800       li      at,2048
+0+152c <[^>]*> 6221 a5ff       prefe   0x11,-1\(at\)
+0+1530 <[^>]*> 3020 f000       li      at,-4096
+0+1534 <[^>]*> 0261 0950       addu    at,at,s3
+0+1538 <[^>]*> 6241 a400       prefe   0x12,0\(at\)
+0+153c <[^>]*> 3020 f000       li      at,-4096
+0+1540 <[^>]*> 6281 a400       prefe   0x14,0\(at\)
+0+1544 <[^>]*> 3020 1000       li      at,4096
+0+1548 <[^>]*> 02c1 0950       addu    at,at,s6
+0+154c <[^>]*> 62a1 a5ff       prefe   0x15,-1\(at\)
+0+1550 <[^>]*> 3020 1000       li      at,4096
+0+1554 <[^>]*> 62e1 a5ff       prefe   0x17,-1\(at\)
+0+1558 <[^>]*> 3020 8000       li      at,-32768
+0+155c <[^>]*> 0321 0950       addu    at,at,t9
+0+1560 <[^>]*> 6301 a400       prefe   0x18,0\(at\)
+0+1564 <[^>]*> 3020 8000       li      at,-32768
+0+1568 <[^>]*> 6341 a400       prefe   0x1a,0\(at\)
+0+156c <[^>]*> 5020 8000       li      at,0x8000
+0+1570 <[^>]*> 0381 0950       addu    at,at,gp
+0+1574 <[^>]*> 6361 a5ff       prefe   0x1b,-1\(at\)
+0+1578 <[^>]*> 5020 8000       li      at,0x8000
+0+157c <[^>]*> 63a1 a5ff       prefe   0x1d,-1\(at\)
+0+1580 <[^>]*> 3020 8000       li      at,-32768
+0+1584 <[^>]*> 03e1 0950       addu    at,at,ra
+0+1588 <[^>]*> 63c1 a5ff       prefe   0x1e,-1\(at\)
+0+158c <[^>]*> 3020 8000       li      at,-32768
+0+1590 <[^>]*> 6001 a5ff       prefe   0x0,-1\(at\)
+0+1594 <[^>]*> 5020 8000       li      at,0x8000
+0+1598 <[^>]*> 0061 0950       addu    at,at,v1
+0+159c <[^>]*> 6041 a400       prefe   0x2,0\(at\)
+0+15a0 <[^>]*> 5020 8000       li      at,0x8000
+0+15a4 <[^>]*> 6081 a400       prefe   0x4,0\(at\)
+0+15a8 <[^>]*> 41a1 8000       lui     at,0x8000
+0+15ac <[^>]*> 00c1 0950       addu    at,at,a2
+0+15b0 <[^>]*> 60a1 a400       prefe   0x5,0\(at\)
+0+15b4 <[^>]*> 41a1 8000       lui     at,0x8000
+0+15b8 <[^>]*> 60e1 a400       prefe   0x7,0\(at\)
+0+15bc <[^>]*> 41a1 8000       lui     at,0x8000
+0+15c0 <[^>]*> 0121 0950       addu    at,at,t1
+0+15c4 <[^>]*> 6101 a5ff       prefe   0x8,-1\(at\)
+0+15c8 <[^>]*> 41a1 8000       lui     at,0x8000
+0+15cc <[^>]*> 6141 a5ff       prefe   0xa,-1\(at\)
+0+15d0 <[^>]*> 616c a400       prefe   0xb,0\(t4\)
+0+15d4 <[^>]*> 41a1 0000       lui     at,0x0
+                       15d4: R_MICROMIPS_HI16  MYDATA
+0+15d8 <[^>]*> 3021 0000       addiu   at,at,0
+                       15d8: R_MICROMIPS_LO16  MYDATA
+0+15dc <[^>]*> 61a1 a400       prefe   0xd,0\(at\)

diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index e00b3f2..33ba776 100644 (file)
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -849,6 +849,8 @@ if { [istarget mips*-*-vxworks*] } {
                                        [mips_arch_list_matching mips64r2 \
                                            !micromips]
 
                                        [mips_arch_list_matching mips64r2 \
                                            !micromips]
 

+    run_dump_test_arches "eva"         [mips_arch_list_matching mips32r2 !octeon]
+

     run_list_test "illegal" "-32"
     run_list_test "baddata1" "-32"
     run_list_test "jalr" ""
     run_list_test "illegal" "-32"
     run_list_test "baddata1" "-32"
     run_list_test "jalr" ""

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index ecf4b11..4daf47b 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,30 @@
+2013-06-17  Catherine Moore  <clm@codesourcery.com>
+           Maciej W. Rozycki  <macro@codesourcery.com>
+           Chao-Ying Fu  <fu@mips.com>
+
+       * mips.h (OP_SH_EVAOFFSET): Define.
+       (OP_MASK_EVAOFFSET): Define.
+       (INSN_ASE_MASK): Delete.
+       (ASE_EVA): Define.
+       (M_CACHEE_AB, M_CACHEE_OB): New.
+       (M_LBE_OB, M_LBE_AB): New.
+       (M_LBUE_OB, M_LBUE_AB): New.
+       (M_LHE_OB, M_LHE_AB): New.
+       (M_LHUE_OB, M_LHUE_AB): New.
+       (M_LLE_AB, M_LLE_OB): New.
+       (M_LWE_OB, M_LWE_AB): New.
+       (M_LWLE_AB, M_LWLE_OB): New.
+       (M_LWRE_AB, M_LWRE_OB): New.
+       (M_PREFE_AB, M_PREFE_OB): New.
+       (M_SCE_AB, M_SCE_OB): New.
+       (M_SBE_OB, M_SBE_AB): New.
+       (M_SHE_OB, M_SHE_AB): New.
+       (M_SWE_OB, M_SWE_AB): New.
+       (M_SWLE_AB, M_SWLE_OB): New.
+       (M_SWRE_AB, M_SWRE_OB): New.
+       (MICROMIPSOP_SH_EVAOFFSET): Define.
+       (MICROMIPSOP_MASK_EVAOFFSET): Define.
+

 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 
        * nios2.h (OP_MATCH_ERET): Correct eret encoding.
 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 
        * nios2.h (OP_MATCH_ERET): Correct eret encoding.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 0bb9c11..9d241e8 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -330,6 +330,10 @@
 #define OP_MASK_IMMY           0
 #define OP_SH_IMMY             0
 
 #define OP_MASK_IMMY           0
 #define OP_SH_IMMY             0
 

+/* Enhanced VA Scheme */
+#define OP_SH_EVAOFFSET                7
+#define OP_MASK_EVAOFFSET      0x1ff
+

 /* This structure holds information for a particular instruction.  */
 
 struct mips_opcode
 /* This structure holds information for a particular instruction.  */
 
 struct mips_opcode


@@ -521,6 +525,9 @@ struct mips_opcode
    "+z" 5-bit rz register (OP_*_RZ)
    "+Z" 5-bit fz register (OP_*_FZ)
 
    "+z" 5-bit rz register (OP_*_RZ)
    "+Z" 5-bit fz register (OP_*_FZ)
 

+   Enhanced VA Scheme:
+   "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
+

    Other:
    "()" parens surrounding optional value
    ","  separates operands
    Other:
    "()" parens surrounding optional value
    ","  separates operands


@@ -537,7 +544,7 @@ struct mips_opcode
    following), for quick reference when adding more:
    "1234"
    "ABCDEFGHIJPQSTXZ"
    following), for quick reference when adding more:
    "1234"
    "ABCDEFGHIJPQSTXZ"

-   "abcpstxz"
+   "abcjpstxz"

 */
 
 /* These are the bits which may be set in the pinfo field of an
 */
 
 /* These are the bits which may be set in the pinfo field of an


@@ -733,9 +740,6 @@ static const unsigned int mips_isa_table[] =
 #define INSN_OCTEONP             0x00000200
 #define INSN_OCTEON2             0x00000100
 
 #define INSN_OCTEONP             0x00000200
 #define INSN_OCTEON2             0x00000100
 

-/* Masks used for MIPS-defined ASEs.  */
-#define INSN_ASE_MASK            0x3c00f0d0
-

 /* MIPS R5900 instruction */
 #define INSN_5900                 0x00004000
 
 /* MIPS R5900 instruction */
 #define INSN_5900                 0x00004000
 


@@ -774,6 +778,8 @@ static const unsigned int mips_isa_table[] =
 #define ASE_DSP64              0x00000002
 /* DSP R2 ASE  */
 #define ASE_DSPR2              0x00000004
 #define ASE_DSP64              0x00000002
 /* DSP R2 ASE  */
 #define ASE_DSPR2              0x00000004

+/* Enhanced VA Scheme */
+#define ASE_EVA                        0x00000008

 /* MCU (MicroController) ASE */
 #define ASE_MCU                        0x00000010
 /* MDMX ASE */
 /* MCU (MicroController) ASE */
 #define ASE_MCU                        0x00000010
 /* MDMX ASE */


@@ -1020,6 +1026,8 @@ enum
   M_BNEL_I,
   M_CACHE_AB,
   M_CACHE_OB,
   M_BNEL_I,
   M_CACHE_AB,
   M_CACHE_OB,

+  M_CACHEE_AB,
+  M_CACHEE_OB,

   M_DABS,
   M_DADD_I,
   M_DADDU_I,
   M_DABS,
   M_DADD_I,
   M_DADDU_I,


@@ -1061,8 +1069,12 @@ enum
   M_LA_AB,
   M_LB_A,
   M_LB_AB,
   M_LA_AB,
   M_LB_A,
   M_LB_AB,

+  M_LBE_OB,
+  M_LBE_AB,

   M_LBU_A,
   M_LBU_AB,
   M_LBU_A,
   M_LBU_AB,

+  M_LBUE_OB,
+  M_LBUE_AB,

   M_LCA_AB,
   M_LD_A,
   M_LD_OB,
   M_LCA_AB,
   M_LD_A,
   M_LD_OB,


@@ -1082,8 +1094,12 @@ enum
   M_LDR_OB,
   M_LH_A,
   M_LH_AB,
   M_LDR_OB,
   M_LH_A,
   M_LH_AB,

+  M_LHE_OB,
+  M_LHE_AB,

   M_LHU_A,
   M_LHU_AB,
   M_LHU_A,
   M_LHU_AB,

+  M_LHUE_OB,
+  M_LHUE_AB,

   M_LI,
   M_LI_D,
   M_LI_DD,
   M_LI,
   M_LI_D,
   M_LI_DD,


@@ -1093,10 +1109,14 @@ enum
   M_LL_OB,
   M_LLD_AB,
   M_LLD_OB,
   M_LL_OB,
   M_LLD_AB,
   M_LLD_OB,

+  M_LLE_AB,
+  M_LLE_OB,

   M_LQ_AB,
   M_LS_A,
   M_LW_A,
   M_LW_AB,
   M_LQ_AB,
   M_LS_A,
   M_LW_A,
   M_LW_AB,

+  M_LWE_OB,
+  M_LWE_AB,

   M_LWC0_A,
   M_LWC0_AB,
   M_LWC1_A,
   M_LWC0_A,
   M_LWC0_AB,
   M_LWC1_A,


@@ -1109,6 +1129,8 @@ enum
   M_LWL_A,
   M_LWL_AB,
   M_LWL_OB,
   M_LWL_A,
   M_LWL_AB,
   M_LWL_OB,

+  M_LWLE_AB,
+  M_LWLE_OB,

   M_LWM_AB,
   M_LWM_OB,
   M_LWP_AB,
   M_LWM_AB,
   M_LWM_OB,
   M_LWP_AB,


@@ -1116,6 +1138,8 @@ enum
   M_LWR_A,
   M_LWR_AB,
   M_LWR_OB,
   M_LWR_A,
   M_LWR_AB,
   M_LWR_OB,

+  M_LWRE_AB,
+  M_LWRE_OB,

   M_LWU_AB,
   M_LWU_OB,
   M_MSGSND,
   M_LWU_AB,
   M_LWU_OB,
   M_MSGSND,


@@ -1134,6 +1158,8 @@ enum
   M_OR_I,
   M_PREF_AB,
   M_PREF_OB,
   M_OR_I,
   M_PREF_AB,
   M_PREF_OB,

+  M_PREFE_AB,
+  M_PREFE_OB,

   M_REM_3,
   M_REM_3I,
   M_REMU_3,
   M_REM_3,
   M_REM_3I,
   M_REMU_3,


@@ -1158,6 +1184,8 @@ enum
   M_SC_OB,
   M_SCD_AB,
   M_SCD_OB,
   M_SC_OB,
   M_SCD_AB,
   M_SCD_OB,

+  M_SCE_AB,
+  M_SCE_OB,

   M_SD_A,
   M_SD_OB,
   M_SD_AB,
   M_SD_A,
   M_SD_OB,
   M_SD_AB,


@@ -1194,11 +1222,17 @@ enum
   M_SNE_I,
   M_SB_A,
   M_SB_AB,
   M_SNE_I,
   M_SB_A,
   M_SB_AB,

+  M_SBE_OB,
+  M_SBE_AB,

   M_SH_A,
   M_SH_AB,
   M_SH_A,
   M_SH_AB,

+  M_SHE_OB,
+  M_SHE_AB,

   M_SQ_AB,
   M_SW_A,
   M_SW_AB,
   M_SQ_AB,
   M_SW_A,
   M_SW_AB,

+  M_SWE_OB,
+  M_SWE_AB,

   M_SWC0_A,
   M_SWC0_AB,
   M_SWC1_A,
   M_SWC0_A,
   M_SWC0_AB,
   M_SWC1_A,


@@ -1211,6 +1245,8 @@ enum
   M_SWL_A,
   M_SWL_AB,
   M_SWL_OB,
   M_SWL_A,
   M_SWL_AB,
   M_SWL_OB,

+  M_SWLE_AB,
+  M_SWLE_OB,

   M_SWM_AB,
   M_SWM_OB,
   M_SWP_AB,
   M_SWM_AB,
   M_SWM_OB,
   M_SWP_AB,


@@ -1218,6 +1254,8 @@ enum
   M_SWR_A,
   M_SWR_AB,
   M_SWR_OB,
   M_SWR_A,
   M_SWR_AB,
   M_SWR_OB,

+  M_SWRE_AB,
+  M_SWRE_OB,

   M_SUB_I,
   M_SUBU_I,
   M_SUBU_I_2,
   M_SUB_I,
   M_SUBU_I,
   M_SUBU_I_2,


@@ -1638,6 +1676,10 @@ extern const int bfd_mips16_num_opcodes;
 #define MICROMIPSOP_SH_FZ              0
 #define MICROMIPSOP_MASK_FZ            0
 
 #define MICROMIPSOP_SH_FZ              0
 #define MICROMIPSOP_MASK_FZ            0
 

+/* microMIPS Enhanced VA Scheme */
+#define MICROMIPSOP_SH_EVAOFFSET       0
+#define MICROMIPSOP_MASK_EVAOFFSET     0x1ff
+

 /* These are the characters which may appears in the args field of a microMIPS
    instruction.  They appear in the order in which the fields appear
    when the instruction is used.  Commas and parentheses in the args
 /* These are the characters which may appears in the args field of a microMIPS
    instruction.  They appear in the order in which the fields appear
    when the instruction is used.  Commas and parentheses in the args


@@ -1795,6 +1837,9 @@ extern const int bfd_mips16_num_opcodes;
    "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
    "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
 
    "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
    "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
 

+   microMIPS Enhanced VA Scheme:
+   "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
+

    Other:
    "()" parens surrounding optional value
    ","  separates operands
    Other:
    "()" parens surrounding optional value
    ","  separates operands


@@ -1809,7 +1854,7 @@ extern const int bfd_mips16_num_opcodes;
 
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
 
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:

-   ""
+   "j"

    ""
    "ABCDEFGHI"
    ""
    ""
    "ABCDEFGHI"
    ""

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 79d289a..d1b106e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,17 @@
+2013-06-17  Catherine Moore  <clm@codesourcery.com>
+           Maciej W. Rozycki  <macro@codesourcery.com>
+           Chao-Ying Fu  <fu@mips.com>
+
+       * micromips-opc.c (EVA): Define.
+       (TLBINV): Define.
+       (micromips_opcodes): Add EVA opcodes.
+       * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
+       (print_insn_args): Handle EVA offsets.
+       (print_insn_micromips): Likewise.
+       * mips-opc.c (EVA): Define.
+       (TLBINV): Define.
+       (mips_builtin_opcodes): Add EVA opcodes.
+

 2013-06-17  Alan Modra  <amodra@gmail.com>
 
        * Makefile.am (mips-opc.lo): Add rules to create automatic
 2013-06-17  Alan Modra  <amodra@gmail.com>
 
        * Makefile.am (mips-opc.lo): Add rules to create automatic

diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 605384c..34e7b12 100644 (file)
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -110,6 +110,12 @@
 /* MIPS MCU (MicroController) ASE support.  */
 #define MC     ASE_MCU
 
 /* MIPS MCU (MicroController) ASE support.  */
 #define MC     ASE_MCU
 

+/* MIPS Enhanced VA Scheme.  */
+#define EVA    ASE_EVA
+
+/* TLB invalidate instruction support.  */
+#define TLBINV ASE_EVA
+

 /* MIPS Virtualization ASE.  */
 #define IVIRT  ASE_VIRT
 #define IVIRT64        ASE_VIRT64
 /* MIPS Virtualization ASE.  */
 #define IVIRT  ASE_VIRT
 #define IVIRT64        ASE_VIRT64


@@ -955,6 +961,8 @@ const struct mips_opcode micromips_opcodes[] =
 {"tgeu",    "s,t,|",   0x0000043c, 0xfc000fff, RD_s|RD_t|TRAP,         0,              I1      },
 {"tgeu",    "s,j",     0x41600000, 0xffe00000, RD_s|TRAP,              0,              I1      }, /* tgeiu */
 {"tgeu",    "s,I",     0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I1      },
 {"tgeu",    "s,t,|",   0x0000043c, 0xfc000fff, RD_s|RD_t|TRAP,         0,              I1      },
 {"tgeu",    "s,j",     0x41600000, 0xffe00000, RD_s|TRAP,              0,              I1      }, /* tgeiu */
 {"tgeu",    "s,I",     0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I1      },

+{"tlbinv",  "",                0x0000437c, 0xffffffff, INSN_TLB,               0,              0,      TLBINV  },
+{"tlbinvf", "",                0x0000537c, 0xffffffff, INSN_TLB,               0,              0,      TLBINV  },

 {"tlbginv", "",                0x0000417c, 0xffffffff, INSN_TLB,               0,              0,      IVIRT   },
 {"tlbginvf","",                0x0000517c, 0xffffffff, INSN_TLB,               0,              0,      IVIRT   },
 {"tlbgp",   "",                0x0000017c, 0xffffffff, INSN_TLB,               0,              0,      IVIRT   },
 {"tlbginv", "",                0x0000417c, 0xffffffff, INSN_TLB,               0,              0,      IVIRT   },
 {"tlbginvf","",                0x0000517c, 0xffffffff, INSN_TLB,               0,              0,      IVIRT   },
 {"tlbgp",   "",                0x0000017c, 0xffffffff, INSN_TLB,               0,              0,      IVIRT   },


@@ -1007,6 +1015,55 @@ const struct mips_opcode micromips_opcodes[] =
 {"xor",     "d,v,t",   0x00000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1      },
 {"xori",    "t,r,i",   0x70000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
 {"xor",     "d,v,t",   0x00000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1      },
 {"xori",    "t,r,i",   0x70000000, 0xfc000000, WR_t|RD_s,              0,              I1      },

+/* microMIPS Enhanced VA Scheme */
+{"lbue",   "t,+j(b)",  0x60006000, 0xfc00fe00, RD_b|WR_t,      0,      0,      EVA     },
+{"lbue",   "t,o(b)",   0,    (int) M_LBUE_OB,  INSN_MACRO,     0,      0,      EVA     },
+{"lbue",   "t,A(b)",   0,    (int) M_LBUE_AB,  INSN_MACRO,     0,      0,      EVA     },
+{"lhue",   "t,+j(b)",  0x60006200, 0xfc00fe00, RD_b|WR_t,      0,      0,      EVA     },
+{"lhue",   "t,o(b)",   0,    (int) M_LHUE_OB,  INSN_MACRO,     0,      0,      EVA     },
+{"lhue",   "t,A(b)",   0,    (int) M_LHUE_AB,  INSN_MACRO,     0,      0,      EVA     },
+{"lbe",    "t,+j(b)",  0x60006800, 0xfc00fe00, RD_b|WR_t,      0,      0,      EVA     },
+{"lbe",    "t,o(b)",   0,    (int) M_LBE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"lbe",    "t,A(b)",   0,    (int) M_LBE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"lhe",    "t,+j(b)",  0x60006a00, 0xfc00fe00, RD_b|WR_t,      0,      0,      EVA     },
+{"lhe",    "t,o(b)",   0,    (int) M_LHE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"lhe",    "t,A(b)",   0,    (int) M_LHE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"lle",    "t,+j(b)",  0x60006c00, 0xfc00fe00, RD_b|WR_t,      0,      0,      EVA     },
+{"lle",    "t,o(b)",   0,    (int) M_LLE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"lle",    "t,A(b)",   0,    (int) M_LLE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"lwe",    "t,+j(b)",  0x60006e00, 0xfc00fe00, RD_b|WR_t,      0,      0,      EVA     },
+{"lwe",    "t,o(b)",   0,    (int) M_LWE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"lwe",    "t,A(b)",   0,    (int) M_LWE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"lwle",   "t,+j(b)",  0x60006400, 0xfc00fe00, RD_b|WR_t,      0,      0,      EVA     },
+{"lwle",   "t,o(b)",   0,    (int) M_LWLE_OB,  INSN_MACRO,     0,      0,      EVA     },
+{"lwle",   "t,A(b)",   0,    (int) M_LWLE_AB,  INSN_MACRO,     0,      0,      EVA     },
+{"lwre",   "t,+j(b)",  0x60006600, 0xfc00fe00, RD_b|WR_t,      0,      0,      EVA     },
+{"lwre",   "t,o(b)",   0,    (int) M_LWRE_OB,  INSN_MACRO,     0,      0,      EVA     },
+{"lwre",   "t,A(b)",   0,    (int) M_LWRE_AB,  INSN_MACRO,     0,      0,      EVA     },
+{"sbe",    "t,+j(b)",  0x6000a800, 0xfc00fe00, SM|RD_b|WR_t,   0,      0,      EVA     },
+{"sbe",    "t,o(b)",   0,    (int) M_SBE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"sbe",    "t,A(b)",   0,    (int) M_SBE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"sce",    "t,+j(b)",  0x6000ac00, 0xfc00fe00, SM|RD_t|WR_t|RD_b,      0,      0,      EVA     },
+{"sce",    "t,o(b)",   0,    (int) M_SCE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"sce",    "t,A(b)",   0,    (int) M_SCE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"she",    "t,+j(b)",  0x6000aa00, 0xfc00fe00, SM|RD_b|WR_t,   0,      0,      EVA     },
+{"she",    "t,o(b)",   0,    (int) M_SHE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"she",    "t,A(b)",   0,    (int) M_SHE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"swe",    "t,+j(b)",  0x6000ae00, 0xfc00fe00, SM|RD_b|WR_t,   0,      0,      EVA     },
+{"swe",    "t,o(b)",   0,    (int) M_SWE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"swe",    "t,A(b)",   0,    (int) M_SWE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"swle",   "t,+j(b)",  0x6000a000, 0xfc00fe00, SM|RD_b|WR_t,   0,      0,      EVA     },
+{"swle",   "t,o(b)",   0,    (int) M_SWLE_OB,  INSN_MACRO,     0,      0,      EVA     },
+{"swle",   "t,A(b)",   0,    (int) M_SWLE_AB,  INSN_MACRO,     0,      0,      EVA     },
+{"swre",   "t,+j(b)",  0x6000a200, 0xfc00fe00, SM|RD_b|WR_t,   0,      0,      EVA     },
+{"swre",   "t,o(b)",   0,    (int) M_SWRE_OB,  INSN_MACRO,     0,      0,      EVA     },
+{"swre",   "t,A(b)",   0,    (int) M_SWRE_AB,  INSN_MACRO,     0,      0,      EVA     },
+{"cachee", "k,+j(b)",  0x6000a600, 0xfc00fe00, RD_b,           0,      0,      EVA     },
+{"cachee", "k,o(b)",   0,    (int) M_CACHEE_OB,INSN_MACRO,     0,      0,      EVA     },
+{"cachee", "k,A(b)",   0,    (int) M_CACHEE_AB,INSN_MACRO,     0,      0,      EVA     },
+{"prefe",  "k,+j(b)",  0x6000a400, 0xfc00fe00, RD_b,           0,      0,      EVA     },
+{"prefe",  "k,o(b)",   0,    (int) M_PREFE_OB, INSN_MACRO,     0,      0,      EVA     },
+{"prefe",  "k,A(b)",   0,    (int) M_PREFE_AB, INSN_MACRO,     0,      0,      EVA     },

 /* MIPS DSP ASE.  */
 {"absq_s.ph", "t,s",   0x0000113c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
 {"absq_s.w", "t,s",    0x0000213c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
 /* MIPS DSP ASE.  */
 {"absq_s.ph", "t,s",   0x0000113c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },
 {"absq_s.w", "t,s",    0x0000213c, 0xfc00ffff, WR_t|RD_s,              0,              0,      D32     },

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index bf1ef40..db8dac4 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -591,8 +591,8 @@ const struct mips_arch_choice mips_arch_choices[] =
 
   { "mips32r2",        1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
     ISA_MIPS32R2,
 
   { "mips32r2",        1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
     ISA_MIPS32R2,

-    (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_MIPS3D | ASE_MT
-     | ASE_MCU | ASE_VIRT),
+    (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
+     | ASE_MT | ASE_MCU | ASE_VIRT),

     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_hwr_names_mips3264r2 },
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_hwr_names_mips3264r2 },


@@ -606,8 +606,8 @@ const struct mips_arch_choice mips_arch_choices[] =
 
   { "mips64r2",        1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
     ISA_MIPS64R2,
 
   { "mips64r2",        1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
     ISA_MIPS64R2,

-    (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_MT | ASE_MDMX
-     | ASE_MCU | ASE_VIRT | ASE_VIRT64),
+    (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
+     | ASE_MDMX | ASE_MCU | ASE_VIRT | ASE_VIRT64),

     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_hwr_names_mips3264r2 },
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_hwr_names_mips3264r2 },


@@ -1152,6 +1152,10 @@ print_insn_args (const char *d,
              infprintf (is, "%s", mips_fpr_names[GET_OP (l, FZ)]);
              break;
 
              infprintf (is, "%s", mips_fpr_names[GET_OP (l, FZ)]);
              break;
 

+           case 'j':   /* 9-bit signed offset in bit 7.  */
+             infprintf (is, "%d", GET_OP_S (l, EVAOFFSET));
+             break;
+

            default:
              /* xgettext:c-format */
              infprintf (is,
            default:
              /* xgettext:c-format */
              infprintf (is,


@@ -2659,6 +2663,11 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
                      infprintf (is, "0x%x", msbd + 1);
                      break;
 
                      infprintf (is, "0x%x", msbd + 1);
                      break;
 

+                   case 'j':   /* 9-bit signed offset in bit 0. */
+                     delta = GET_OP_S (insn, EVAOFFSET);
+                     infprintf (is, "%d", delta);
+                     break;
+

                    default:
                      /* xgettext:c-format */
                      infprintf (is,
                    default:
                      /* xgettext:c-format */
                      infprintf (is,

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index fcfa020..d12701b 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -194,6 +194,12 @@
 /* MIPS MCU (MicroController) ASE support.  */
 #define MC     ASE_MCU
 
 /* MIPS MCU (MicroController) ASE support.  */
 #define MC     ASE_MCU
 

+/* MIPS Enhanced VA Scheme.  */
+#define EVA    ASE_EVA
+
+/* TLB invalidate instruction support.  */
+#define TLBINV ASE_EVA
+

 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the


@@ -1640,6 +1646,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tgeu",    "s,t,q",   0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
 {"tgeu",    "s,j",     0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgeiu */
 {"tgeu",    "s,I",     0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I2      },
 {"tgeu",    "s,t,q",   0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
 {"tgeu",    "s,j",     0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgeiu */
 {"tgeu",    "s,I",     0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I2      },

+{"tlbinv",  "",         0x42000003, 0xffffffff, INSN_TLB,              0,              0,      TLBINV  },
+{"tlbinvf", "",         0x42000004, 0xffffffff, INSN_TLB,              0,              0,      TLBINV  },

 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,              0,              I1      },
 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,              0,              I1      },
 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,              0,              I1      },
 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,              0,              I1      },
 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,              0,              I1      },
 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,              0,              I1      },


@@ -2296,6 +2304,55 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"punpcklwd",  "D,S,T",        0x4b80000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"sequ",       "S,T",          0x46800032,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
 {"sequ",       "S,T",          0x4b80000c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F|IL3A       },
 {"punpcklwd",  "D,S,T",        0x4b80000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"sequ",       "S,T",          0x46800032,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
 {"sequ",       "S,T",          0x4b80000c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F|IL3A       },

+/* MIPS Enhanced VA Scheme */
+{"lbue",   "t,+j(b)",  0x7c000028, 0xfc00007f, LDD|RD_b|WR_t,  0,      0,      EVA     },
+{"lbue",   "t,o(b)",   0,    (int) M_LBUE_OB,  INSN_MACRO,     0,      0,      EVA     },
+{"lbue",   "t,A(b)",   0,    (int) M_LBUE_AB,  INSN_MACRO,     0,      0,      EVA     },
+{"lhue",   "t,+j(b)",  0x7c000029, 0xfc00007f, LDD|RD_b|WR_t,  0,      0,      EVA     },
+{"lhue",   "t,o(b)",   0,    (int) M_LHUE_OB,  INSN_MACRO,     0,      0,      EVA     },
+{"lhue",   "t,A(b)",   0,    (int) M_LHUE_AB,  INSN_MACRO,     0,      0,      EVA     },
+{"lbe",    "t,+j(b)",  0x7c00002c, 0xfc00007f, LDD|RD_b|WR_t,  0,      0,      EVA     },
+{"lbe",    "t,o(b)",   0,    (int) M_LBE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"lbe",    "t,A(b)",   0,    (int) M_LBE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"lhe",    "t,+j(b)",  0x7c00002d, 0xfc00007f, LDD|RD_b|WR_t,  0,      0,      EVA     },
+{"lhe",    "t,o(b)",   0,    (int) M_LHE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"lhe",    "t,A(b)",   0,    (int) M_LHE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"lle",    "t,+j(b)",  0x7c00002e, 0xfc00007f, LDD|RD_b|WR_t,  0,      0,      EVA     },
+{"lle",    "t,o(b)",   0,    (int) M_LLE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"lle",    "t,A(b)",   0,    (int) M_LLE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"lwe",    "t,+j(b)",  0x7c00002f, 0xfc00007f, LDD|RD_b|WR_t,  0,      0,      EVA     },
+{"lwe",    "t,o(b)",   0,    (int) M_LWE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"lwe",    "t,A(b)",   0,    (int) M_LWE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"lwle",   "t,+j(b)",  0x7c000019, 0xfc00007f, LDD|RD_b|WR_t,  0,      0,      EVA     },
+{"lwle",   "t,o(b)",   0,    (int) M_LWLE_OB,  INSN_MACRO,     0,      0,      EVA     },
+{"lwle",   "t,A(b)",   0,    (int) M_LWLE_AB,  INSN_MACRO,     0,      0,      EVA     },
+{"lwre",   "t,+j(b)",  0x7c00001a, 0xfc00007f, LDD|RD_b|WR_t,  0,      0,      EVA     },
+{"lwre",   "t,o(b)",   0,    (int) M_LWRE_OB,  INSN_MACRO,     0,      0,      EVA     },
+{"lwre",   "t,A(b)",   0,    (int) M_LWRE_AB,  INSN_MACRO,     0,      0,      EVA     },
+{"sbe",    "t,+j(b)",  0x7c00001c, 0xfc00007f, SM|RD_t|RD_b,   0,      0,      EVA     },
+{"sbe",    "t,o(b)",   0,    (int) M_SBE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"sbe",    "t,A(b)",   0,    (int) M_SBE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"sce",    "t,+j(b)",  0x7c00001e, 0xfc00007f, SM|RD_t|WR_t|RD_b,      0,      0,      EVA     },
+{"sce",    "t,o(b)",   0,    (int) M_SCE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"sce",    "t,A(b)",   0,    (int) M_SCE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"she",    "t,+j(b)",  0x7c00001d, 0xfc00007f, SM|RD_t|RD_b,   0,      0,      EVA     },
+{"she",    "t,o(b)",   0,    (int) M_SHE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"she",    "t,A(b)",   0,    (int) M_SHE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"swe",    "t,+j(b)",  0x7c00001f, 0xfc00007f, SM|RD_t|RD_b,   0,      0,      EVA     },
+{"swe",    "t,o(b)",   0,    (int) M_SWE_OB,   INSN_MACRO,     0,      0,      EVA     },
+{"swe",    "t,A(b)",   0,    (int) M_SWE_AB,   INSN_MACRO,     0,      0,      EVA     },
+{"swle",   "t,+j(b)",  0x7c000021, 0xfc00007f, SM|RD_t|RD_b,   0,      0,      EVA     },
+{"swle",   "t,o(b)",   0,    (int) M_SWLE_OB,  INSN_MACRO,     0,      0,      EVA     },
+{"swle",   "t,A(b)",   0,    (int) M_SWLE_AB,  INSN_MACRO,     0,      0,      EVA     },
+{"swre",   "t,+j(b)",  0x7c000022, 0xfc00007f, SM|RD_t|RD_b,   0,      0,      EVA     },
+{"swre",   "t,o(b)",   0,    (int) M_SWRE_OB,  INSN_MACRO,     0,      0,      EVA     },
+{"swre",   "t,A(b)",   0,    (int) M_SWRE_AB,  INSN_MACRO,     0,      0,      EVA     },
+{"cachee", "k,+j(b)",  0x7c00001b, 0xfc00007f, RD_b,           0,      0,      EVA     },
+{"cachee", "k,o(b)",   0,    (int) M_CACHEE_OB,INSN_MACRO,     0,      0,      EVA     },
+{"cachee", "k,A(b)",   0,    (int) M_CACHEE_AB,INSN_MACRO,     0,      0,      EVA     },
+{"prefe",  "k,+j(b)",  0x7c000023, 0xfc00007f, RD_b,           0,      0,      EVA     },
+{"prefe",  "k,o(b)",   0,    (int) M_PREFE_OB, INSN_MACRO,     0,      0,      EVA     },
+{"prefe",  "k,A(b)",   0,    (int) M_PREFE_AB, INSN_MACRO,     0,      0,      EVA     },

 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the