mailbox: imx: fix RST channel support

Because IMX_MU_xCR_MAX was increased to 5, some mu cfgs were not updated
to include the CR register. Add the missed CR register to xcr array.

Fixes: 82ab513baed5 ("mailbox: imx: support RST channel")
Reported-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Liu Ying <victor.liu@nxp.com> # i.MX8qm/qxp MEK boards boot
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index 0292207..20f2ec8 100644 (file)
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -904,7 +904,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
        .xTR    = 0x20,
        .xRR    = 0x40,
        .xSR    = {0x60, 0x60, 0x60, 0x60},
        .xTR    = 0x20,
        .xRR    = 0x40,
        .xSR    = {0x60, 0x60, 0x60, 0x60},

-       .xCR    = {0x64, 0x64, 0x64, 0x64},
+       .xCR    = {0x64, 0x64, 0x64, 0x64, 0x64},

 };
 
 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
 };
 
 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {


@@ -927,7 +927,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
        .xTR    = 0x200,
        .xRR    = 0x280,
        .xSR    = {0xC, 0x118, 0x124, 0x12C},
        .xTR    = 0x200,
        .xRR    = 0x280,
        .xSR    = {0xC, 0x118, 0x124, 0x12C},

-       .xCR    = {0x110, 0x114, 0x120, 0x128},
+       .xCR    = {0x8, 0x110, 0x114, 0x120, 0x128},

 };
 
 static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
 };
 
 static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {


@@ -938,7 +938,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
        .xTR    = 0x200,
        .xRR    = 0x280,
        .xSR    = {0xC, 0x118, 0x124, 0x12C},
        .xTR    = 0x200,
        .xRR    = 0x280,
        .xSR    = {0xC, 0x118, 0x124, 0x12C},

-       .xCR    = {0x110, 0x114, 0x120, 0x128},
+       .xCR    = {0x8, 0x110, 0x114, 0x120, 0x128},

 };
 
 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
 };
 
 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {


@@ -949,7 +949,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
        .xTR    = 0x0,
        .xRR    = 0x10,
        .xSR    = {0x20, 0x20, 0x20, 0x20},
        .xTR    = 0x0,
        .xRR    = 0x10,
        .xSR    = {0x20, 0x20, 0x20, 0x20},

-       .xCR    = {0x24, 0x24, 0x24, 0x24},
+       .xCR    = {0x24, 0x24, 0x24, 0x24, 0x24},

 };
 
 static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
 };
 
 static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {


@@ -960,7 +960,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
        .xTR    = 0x0,
        .xRR    = 0x10,
        .xSR    = {0x20, 0x20, 0x20, 0x20},
        .xTR    = 0x0,
        .xRR    = 0x10,
        .xSR    = {0x20, 0x20, 0x20, 0x20},

-       .xCR    = {0x24, 0x24, 0x24, 0x24},
+       .xCR    = {0x24, 0x24, 0x24, 0x24, 0x24},

 };
 
 static const struct of_device_id imx_mu_dt_ids[] = {
 };
 
 static const struct of_device_id imx_mu_dt_ids[] = {