- radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
- radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
- radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
- radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
- radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
- radeon_ring_write(rdev, 0);
- radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
- radeon_ring_write(rdev, 0);
- radeon_ring_write(rdev, PACKET0(R500_SU_REG_DEST, 0));
- radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
- radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
- radeon_ring_write(rdev, 0);
- radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
- radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
- radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
- radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
- radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
- radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
- radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
- radeon_ring_write(rdev, 0);
- radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
- radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
- radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
- radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
- radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
- radeon_ring_write(rdev,
+ radeon_ring_write(cp, PACKET0(WAIT_UNTIL, 0));
+ radeon_ring_write(cp, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
+ radeon_ring_write(cp, PACKET0(R300_DST_PIPE_CONFIG, 0));
+ radeon_ring_write(cp, R300_PIPE_AUTO_CONFIG);
+ radeon_ring_write(cp, PACKET0(GB_SELECT, 0));
+ radeon_ring_write(cp, 0);
+ radeon_ring_write(cp, PACKET0(GB_ENABLE, 0));
+ radeon_ring_write(cp, 0);
+ radeon_ring_write(cp, PACKET0(R500_SU_REG_DEST, 0));
+ radeon_ring_write(cp, (1 << rdev->num_gb_pipes) - 1);
+ radeon_ring_write(cp, PACKET0(VAP_INDEX_OFFSET, 0));
+ radeon_ring_write(cp, 0);
+ radeon_ring_write(cp, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
+ radeon_ring_write(cp, RB3D_DC_FLUSH | RB3D_DC_FREE);
+ radeon_ring_write(cp, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
+ radeon_ring_write(cp, ZC_FLUSH | ZC_FREE);
+ radeon_ring_write(cp, PACKET0(WAIT_UNTIL, 0));
+ radeon_ring_write(cp, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
+ radeon_ring_write(cp, PACKET0(GB_AA_CONFIG, 0));
+ radeon_ring_write(cp, 0);
+ radeon_ring_write(cp, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
+ radeon_ring_write(cp, RB3D_DC_FLUSH | RB3D_DC_FREE);
+ radeon_ring_write(cp, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
+ radeon_ring_write(cp, ZC_FLUSH | ZC_FREE);
+ radeon_ring_write(cp, PACKET0(GB_MSPOS0, 0));
+ radeon_ring_write(cp,