* gas/config/tc-arm.c (NEON_ENC_TAB): Add vmaxnm, vminnm entries.

	(vfp_or_neon_is_neon_bits): Add NEON_CHECK_ARCH8 enumerator.
	(vfp_or_neon_is_neon): Add check for SIMD for ARMv8.
	(do_maxnm): New function.
	(insns): Add vmaxnm, vminnm entries.
	* gas/testsuite/gas/testsuite/gas/armv8-a+fp.d: Update testcase.
	* gas/testsuite/gas/testsuite/gas/armv8-a+fp.s: Likewise.
	* gas/testsuite/gas/testsuite/gas/armv8-a+simd.d: New testcase.
	* gas/testsuite/gas/testsuite/gas/armv8-a+simd.s: Likewise.
	* opcodes/arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
	(neon_opcodes): Likewise.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index f717360..249205f 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,13 @@
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 

+       * config/tc-arm.c (NEON_ENC_TAB): Add vmaxnm, vminnm entries.
+       (vfp_or_neon_is_neon_bits): Add NEON_CHECK_ARCH8 enumerator.
+       (vfp_or_neon_is_neon): Add check for SIMD for ARMv8.
+       (do_maxnm): New function.
+       (insns): Add vmaxnm, vminnm entries.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+

        * config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL.
        (NEON_ENC_FPV8_): New define.
        (do_vfp_nsyn_fpv8): New function.
        * config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL.
        (NEON_ENC_FPV8_): New define.
        (do_vfp_nsyn_fpv8): New function.

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 5612d7e..4c46abc 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12345,7 +12345,9 @@ struct neon_tab_entry
   X(vseleq,    0xe000a00, N_INV,     N_INV),           \
   X(vselvs,    0xe100a00, N_INV,     N_INV),           \
   X(vselge,    0xe200a00, N_INV,     N_INV),           \
   X(vseleq,    0xe000a00, N_INV,     N_INV),           \
   X(vselvs,    0xe100a00, N_INV,     N_INV),           \
   X(vselge,    0xe200a00, N_INV,     N_INV),           \

-  X(vselgt,    0xe300a00, N_INV,     N_INV)
+  X(vselgt,    0xe300a00, N_INV,     N_INV),           \
+  X(vmaxnm,    0xe800a00, 0x3000f10, N_INV),           \
+  X(vminnm,    0xe800a40, 0x3200f10, N_INV)

 
 enum neon_opc
 {
 
 enum neon_opc
 {


@@ -13982,7 +13984,8 @@ do_neon_dyadic_if_i_d (void)
 enum vfp_or_neon_is_neon_bits
 {
   NEON_CHECK_CC = 1,
 enum vfp_or_neon_is_neon_bits
 {
   NEON_CHECK_CC = 1,

-  NEON_CHECK_ARCH = 2
+  NEON_CHECK_ARCH = 2,
+  NEON_CHECK_ARCH8 = 4

 };
 
 /* Call this function if an instruction which may have belonged to the VFP or
 };
 
 /* Call this function if an instruction which may have belonged to the VFP or


@@ -14020,7 +14023,14 @@ vfp_or_neon_is_neon (unsigned check)
     }
 
   if ((check & NEON_CHECK_ARCH)
     }
 
   if ((check & NEON_CHECK_ARCH)

-      && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
+      && !mark_feature_used (&fpu_neon_ext_v1))
+    {
+      first_error (_(BAD_FPU));
+      return FAIL;
+    }
+
+  if ((check & NEON_CHECK_ARCH8)
+      && !mark_feature_used (&fpu_neon_ext_armv8))

     {
       first_error (_(BAD_FPU));
       return FAIL;
     {
       first_error (_(BAD_FPU));
       return FAIL;


@@ -15874,6 +15884,20 @@ do_vsel (void)
     first_error (_("invalid instruction shape"));
 }
 
     first_error (_("invalid instruction shape"));
 }
 

+static void
+do_vmaxnm (void)
+{
+  set_it_insn_type (OUTSIDE_IT_INSN);
+
+  if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
+    return;
+
+  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
+    return;
+
+  neon_dyadic_misc (NT_untyped, N_F32, 0);
+}
+

 \f
 /* Overall per-instruction processing. */
 
 \f
 /* Overall per-instruction processing. */
 


@@ -18087,6 +18111,8 @@ static const struct asm_opcode insns[] =
   nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD),          vsel),
   nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD),          vsel),
   nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD),          vsel),
   nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD),          vsel),
   nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD),          vsel),
   nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD),          vsel),

+  nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ),      vmaxnm),
+  nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ),      vmaxnm),

 
 #undef  ARM_VARIANT
 #define ARM_VARIANT  & fpu_fpa_ext_v1  /* Core FPA instruction set (V1).  */
 
 #undef  ARM_VARIANT
 #define ARM_VARIANT  & fpu_fpa_ext_v1  /* Core FPA instruction set (V1).  */

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index f6f111f..11bae09 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,12 @@
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 

+       * gas/testsuite/gas/armv8-a+fp.d: Update testcase.
+       * gas/testsuite/gas/armv8-a+fp.s: Likewise.
+       * gas/testsuite/gas/armv8-a+simd.d: New testcase.
+       * gas/testsuite/gas/armv8-a+simd.s: Likewise.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+

        * gas/arm/armv8-a+fp.d: New testcase.
        * gas/arm/armv8-a+fp.s: Likewise.
 
        * gas/arm/armv8-a+fp.d: New testcase.
        * gas/arm/armv8-a+fp.s: Likewise.
 

diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d
index 568d317..c902874 100644 (file)
--- a/gas/testsuite/gas/arm/armv8-a+fp.d
+++ b/gas/testsuite/gas/arm/armv8-a+fp.d
@@ -12,6 +12,22 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> fe500ba0    vselvs.f64      d16, d16, d16
 0[0-9a-f]+ <[^>]+> fe2ffb0f    vselge.f64      d15, d15, d15
 0[0-9a-f]+ <[^>]+> fe7ffbaf    vselgt.f64      d31, d31, d31
 0[0-9a-f]+ <[^>]+> fe500ba0    vselvs.f64      d16, d16, d16
 0[0-9a-f]+ <[^>]+> fe2ffb0f    vselge.f64      d15, d15, d15
 0[0-9a-f]+ <[^>]+> fe7ffbaf    vselgt.f64      d31, d31, d31

+0[0-9a-f]+ <[^>]+> fe800a00    vmaxnm.f32      s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec00aa0    vmaxnm.f32      s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8ffa0f    vmaxnm.f32      s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecffaaf    vmaxnm.f32      s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe800b00    vmaxnm.f64      d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec00ba0    vmaxnm.f64      d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8ffb0f    vmaxnm.f64      d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecffbaf    vmaxnm.f64      d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe800a40    vminnm.f32      s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec00ae0    vminnm.f32      s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8ffa4f    vminnm.f32      s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecffaef    vminnm.f32      s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe800b40    vminnm.f64      d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec00be0    vminnm.f64      d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8ffb4f    vminnm.f64      d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecffbef    vminnm.f64      d31, d31, d31

 0[0-9a-f]+ <[^>]+> fe00 0a00   vseleq.f32      s0, s0, s0
 0[0-9a-f]+ <[^>]+> fe50 0aa0   vselvs.f32      s1, s1, s1
 0[0-9a-f]+ <[^>]+> fe2f fa0f   vselge.f32      s30, s30, s30
 0[0-9a-f]+ <[^>]+> fe00 0a00   vseleq.f32      s0, s0, s0
 0[0-9a-f]+ <[^>]+> fe50 0aa0   vselvs.f32      s1, s1, s1
 0[0-9a-f]+ <[^>]+> fe2f fa0f   vselge.f32      s30, s30, s30


@@ -20,3 +36,19 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> fe50 0ba0   vselvs.f64      d16, d16, d16
 0[0-9a-f]+ <[^>]+> fe2f fb0f   vselge.f64      d15, d15, d15
 0[0-9a-f]+ <[^>]+> fe7f fbaf   vselgt.f64      d31, d31, d31
 0[0-9a-f]+ <[^>]+> fe50 0ba0   vselvs.f64      d16, d16, d16
 0[0-9a-f]+ <[^>]+> fe2f fb0f   vselge.f64      d15, d15, d15
 0[0-9a-f]+ <[^>]+> fe7f fbaf   vselgt.f64      d31, d31, d31

+0[0-9a-f]+ <[^>]+> fe80 0a00   vmaxnm.f32      s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0aa0   vmaxnm.f32      s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa0f   vmaxnm.f32      s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faaf   vmaxnm.f32      s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b00   vmaxnm.f64      d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec0 0ba0   vmaxnm.f64      d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8f fb0f   vmaxnm.f64      d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecf fbaf   vmaxnm.f64      d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe80 0a40   vminnm.f32      s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0ae0   vminnm.f32      s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa4f   vminnm.f32      s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faef   vminnm.f32      s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b40   vminnm.f64      d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec0 0be0   vminnm.f64      d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8f fb4f   vminnm.f64      d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecf fbef   vminnm.f64      d31, d31, d31

diff --git a/gas/testsuite/gas/arm/armv8-a+fp.s b/gas/testsuite/gas/arm/armv8-a+fp.s
index ec79f99..e967b1a 100644 (file)
--- a/gas/testsuite/gas/arm/armv8-a+fp.s
+++ b/gas/testsuite/gas/arm/armv8-a+fp.s
@@ -12,6 +12,22 @@
        vselvs.f64      d16, d16, d16
        vselge.f64      d15, d15, d15
        vselgt.f64      d31, d31, d31
        vselvs.f64      d16, d16, d16
        vselge.f64      d15, d15, d15
        vselgt.f64      d31, d31, d31

+       vmaxnm.f32      s0, s0, s0
+       vmaxnm.f32      s1, s1, s1
+       vmaxnm.f32      s30, s30, s30
+       vmaxnm.f32      s31, s31, s31
+       vmaxnm.f64      d0, d0, d0
+       vmaxnm.f64      d16, d16, d16
+       vmaxnm.f64      d15, d15, d15
+       vmaxnm.f64      d31, d31, d31
+       vminnm.f32      s0, s0, s0
+       vminnm.f32      s1, s1, s1
+       vminnm.f32      s30, s30, s30
+       vminnm.f32      s31, s31, s31
+       vminnm.f64      d0, d0, d0
+       vminnm.f64      d16, d16, d16
+       vminnm.f64      d15, d15, d15
+       vminnm.f64      d31, d31, d31

 
        .thumb
        vseleq.f32      s0, s0, s0
 
        .thumb
        vseleq.f32      s0, s0, s0


@@ -22,3 +38,19 @@
        vselvs.f64      d16, d16, d16
        vselge.f64      d15, d15, d15
        vselgt.f64      d31, d31, d31
        vselvs.f64      d16, d16, d16
        vselge.f64      d15, d15, d15
        vselgt.f64      d31, d31, d31

+       vmaxnm.f32      s0, s0, s0
+       vmaxnm.f32      s1, s1, s1
+       vmaxnm.f32      s30, s30, s30
+       vmaxnm.f32      s31, s31, s31
+       vmaxnm.f64      d0, d0, d0
+       vmaxnm.f64      d16, d16, d16
+       vmaxnm.f64      d15, d15, d15
+       vmaxnm.f64      d31, d31, d31
+       vminnm.f32      s0, s0, s0
+       vminnm.f32      s1, s1, s1
+       vminnm.f32      s30, s30, s30
+       vminnm.f32      s31, s31, s31
+       vminnm.f64      d0, d0, d0
+       vminnm.f64      d16, d16, d16
+       vminnm.f64      d15, d15, d15
+       vminnm.f64      d31, d31, d31

diff --git a/gas/testsuite/gas/arm/armv8-a+simd.d b/gas/testsuite/gas/arm/armv8-a+simd.d
new file mode 100644 (file)
index 0000000..d194ccb
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a+simd.d
@@ -0,0 +1,38 @@
+#name: Valid v8-a+simdv3
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f3000f10    vmaxnm.f32      d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3400fb0    vmaxnm.f32      d16, d16, d16
+0[0-9a-f]+ <[^>]+> f30fff1f    vmaxnm.f32      d15, d15, d15
+0[0-9a-f]+ <[^>]+> f34fffbf    vmaxnm.f32      d31, d31, d31
+0[0-9a-f]+ <[^>]+> f3000f50    vmaxnm.f32      q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3400ff0    vmaxnm.f32      q8, q8, q8
+0[0-9a-f]+ <[^>]+> f30eef5e    vmaxnm.f32      q7, q7, q7
+0[0-9a-f]+ <[^>]+> f34eeffe    vmaxnm.f32      q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3200f10    vminnm.f32      d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3600fb0    vminnm.f32      d16, d16, d16
+0[0-9a-f]+ <[^>]+> f32fff1f    vminnm.f32      d15, d15, d15
+0[0-9a-f]+ <[^>]+> f36fffbf    vminnm.f32      d31, d31, d31
+0[0-9a-f]+ <[^>]+> f3200f50    vminnm.f32      q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3600ff0    vminnm.f32      q8, q8, q8
+0[0-9a-f]+ <[^>]+> f32eef5e    vminnm.f32      q7, q7, q7
+0[0-9a-f]+ <[^>]+> f36eeffe    vminnm.f32      q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff00 0f10   vmaxnm.f32      d0, d0, d0
+0[0-9a-f]+ <[^>]+> ff40 0fb0   vmaxnm.f32      d16, d16, d16
+0[0-9a-f]+ <[^>]+> ff0f ff1f   vmaxnm.f32      d15, d15, d15
+0[0-9a-f]+ <[^>]+> ff4f ffbf   vmaxnm.f32      d31, d31, d31
+0[0-9a-f]+ <[^>]+> ff00 0f50   vmaxnm.f32      q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff40 0ff0   vmaxnm.f32      q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff0e ef5e   vmaxnm.f32      q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff4e effe   vmaxnm.f32      q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff20 0f10   vminnm.f32      d0, d0, d0
+0[0-9a-f]+ <[^>]+> ff60 0fb0   vminnm.f32      d16, d16, d16
+0[0-9a-f]+ <[^>]+> ff2f ff1f   vminnm.f32      d15, d15, d15
+0[0-9a-f]+ <[^>]+> ff6f ffbf   vminnm.f32      d31, d31, d31
+0[0-9a-f]+ <[^>]+> ff20 0f50   vminnm.f32      q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff60 0ff0   vminnm.f32      q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff2e ef5e   vminnm.f32      q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff6e effe   vminnm.f32      q15, q15, q15

diff --git a/gas/testsuite/gas/arm/armv8-a+simd.s b/gas/testsuite/gas/arm/armv8-a+simd.s
new file mode 100644 (file)
index 0000000..f11103c
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a+simd.s
@@ -0,0 +1,39 @@
+       .syntax unified
+       .arch armv8-a
+       .arch_extension simd
+
+       .arm
+       vmaxnm.f32      d0, d0, d0
+       vmaxnm.f32      d16, d16, d16
+       vmaxnm.f32      d15, d15, d15
+       vmaxnm.f32      d31, d31, d31
+       vmaxnm.f32      q0, q0, q0
+       vmaxnm.f32      q8, q8, q8
+       vmaxnm.f32      q7, q7, q7
+       vmaxnm.f32      q15, q15, q15
+       vminnm.f32      d0, d0, d0
+       vminnm.f32      d16, d16, d16
+       vminnm.f32      d15, d15, d15
+       vminnm.f32      d31, d31, d31
+       vminnm.f32      q0, q0, q0
+       vminnm.f32      q8, q8, q8
+       vminnm.f32      q7, q7, q7
+       vminnm.f32      q15, q15, q15
+
+       .thumb
+       vmaxnm.f32      d0, d0, d0
+       vmaxnm.f32      d16, d16, d16
+       vmaxnm.f32      d15, d15, d15
+       vmaxnm.f32      d31, d31, d31
+       vmaxnm.f32      q0, q0, q0
+       vmaxnm.f32      q8, q8, q8
+       vmaxnm.f32      q7, q7, q7
+       vmaxnm.f32      q15, q15, q15
+       vminnm.f32      d0, d0, d0
+       vminnm.f32      d16, d16, d16
+       vminnm.f32      d15, d15, d15
+       vminnm.f32      d31, d31, d31
+       vminnm.f32      q0, q0, q0
+       vminnm.f32      q8, q8, q8
+       vminnm.f32      q7, q7, q7
+       vminnm.f32      q15, q15, q15

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3d5e26e..abc851c 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 

+       * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
+       (neon_opcodes): Likewise.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+

        * arm-dis.c (coprocessor_opcodes): Add VSEL.
        (print_insn_coprocessor): Add new %<>c bitfield format
        specifier.
        * arm-dis.c (coprocessor_opcodes): Add VSEL.
        (print_insn_coprocessor): Add new %<>c bitfield format
        specifier.

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 2e4b333..9757c20 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -490,6 +490,10 @@ static const struct opcode32 coprocessor_opcodes[] =
   /* FP v5.  */
   {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
   {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
   /* FP v5.  */
   {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
   {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},

+  {FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
+  {FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
+  {FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
+  {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},

 
   /* Generic coprocessor instructions.  */
   { 0, SENTINEL_GENERIC_START, 0, "" },
 
   /* Generic coprocessor instructions.  */
   { 0, SENTINEL_GENERIC_START, 0, "" },


@@ -607,6 +611,8 @@ static const struct opcode32 neon_opcodes[] =
   {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
 
   /* Three registers of the same length.  */
   {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
 
   /* Three registers of the same length.  */

+  {FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+  {FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},

   {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
   {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
   {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
   {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
   {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
   {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},