powerpc/ppc4xx: Make gdsys 405ep boards reset more generic

In order to add boards that have different hardware for fpga reset,
any 405ep gdsys board now provides these functions:

void gd405ep_init(void);
void gd405ep_set_fpga_reset(unsigned state);
void gd405ep_setup_hw(void);
int gd405ep_get_fpga_done(unsigned fpga);

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index 8b80533..bea671e 100644 (file)
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -28,12 +28,9 @@
 #include <asm/ppc4xx-gpio.h>
 #include <asm/global_data.h>
 
 #include <asm/ppc4xx-gpio.h>
 #include <asm/global_data.h>
 

+#include "405ep.h"

 #include <gdsys_fpga.h>
 
 #include <gdsys_fpga.h>
 

-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-

 #define REFLECTION_TESTPATTERN 0xdede
 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
 
 #define REFLECTION_TESTPATTERN 0xdede
 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
 


@@ -55,7 +52,6 @@ void print_fpga_state(unsigned dev)
 int board_early_init_f(void)
 {
        unsigned k;
 int board_early_init_f(void)
 {
        unsigned k;

-       unsigned ctr;

 
        for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
                gd->fpga_state[k] = 0;
 
        for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
                gd->fpga_state[k] = 0;


@@ -73,26 +69,29 @@ int board_early_init_f(void)
         * -> ca. 15 us
         */
        mtebc(EBC0_CFG, 0xa8400000);    /* ebc always driven */
         * -> ca. 15 us
         */
        mtebc(EBC0_CFG, 0xa8400000);    /* ebc always driven */

+       return 0;
+}

 
 

-       /*
-        * setup io-latches for reset
-        */
-       out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
-       out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+int board_early_init_r(void)
+{
+       unsigned k;
+       unsigned ctr;

 
 

-       /*
-        * set "startup-finished"-gpios
-        */
-       gpio_write_bit(21, 0);
-       gpio_write_bit(22, 1);
+       for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+               gd->fpga_state[k] = 0;

 
        /*
 
        /*

-        * wait for fpga-done
+        * reset FPGA

         */
         */

+       gd405ep_init();
+
+       gd405ep_set_fpga_reset(1);
+
+       gd405ep_setup_hw();
+

        for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
                ctr = 0;
        for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
                ctr = 0;

-               while (!(in_le16((void *)LATCH2_BASE)
-                       & CONFIG_SYS_FPGA_DONE(k))) {
+               while (!gd405ep_get_fpga_done(k)) {

                        udelay(100000);
                        if (ctr++ > 5) {
                                gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
                        udelay(100000);
                        if (ctr++ > 5) {
                                gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;


@@ -101,12 +100,9 @@ int board_early_init_f(void)
                }
        }
 
                }
        }
 

-       /*
-        * setup io-latches for boot (stop reset)
-        */

        udelay(10);
        udelay(10);

-       out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
-       out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+
+       gd405ep_set_fpga_reset(0);

 
        for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
                ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
 
        for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
                ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);

diff --git a/board/gdsys/405ep/405ep.h b/board/gdsys/405ep/405ep.h
new file mode 100644 (file)
index 0000000..5647dbc
--- /dev/null
+++ b/board/gdsys/405ep/405ep.h
@@ -0,0 +1,10 @@
+#ifndef __405EP_H_
+#define __405EP_H_
+
+/* functions to be provided by board implementation */
+void gd405ep_init(void);
+void gd405ep_set_fpga_reset(unsigned state);
+void gd405ep_setup_hw(void);
+int gd405ep_get_fpga_done(unsigned fpga);
+
+#endif /* __405EP_H_ */

diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
index feb5cec..38e5ea4 100644 (file)
--- a/board/gdsys/405ep/Makefile
+++ b/board/gdsys/405ep/Makefile
@@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
 
 LIB    = $(obj)lib$(BOARD).o
 

+COBJS-$(CONFIG_NEO) += neo.o

 COBJS-$(CONFIG_IO) += io.o
 COBJS-$(CONFIG_IOCON) += iocon.o
 COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
 COBJS-$(CONFIG_IO) += io.o
 COBJS-$(CONFIG_IOCON) += iocon.o
 COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o

diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index f55afbd..adaffb2 100644 (file)
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -27,15 +27,18 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 

+#include "405ep.h"

 #include <gdsys_fpga.h>
 
 #include "../common/osd.h"
 
 #include <gdsys_fpga.h>
 
 #include "../common/osd.h"
 

+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)

 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)

-#define LATCH2_MC2_PRESENT_N 0x0080
-

 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
 
 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
 

+#define LATCH2_MC2_PRESENT_N 0x0080
+

 enum {
        UNITTYPE_VIDEO_USER = 0,
        UNITTYPE_MAIN_USER = 1,
 enum {
        UNITTYPE_VIDEO_USER = 0,
        UNITTYPE_MAIN_USER = 1,


@@ -261,3 +264,32 @@ int last_stage_init(void)
 
        return 0;
 }
 
        return 0;
 }

+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+       if (state) {
+               out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+               out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+       } else {
+               out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+               out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+       }
+}
+
+void gd405ep_setup_hw(void)
+{
+       /*
+        * set "startup-finished"-gpios
+        */
+       gpio_write_bit(21, 0);
+       gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+       return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}

diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index db1ea7f..ac4cefd 100644 (file)
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -29,8 +29,13 @@
 
 #include <miiphy.h>
 
 
 #include <miiphy.h>
 

+#include "405ep.h"

 #include <gdsys_fpga.h>
 
 #include <gdsys_fpga.h>
 

+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+

 #define PHYREG_CONTROL                         0
 #define PHYREG_PAGE_ADDRESS                    22
 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1   16
 #define PHYREG_CONTROL                         0
 #define PHYREG_PAGE_ADDRESS                    22
 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1   16


@@ -175,3 +180,32 @@ int last_stage_init(void)
 
        return 0;
 }
 
        return 0;
 }

+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+       if (state) {
+               out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+               out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+       } else {
+               out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+               out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+       }
+}
+
+void gd405ep_setup_hw(void)
+{
+       /*
+        * set "startup-finished"-gpios
+        */
+       gpio_write_bit(21, 0);
+       gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+       return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}

diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index ce53340..ed27791 100644 (file)
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -27,10 +27,15 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 

+#include "405ep.h"

 #include <gdsys_fpga.h>
 
 #include "../common/osd.h"
 
 #include <gdsys_fpga.h>
 
 #include "../common/osd.h"
 

+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+

 enum {
        UNITTYPE_MAIN_SERVER = 0,
        UNITTYPE_MAIN_USER = 1,
 enum {
        UNITTYPE_MAIN_SERVER = 0,
        UNITTYPE_MAIN_USER = 1,


@@ -231,3 +236,32 @@ int fpga_gpio_get(int pin)
 {
        return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
 }
 {
        return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
 }

+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+       if (state) {
+               out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+               out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+       } else {
+               out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+               out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+       }
+}
+
+void gd405ep_setup_hw(void)
+{
+       /*
+        * set "startup-finished"-gpios
+        */
+       gpio_write_bit(21, 0);
+       gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+       return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}

diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c
new file mode 100644 (file)
index 0000000..f38edd2
--- /dev/null
+++ b/board/gdsys/405ep/neo.c
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+enum {
+       UNITTYPE_CCX16 = 1,
+       UNITTYPE_CCIP216 = 2,
+};
+
+enum {
+       HWVER_300 = 3,
+};
+
+int misc_init_r(void)
+{
+       /* startup fans */
+       dtt_init();
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       char *s = getenv("serial#");
+
+       puts("Board: CATCenter Neo");
+
+       if (s != NULL) {
+               puts(", serial# ");
+               puts(s);
+       }
+
+       puts("\n");
+
+       return 0;
+}
+
+static void print_fpga_info(void)
+{
+       ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+       u16 versions = in_le16(&fpga->versions);
+       u16 fpga_version = in_le16(&fpga->fpga_version);
+       u16 fpga_features = in_le16(&fpga->fpga_features);
+       int fpga_state = get_fpga_state(0);
+       unsigned unit_type;
+       unsigned hardware_version;
+       unsigned feature_channels;
+
+       puts("FPGA:  ");
+       if (fpga_state & FPGA_STATE_DONE_FAILED) {
+               printf(" done timed out\n");
+               return;
+       }
+
+       if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
+               printf(" refelectione test failed\n");
+               return;
+       }
+
+       unit_type = (versions & 0xf000) >> 12;
+       hardware_version = versions & 0x000f;
+       feature_channels = fpga_features & 0x007f;
+
+       switch (unit_type) {
+       case UNITTYPE_CCX16:
+               printf("CCX-Switch");
+               break;
+
+       default:
+               printf("UnitType %d(not supported)", unit_type);
+               break;
+       }
+
+       switch (hardware_version) {
+       case HWVER_300:
+               printf(" HW-Ver 3.00-3.12\n");
+               break;
+
+       default:
+               printf(" HW-Ver %d(not supported)\n",
+                      hardware_version);
+               break;
+       }
+
+       printf("       FPGA V %d.%02d, features:",
+               fpga_version / 100, fpga_version % 100);
+
+       printf(" %d channel(s)\n", feature_channels);
+}
+
+int last_stage_init(void)
+{
+       print_fpga_info();
+
+       return 0;
+}
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+       if (state) {
+               out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+               out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+       } else {
+               out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+               out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+       }
+}
+
+void gd405ep_setup_hw(void)
+{
+       /*
+        * set "startup-finished"-gpios
+        */
+       gpio_write_bit(21, 0);
+       gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+       /*
+        * Neo hardware has no FPGA-DONE GPIO
+        */
+       return 1;
+}

diff --git a/board/gdsys/neo/Makefile b/board/gdsys/neo/Makefile
deleted file mode 100644 (file)
index dc5b5b8..0000000
--- a/board/gdsys/neo/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
-COBJS  = $(BOARD).o
-SOBJS   =
-
-SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
-SOBJS  := $(addprefix $(obj),$(SOBJS))
-
-$(LIB):        $(OBJS) $(SOBJS)
-       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c
deleted file mode 100644 (file)
index d21d599..0000000
--- a/board/gdsys/neo/neo.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#define HWTYPE_CCX16   1
-#define HWREV_300      3
-
-int board_early_init_f(void)
-{
-       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
-       mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical */
-       mtdcr(UIC0PR, 0xFFFFFF80);      /* set int polarities */
-       mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
-       mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest prio */
-       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
-
-       /*
-        * EBC Configuration Register: set ready timeout to 512 ebc-clks
-        * -> ca. 15 us
-        */
-       mtebc(EBC0_CFG, 0xa8400000);    /* ebc always driven */
-
-       return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
-       char buf[64];
-       int i = getenv_f("serial#", buf, sizeof(buf));
-       u16 val = in_le16((void *)CONFIG_FPGA_BASE + 2);
-       u8 unit_type;
-       u8 hardware_cpu_ports;
-       u8 hardware_con_ports;
-       u8 hardware_version;
-
-       printf("Board: CATCenter Neo");
-
-       if (i > 0) {
-               puts(", serial# ");
-               puts(buf);
-       }
-       puts("\n       ");
-
-       unit_type = (val & 0xf000) >> 12;
-       hardware_cpu_ports = ((val & 0x0f00) >> 8) * 8;
-       hardware_con_ports = ((val & 0x00f0) >> 4) * 2;
-       hardware_version = val & 0x000f;
-
-       switch (unit_type) {
-       case HWTYPE_CCX16:
-               printf("CCX16-FPGA (80 UARTs)");
-               break;
-
-       default:
-               printf("UnitType %d, unsupported", unit_type);
-               break;
-       }
-
-       printf(", %d cpu ports, %d console ports,",
-              hardware_cpu_ports, hardware_con_ports);
-
-       switch (hardware_version) {
-       case HWREV_300:
-               printf(" HW-Ver 3.00\n");
-               break;
-
-       default:
-               printf(" HW-Ver %d, unsupported\n",
-                      hardware_version);
-               break;
-       }
-
-       return 0;
-}

diff --git a/boards.cfg b/boards.cfg
index 3cf75c3..24c5879 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -982,7 +982,7 @@ intip                        powerpc     ppc4xx      intip               gdsys
 io                           powerpc     ppc4xx      405ep               gdsys
 io64                         powerpc     ppc4xx      405ex               gdsys
 iocon                        powerpc     ppc4xx      405ep               gdsys
 io                           powerpc     ppc4xx      405ep               gdsys
 io64                         powerpc     ppc4xx      405ex               gdsys
 iocon                        powerpc     ppc4xx      405ep               gdsys

-neo                          powerpc     ppc4xx      -                   gdsys
+neo                          powerpc     ppc4xx      405ep               gdsys

 icon                         powerpc     ppc4xx      -                   mosaixtech
 MIP405                       powerpc     ppc4xx      mip405              mpl
 MIP405T                      powerpc     ppc4xx      mip405              mpl            -           MIP405:MIP405T
 icon                         powerpc     ppc4xx      -                   mosaixtech
 MIP405                       powerpc     ppc4xx      mip405              mpl
 MIP405T                      powerpc     ppc4xx      mip405              mpl            -           MIP405:MIP405T

diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 1468197..cd64e3a 100644 (file)
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -37,7 +37,8 @@
 #define CONFIG_IDENT_STRING    " dlvision-10g 0.02"
 #include "amcc-common.h"
 
 #define CONFIG_IDENT_STRING    " dlvision-10g 0.02"
 #include "amcc-common.h"
 

-#define CONFIG_BOARD_EARLY_INIT_F      /* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R

 #define CONFIG_LAST_STAGE_INIT
 
 #define CONFIG_SYS_CLK_FREQ    33333333 /* external frequency to pll   */
 #define CONFIG_LAST_STAGE_INIT
 
 #define CONFIG_SYS_CLK_FREQ    33333333 /* external frequency to pll   */

diff --git a/include/configs/io.h b/include/configs/io.h
index 9d2a87d..fe07ca5 100644 (file)
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -37,8 +37,9 @@
 #define CONFIG_IDENT_STRING    " io 0.04"
 #include "amcc-common.h"
 
 #define CONFIG_IDENT_STRING    " io 0.04"
 #include "amcc-common.h"
 

-#define CONFIG_BOARD_EARLY_INIT_F      /* call board_early_init_f */
-#define CONFIG_LAST_STAGE_INIT         /* call last_stage_init */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_LAST_STAGE_INIT

 
 #define CONFIG_SYS_CLK_FREQ    33333333 /* external frequency to pll   */
 
 
 #define CONFIG_SYS_CLK_FREQ    33333333 /* external frequency to pll   */
 

diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 9fcc643..bbf79e7 100644 (file)
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -37,7 +37,8 @@
 #define CONFIG_IDENT_STRING    " iocon 0.03"
 #include "amcc-common.h"
 
 #define CONFIG_IDENT_STRING    " iocon 0.03"
 #include "amcc-common.h"
 

-#define CONFIG_BOARD_EARLY_INIT_F      /* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R

 #define CONFIG_LAST_STAGE_INIT
 
 #define CONFIG_SYS_CLK_FREQ    33333333 /* external frequency to pll   */
 #define CONFIG_LAST_STAGE_INIT
 
 #define CONFIG_SYS_CLK_FREQ    33333333 /* external frequency to pll   */

diff --git a/include/configs/neo.h b/include/configs/neo.h
index 6559353..38b5bec 100644 (file)
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -35,9 +35,13 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME                neo
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME                neo

+#define CONFIG_IDENT_STRING    " neo 0.01"

 #include "amcc-common.h"
 
 #include "amcc-common.h"
 

-#define CONFIG_BOARD_EARLY_INIT_F      /* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT

 
 #define CONFIG_SYS_CLK_FREQ    33333333 /* external frequency to pll   */
 
 
 #define CONFIG_SYS_CLK_FREQ    33333333 /* external frequency to pll   */
 


@@ -149,53 +153,53 @@
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE   0x20000 /* size of one complete sector          */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE   0x20000 /* size of one complete sector          */

-#define CONFIG_ENV_ADDR                ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR                0xFFF00000

 #define        CONFIG_ENV_SIZE         0x20000 /* Total Size of Environment Sector */
 
 /* Address and size of Redundant Environment Sector    */
 #define        CONFIG_ENV_SIZE         0x20000 /* Total Size of Environment Sector */
 
 /* Address and size of Redundant Environment Sector    */

-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND 0xFFF20000

 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
 #endif
 
 /*
  * PPC405 GPIO Configuration
  */
 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
 #endif
 
 /*
  * PPC405 GPIO Configuration
  */

-#define CONFIG_SYS_4xx_GPIO_TABLE { /*                         GPIO    Alternate1      */      \
-{                                                                                      \
-/* GPIO Core 0 */                                                                      \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0  PerBLast        */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1  TS1E            */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2  TS2E            */      \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3  TS1O            */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4  TS2O            */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO5  TS3             */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6  TS4             */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7  TS5             */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8  TS6             */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9  TrcClk          */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1          */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2          */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3          */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4          */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03       */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04       */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05       */      \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0            */      \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1            */      \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2            */      \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3            */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4            */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5            */      \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6            */      \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD       */      \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR       */      \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI        */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR       */      \
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx        */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx        */      \
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0      */      \
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1      */      \
-}                                                                                      \
+#define CONFIG_SYS_4xx_GPIO_TABLE { \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0  PerBLast   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1  TS1E       */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2  TS2E       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3  TS1O       */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4  TS2O       */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5  TS3        */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6  TS4        */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7  TS5        */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8  TS6        */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9  TrcClk     */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1     */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2     */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3     */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4     */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03  */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04  */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3       */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4       */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
+} \

 }
 
 /*
 }
 
 /*


@@ -226,12 +230,22 @@
 #define CONFIG_SYS_EBC_PB1CR           0xFB85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 2 (FPGA) initialization                 */
 #define CONFIG_SYS_EBC_PB1CR           0xFB85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 2 (FPGA) initialization                 */

-#define CONFIG_FPGA_BASE       0x7f100000
+#define CONFIG_SYS_FPGA0_BASE          0x7f100000

 #define CONFIG_SYS_EBC_PB2AP           0x92015480
 #define CONFIG_SYS_EBC_PB2CR           0x7f11a000  /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 
 #define CONFIG_SYS_EBC_PB2AP           0x92015480
 #define CONFIG_SYS_EBC_PB2CR           0x7f11a000  /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 

+#define CONFIG_SYS_FPGA_BASE(k)                CONFIG_SYS_FPGA0_BASE
+
+#define CONFIG_SYS_FPGA_COUNT          1
+

 /* Memory Bank 3 (Latches) initialization                      */
 /* Memory Bank 3 (Latches) initialization                      */

+#define CONFIG_SYS_LATCH_BASE          0x7f200000

 #define CONFIG_SYS_EBC_PB3AP           0x92015480
 #define CONFIG_SYS_EBC_PB3CR           0x7f21a000  /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
 
 #define CONFIG_SYS_EBC_PB3AP           0x92015480
 #define CONFIG_SYS_EBC_PB3CR           0x7f21a000  /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
 

+#define CONFIG_SYS_LATCH0_RESET                0xffff
+#define CONFIG_SYS_LATCH0_BOOT         0xffff
+#define CONFIG_SYS_LATCH1_RESET                0xffbf
+#define CONFIG_SYS_LATCH1_BOOT         0xffff
+

 #endif /* __CONFIG_H */
 #endif /* __CONFIG_H */

diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 949864c..555fbe2 100644 (file)
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -58,6 +58,17 @@ typedef struct ihs_osd {
        u16 y_pos;
 } ihs_osd_t;
 
        u16 y_pos;
 } ihs_osd_t;
 

+#ifdef CONFIG_NEO
+typedef struct ihs_fpga {
+       u16 reflection_low;     /* 0x0000 */
+       u16 versions;           /* 0x0002 */
+       u16 fpga_features;      /* 0x0004 */
+       u16 fpga_version;       /* 0x0006 */
+       u16 reserved_0[8187];   /* 0x0008 */
+       u16 reflection_high;    /* 0x3ffe */
+} ihs_fpga_t;
+#endif
+

 #ifdef CONFIG_IO
 typedef struct ihs_fpga {
        u16 reflection_low;     /* 0x0000 */
 #ifdef CONFIG_IO
 typedef struct ihs_fpga {
        u16 reflection_low;     /* 0x0000 */