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drm/radeon/cik: use hw defaults for TC_CFG registers
author
Alex Deucher
<alexander.deucher@amd.com>
Mon, 13 Jan 2014 15:18:03 +0000
(10:18 -0500)
committer
Alex Deucher
<alexander.deucher@amd.com>
Mon, 20 Jan 2014 17:05:16 +0000
(12:05 -0500)
Use the hw power up values rather than 0.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/cik.c
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diff --git
a/drivers/gpu/drm/radeon/cik.c
b/drivers/gpu/drm/radeon/cik.c
index
e8ec15d
..
6ffe824
100644
(file)
--- a/
drivers/gpu/drm/radeon/cik.c
+++ b/
drivers/gpu/drm/radeon/cik.c
@@
-5353,20
+5353,6
@@
static int cik_pcie_gart_enable(struct radeon_device *rdev)
WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
- /* TC cache setup ??? */
- WREG32(TC_CFG_L1_LOAD_POLICY0, 0);
- WREG32(TC_CFG_L1_LOAD_POLICY1, 0);
- WREG32(TC_CFG_L1_STORE_POLICY, 0);
-
- WREG32(TC_CFG_L2_LOAD_POLICY0, 0);
- WREG32(TC_CFG_L2_LOAD_POLICY1, 0);
- WREG32(TC_CFG_L2_STORE_POLICY0, 0);
- WREG32(TC_CFG_L2_STORE_POLICY1, 0);
- WREG32(TC_CFG_L2_ATOMIC_POLICY, 0);
-
- WREG32(TC_CFG_L1_VOLATILE, 0);
- WREG32(TC_CFG_L2_VOLATILE, 0);
-
if (rdev->family == CHIP_KAVERI) {
u32 tmp = RREG32(CHUB_CONTROL);
tmp &= ~BYPASS_VM;
if (rdev->family == CHIP_KAVERI) {
u32 tmp = RREG32(CHUB_CONTROL);
tmp &= ~BYPASS_VM;