powerpc/85xx: Change timebase divisor to be defined per processor

Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts.  All the PQ3 parts are
/8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/README b/README
index 157cc9e..2754d1e 100644 (file)
--- a/README
+++ b/README
@@ -356,6 +356,13 @@ The following options need to be configured:
                Define this option if you want to enable the
                ICache only when Code runs from RAM.
 
                Define this option if you want to enable the
                ICache only when Code runs from RAM.
 

+- 85xx CPU Options:
+               CONFIG_SYS_FSL_TBCLK_DIV
+
+               Defines the core time base clock divider ratio compared to the
+               system clock.  On most PQ3 devices this is 8, on newer QorIQ
+               devices it can be 16 or 32.  The ratio varies from SoC to Soc.
+

 - Intel Monahans options:
                CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
 - Intel Monahans options:
                CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index f5b39c0..f863f4a 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -234,13 +234,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 /*
  * Get timebase clock frequency
  */
 /*
  * Get timebase clock frequency
  */

+#ifndef CONFIG_SYS_FSL_TBCLK_DIV
+#define CONFIG_SYS_FSL_TBCLK_DIV 8
+#endif

 unsigned long get_tbclk (void)
 {
 unsigned long get_tbclk (void)
 {

-#ifdef CONFIG_FSL_CORENET
-       return (gd->bus_clk + 8) / 16;
-#else
-       return (gd->bus_clk + 4UL)/8UL;
-#endif
+       unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
+
+       return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;

 }
 
 
 }
 
 

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index ccf703b..41c2d20 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -264,6 +264,7 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000

+#define CONFIG_SYS_FSL_TBCLK_DIV       32

 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111


@@ -278,6 +279,7 @@
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000

+#define CONFIG_SYS_FSL_TBCLK_DIV       32

 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111


@@ -288,6 +290,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS                32
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_NUM_LAWS                32
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000

+#define CONFIG_SYS_FSL_TBCLK_DIV       16

 
 #elif defined(CONFIG_PPC_P4080)
 #define CONFIG_MAX_CPUS                        8
 
 #elif defined(CONFIG_PPC_P4080)
 #define CONFIG_MAX_CPUS                        8


@@ -301,6 +304,7 @@
 #define CONFIG_SYS_NUM_FM2_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     2
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_NUM_FM2_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     2
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000

+#define CONFIG_SYS_FSL_TBCLK_DIV       16

 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003


@@ -325,6 +329,7 @@
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000

+#define CONFIG_SYS_FSL_TBCLK_DIV       32

 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111


@@ -339,6 +344,7 @@
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     2
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_NUM_FM1_10GEC       1
 #define CONFIG_NUM_DDR_CONTROLLERS     2
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000

+#define CONFIG_SYS_FSL_TBCLK_DIV       32

 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111