MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout;
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout;
+ unsigned int freq, pll_div2_sel, mpll_fout_sel;
switch (pllreg) {
case APLL:
switch (pllreg) {
case APLL:
fout = m * (freq / (p * (1 << (s - 1))));
}
fout = m * (freq / (p * (1 << (s - 1))));
}
+ /* According to the user manual, in EVT1 MPLL always gives
+ * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
+ if (pllreg == MPLL) {
+ pll_div2_sel = readl(&clk->pll_div2_sel);
+ mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+ & MPLL_FOUT_SEL_MASK;
+ if (mpll_fout_sel == 0)
+ fout /= 2;
+ }
+
unsigned char res123[0xf5d8];
};
#endif
unsigned char res123[0xf5d8];
};
#endif
+
+#define MPLL_FOUT_SEL_SHIFT 4
+#define MPLL_FOUT_SEL_MASK 0x1