#define BH OP_IMREG, bh_reg
#define AX OP_IMREG, ax_reg
#define DX OP_IMREG, dx_reg
#define BH OP_IMREG, bh_reg
#define AX OP_IMREG, ax_reg
#define DX OP_IMREG, dx_reg
#define indirDX OP_IMREG, indir_dx_reg
#define Sw OP_SEG, w_mode
#define indirDX OP_IMREG, indir_dx_reg
#define Sw OP_SEG, w_mode
#define Ov OP_OFF64, v_mode
#define Xb OP_DSreg, eSI_reg
#define Xv OP_DSreg, eSI_reg
#define Ov OP_OFF64, v_mode
#define Xb OP_DSreg, eSI_reg
#define Xv OP_DSreg, eSI_reg
#define Yb OP_ESreg, eDI_reg
#define Yv OP_ESreg, eDI_reg
#define DSBX OP_DSreg, eBX_reg
#define Yb OP_ESreg, eDI_reg
#define Yv OP_ESreg, eDI_reg
#define DSBX OP_DSreg, eBX_reg
#define Xvr REP_Fixup, eSI_reg
#define Ybr REP_Fixup, eDI_reg
#define Yvr REP_Fixup, eDI_reg
#define Xvr REP_Fixup, eSI_reg
#define Ybr REP_Fixup, eDI_reg
#define Yvr REP_Fixup, eDI_reg
#define indirDXr REP_Fixup, indir_dx_reg
#define ALr REP_Fixup, al_reg
#define eAXr REP_Fixup, eAX_reg
#define indirDXr REP_Fixup, indir_dx_reg
#define ALr REP_Fixup, al_reg
#define eAXr REP_Fixup, eAX_reg
#define f_mode 13 /* 4- or 6-byte pointer operand */
#define const_1_mode 14
#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
#define f_mode 13 /* 4- or 6-byte pointer operand */
#define const_1_mode 14
#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
. size prefix
'E' => print 'e' if 32-bit form of jcxz
'F' => print 'w' or 'l' depending on address size prefix (loop insns)
. size prefix
'E' => print 'e' if 32-bit form of jcxz
'F' => print 'w' or 'l' depending on address size prefix (loop insns)
'H' => print ",pt" or ",pn" branch hint
'I' => honor following macro letter even in Intel mode (implemented only
. for some of the macro letters)
'H' => print ",pt" or ",pn" branch hint
'I' => honor following macro letter even in Intel mode (implemented only
. for some of the macro letters)
{ "pushT", sIb, XX, XX, XX },
{ "imulS", Gv, Ev, sIb, XX },
{ "ins{b||b|}", Ybr, indirDX, XX, XX },
{ "pushT", sIb, XX, XX, XX },
{ "imulS", Gv, Ev, sIb, XX },
{ "ins{b||b|}", Ybr, indirDX, XX, XX },
- { "ins{R||R|}", Yvr, indirDX, XX, XX },
+ { "ins{R||G|}", Yzr, indirDX, XX, XX },
{ "outs{b||b|}", indirDXr, Xb, XX, XX },
{ "outs{b||b|}", indirDXr, Xb, XX, XX },
- { "outs{R||R|}", indirDXr, Xv, XX, XX },
+ { "outs{R||G|}", indirDXr, Xz, XX, XX },
/* 70 */
{ "joH", Jb, XX, cond_jump_flag, XX },
{ "jnoH", Jb, XX, cond_jump_flag, XX },
/* 70 */
{ "joH", Jb, XX, cond_jump_flag, XX },
{ "jnoH", Jb, XX, cond_jump_flag, XX },
{ "loopFH", Jb, XX, loop_jcxz_flag, XX },
{ "jEcxzH", Jb, XX, loop_jcxz_flag, XX },
{ "inB", AL, Ib, XX, XX },
{ "loopFH", Jb, XX, loop_jcxz_flag, XX },
{ "jEcxzH", Jb, XX, loop_jcxz_flag, XX },
{ "inB", AL, Ib, XX, XX },
- { "inS", eAX, Ib, XX, XX },
+ { "inG", zAX, Ib, XX, XX },
{ "outB", Ib, AL, XX, XX },
{ "outB", Ib, AL, XX, XX },
- { "outS", Ib, eAX, XX, XX },
+ { "outG", Ib, zAX, XX, XX },
/* e8 */
{ "callT", Jv, XX, XX, XX },
{ "jmpT", Jv, XX, XX, XX },
{ "Jjmp{T|}", Ap, XX, XX, XX },
{ "jmp", Jb, XX, XX, XX },
{ "inB", AL, indirDX, XX, XX },
/* e8 */
{ "callT", Jv, XX, XX, XX },
{ "jmpT", Jv, XX, XX, XX },
{ "Jjmp{T|}", Ap, XX, XX, XX },
{ "jmp", Jb, XX, XX, XX },
{ "inB", AL, indirDX, XX, XX },
- { "inS", eAX, indirDX, XX, XX },
+ { "inG", zAX, indirDX, XX, XX },
{ "outB", indirDX, AL, XX, XX },
{ "outB", indirDX, AL, XX, XX },
- { "outS", indirDX, eAX, XX, XX },
+ { "outG", indirDX, zAX, XX, XX },
/* f0 */
{ "(bad)", XX, XX, XX, XX }, /* lock prefix */
{ "icebp", XX, XX, XX, XX },
/* f0 */
{ "(bad)", XX, XX, XX, XX }, /* lock prefix */
{ "icebp", XX, XX, XX, XX },
case ax_reg: case cx_reg: case dx_reg: case bx_reg:
case sp_reg: case bp_reg: case si_reg: case di_reg:
s = names16[code - ax_reg + add];
case ax_reg: case cx_reg: case dx_reg: case bx_reg:
case sp_reg: case bp_reg: case si_reg: case di_reg:
s = names16[code - ax_reg + add];
- intel_operand_size (codep[-1] & 1 ? v_mode : b_mode, sizeflag);
+ {
+ switch (codep[-1])
+ {
+ case 0x6d: /* insw/insl */
+ intel_operand_size (z_mode, sizeflag);
+ break;
+ case 0xa5: /* movsw/movsl/movsq */
+ case 0xa7: /* cmpsw/cmpsl/cmpsq */
+ case 0xab: /* stosw/stosl */
+ case 0xaf: /* scasw/scasl */
+ intel_operand_size (v_mode, sizeflag);
+ break;
+ default:
+ intel_operand_size (b_mode, sizeflag);
+ }
+ }
oappend ("%es:" + intel_syntax);
ptr_reg (code, sizeflag);
}
oappend ("%es:" + intel_syntax);
ptr_reg (code, sizeflag);
}
- intel_operand_size (codep[-1] != 0xd7 && (codep[-1] & 1)
- ? v_mode
- : b_mode,
- sizeflag);
+ {
+ switch (codep[-1])
+ {
+ case 0x6f: /* outsw/outsl */
+ intel_operand_size (z_mode, sizeflag);
+ break;
+ case 0xa5: /* movsw/movsl/movsq */
+ case 0xa7: /* cmpsw/cmpsl/cmpsq */
+ case 0xad: /* lodsw/lodsl/lodsq */
+ intel_operand_size (v_mode, sizeflag);
+ break;
+ default:
+ intel_operand_size (b_mode, sizeflag);
+ }
+ }